/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypesGeneric.cpp | 58 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST() 59 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST() 69 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST() 70 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST() 77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST() 78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST() 83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST() 84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST() 96 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST() 230 SDValue NewVec = DAG.getNode(ISD::BITCAST, dl, in ExpandRes_EXTRACT_VECTOR_ELT() [all …]
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H A D | LegalizeVectorOps.cpp | 630 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res); in Promote() 959 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); in ExpandSELECT() 960 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); in ExpandSELECT() 969 return DAG.getNode(ISD::BITCAST, DL, Node->getValueType(0), Val); in ExpandSELECT() 1024 ISD::BITCAST, DL, VT, in ExpandANY_EXTEND_VECTOR_INREG() 1087 return DAG.getNode(ISD::BITCAST, DL, VT, in ExpandZERO_EXTEND_VECTOR_INREG() 1113 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in ExpandBSWAP() 1147 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op); in ExpandBITREVERSE() 1201 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); in ExpandVSELECT() 1202 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); in ExpandVSELECT() [all …]
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H A D | LegalizeDAG.cpp | 532 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); in LegalizeStoreOps() 704 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res); in LegalizeLoadOps() 2855 case ISD::BITCAST: in ExpandNode() 3024 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); in ExpandNode() 3025 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); in ExpandNode() 4462 TruncOp = ISD::BITCAST; in PromoteNode() 4497 ExtOp = ISD::BITCAST; in PromoteNode() 4498 TruncOp = ISD::BITCAST; in PromoteNode() 4547 ExtOp = ISD::BITCAST; in PromoteNode() 4548 TruncOp = ISD::BITCAST; in PromoteNode() [all …]
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H A D | LegalizeVectorTypes.cpp | 300 return DAG.getNode(ISD::BITCAST, SDLoc(N), in ScalarizeVecRes_BITCAST() 603 case ISD::BITCAST: in ScalarizeVectorOperand() 689 return DAG.getNode(ISD::BITCAST, SDLoc(N), in ScalarizeVecOp_BITCAST() 1189 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); in SplitVecRes_BITCAST() 1190 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST() 1198 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); in SplitVecRes_BITCAST() 1199 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST() 1215 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); in SplitVecRes_BITCAST() 1216 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST() 3819 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); in WidenVecRes_BITCAST() [all …]
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H A D | SelectionDAGBuilder.cpp | 270 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromParts() 300 Val = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Val); in getCopyFromParts() 431 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromPartsVector() 529 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in getCopyToParts() 538 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in getCopyToParts() 550 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in getCopyToParts() 582 Parts[0] = DAG.getNode(ISD::BITCAST, DL, in getCopyToParts() 662 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in getCopyToPartsVector() 3492 setValue(&I, DAG.getNode(ISD::BITCAST, dl, in visitBitCast() 4991 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, in getLimitedPrecisionExp2() [all …]
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H A D | LegalizeFloatTypes.cpp | 62 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; in SoftenFloatResult() 813 case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break; in SoftenFloatOperand() 859 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Op0); in SoftenFloatOp_BITCAST() 1179 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; in ExpandFloatResult() 1763 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break; in ExpandFloatOperand() 2080 case ISD::BITCAST: R = PromoteFloatOp_BITCAST(N, OpNo); break; in PromoteFloatOperand() 2219 case ISD::BITCAST: R = PromoteFloatRes_BITCAST(N); break; in PromoteFloatResult() 2581 case ISD::BITCAST: R = SoftPromoteHalfRes_BITCAST(N); break; in SoftPromoteHalfResult() 2876 case ISD::BITCAST: Res = SoftPromoteHalfOp_BITCAST(N); break; in SoftPromoteHalfOperand() 2905 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Op0); in SoftPromoteHalfOp_BITCAST()
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H A D | LegalizeTypes.cpp | 872 return DAG.getNode(ISD::BITCAST, SDLoc(Op), in BitConvertToInteger() 882 return DAG.getNode(ISD::BITCAST, SDLoc(Op), in BitConvertVectorToIntegerVector()
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H A D | SelectionDAG.cpp | 173 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllOnes() 222 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllZeros() 1875 while (V.getOpcode() == ISD::BITCAST) in getVectorShuffle() 2923 case ISD::BITCAST: { in computeKnownBits() 3757 case ISD::BITCAST: { in ComputeNumSignBits() 4627 case ISD::BITCAST: in getNode() 4723 case ISD::BITCAST: in getNode() 4961 case ISD::BITCAST: in getNode() 6092 case ISD::BITCAST: in getNode() 6218 return DAG.getNode(ISD::BITCAST, dl, VT, in getMemsetStringVal() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 548 setTargetDAGCombine(ISD::BITCAST); in AMDGPUTargetLowering() 643 case ISD::BITCAST: in hasSourceMods() 1358 return DAG.getNode(ISD::BITCAST, SL, VT, BV); in LowerCONCAT_VECTORS() 1946 REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM); in LowerUDIVREM64() 1977 DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV); in LowerUDIVREM64() 2475 R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R); in LowerINT_TO_FP32() 3044 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in splitBinaryBitConstantOpImpl() 3112 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in performShlCombine() 3214 Elt0 = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine() 3235 SrcElt = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine() [all …]
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H A D | SIISelLowering.cpp | 254 case ISD::BITCAST: in SITargetLowering() 577 case ISD::BITCAST: in SITargetLowering() 5465 return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI); in lowerINSERT_VECTOR_ELT() 5613 return DAG.getNode(ISD::BITCAST, SL, VT, Or); in lowerBUILD_VECTOR() 7714 DAG.getNode(ISD::BITCAST, DL, in LowerINTRINSIC_VOID() 7761 DAG.getNode(ISD::BITCAST, DL, in LowerINTRINSIC_VOID() 8017 Cvt = DAG.getNode(ISD::BITCAST, SL, VT, Cvt); in widenLoad() 8219 return DAG.getNode(ISD::BITCAST, DL, VT, Res); in LowerSELECT() 9418 if (Src.getOpcode() == ISD::BITCAST) { in performZeroExtendCombine() 9621 case ISD::BITCAST: in isCanonicalized() [all …]
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H A D | R600ISelLowering.cpp | 945 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC() 946 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC() 965 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC() 1858 if (Arg.getOpcode() == ISD::BITCAST && in PerformDAGCombine() 1864 return DAG.getNode(ISD::BITCAST, DL, N->getVTList(), in PerformDAGCombine()
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H A D | AMDGPUISelLowering.h | 148 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val; in stripBitcast()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 993 setTargetDAGCombine(ISD::BITCAST); in ARMTargetLowering() 2083 Val = DAG.getNode(ISD::BITCAST, dl, in MoveFromHPR() 6254 while (Op.getOpcode() == ISD::BITCAST) in getVShiftImm() 8935 if (N->getOpcode() == ISD::BITCAST) { in SkipExtensionForVMULL() 9997 case ISD::BITCAST: in ReplaceNodeResults() 13050 if (VMov->getOpcode() == ISD::BITCAST) in PerformSUBCombine() 14031 if (Op0.getOpcode() == ISD::BITCAST) in PerformVMOVDRRCombine() 14033 if (Op1.getOpcode() == ISD::BITCAST) in PerformVMOVDRRCombine() 14242 if (V.getOpcode() == ISD::BITCAST && in PerformARMBUILD_VECTORCombine() 14393 if (Ext.getOpcode() == ISD::BITCAST && in PerformExtractEltToVMOVRRD() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 504 setOperationAction(ISD::BITCAST, MVT::f32, Legal); in PPCTargetLowering() 505 setOperationAction(ISD::BITCAST, MVT::i32, Legal); in PPCTargetLowering() 506 setOperationAction(ISD::BITCAST, MVT::i64, Legal); in PPCTargetLowering() 3474 ISD::BITCAST, dl, MVT::v2i64, in LowerSETCC() 8898 return DAG.getNode(ISD::BITCAST, dl, VT, T); in BuildVSLDOI() 8972 if (InputLoad->getOpcode() == ISD::BITCAST) in getNormalLoadInput() 9364 return DAG.getNode(ISD::BITCAST, dl, VT, T); in GeneratePerfectShuffle() 10932 case ISD::BITCAST: in ReplaceNodeResults() 14376 if (Op.getOpcode() != ISD::BITCAST) in isScalarToVec() 14879 if (Bitcast->getOpcode() != ISD::BITCAST || in PerformDAGCombine() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 346 setOperationAction(ISD::BITCAST, VT, Legal); in SystemZTargetLowering() 4498 if (N->getOpcode() == ISD::BITCAST) in isZeroVector() 4647 if (Op.getOpcode() == ISD::BITCAST) in add() 4771 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in getNode() 5223 Op1.getOpcode() != ISD::BITCAST && in lowerINSERT_VECTOR_ELT() 5238 return DAG.getNode(ISD::BITCAST, DL, VT, Res); in lowerINSERT_VECTOR_ELT() 5395 case ISD::BITCAST: in LowerOperation() 5735 if (Opcode == ISD::BITCAST) in combineExtract() 5948 if (Op0.getOpcode() == ISD::BITCAST) in combineMERGE() 6150 if (Op.getOpcode() == ISD::BITCAST && in combineEXTRACT_VECTOR_ELT() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 450 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); in LowerFormalArguments_32() 813 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall_32() 856 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg); in LowerCall_32() 905 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_32() 1529 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in SparcTargetLowering() 1530 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in SparcTargetLowering() 1567 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in SparcTargetLowering() 1568 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in SparcTargetLowering() 1810 setTargetDAGCombine(ISD::BITCAST); in SparcTargetLowering() 2362 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in LowerFP_TO_SINT() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEISelDAGToDAG.cpp | 556 if (N->getOpcode() == ISD::BITCAST) in selectVSplatCommon() 632 if (N->getOpcode() == ISD::BITCAST) in selectVSplatUimmPow2() 663 if (N->getOpcode() == ISD::BITCAST) in selectVSplatMaskL() 697 if (N->getOpcode() == ISD::BITCAST) in selectVSplatMaskR() 719 if (N->getOpcode() == ISD::BITCAST) in selectVSplatUimmInvPow2()
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H A D | MipsISelLowering.cpp | 2328 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : in lowerFCOPYSIGN32() 2332 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : in lowerFCOPYSIGN32() 2372 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); in lowerFCOPYSIGN64() 2446 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); in lowerFABS32() 2476 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); in lowerFABS64() 3286 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); in LowerCall() 3303 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); in LowerCall() 3519 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); in LowerCallResult() 3593 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); in UnpackFromArgumentSlot() 3680 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); in LowerFormalArguments() [all …]
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H A D | MipsSEISelLowering.cpp | 99 setOperationAction(ISD::BITCAST, VecTys[i], Legal); in MipsSETargetLowering() 219 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in MipsSETargetLowering() 325 setOperationAction(ISD::BITCAST, Ty, Legal); in addMSAIntType() 381 setOperationAction(ISD::BITCAST, Ty, Legal); in addMSAFloatType() 469 case ISD::BITCAST: return lowerBITCAST(Op, DAG); in LowerOperation() 557 if (N->getOpcode() == ISD::BITCAST) in isVectorAllOnes() 1411 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, in lowerMSASplatZExt() 1458 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result); in getBuildVectorSplat() 1484 ISD::BITCAST, DL, MVT::v2i64, in lowerMSABinaryBitImmIntr() 2509 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result); in lowerBUILD_VECTOR()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1462 setOperationAction(ISD::BITCAST, VT, Custom); in addTypeForFixedLengthSVE() 2206 while (N->getOpcode() == ISD::BITCAST) in isZerosVector() 4467 case ISD::BITCAST: in LowerOperation() 8953 if (BitCast.getOpcode() != ISD::BITCAST || in constructDup() 9266 return DAG.getNode(ISD::BITCAST, DL, VT, TBL); in LowerDUPQLane() 10295 while (Op.getOpcode() == ISD::BITCAST) in getVShiftImm() 13148 if (N1Opc != ISD::BITCAST) in performConcatVectorsCombine() 13161 return DAG.getNode(ISD::BITCAST, dl, VT, in performConcatVectorsCombine() 13265 if (N.getOpcode() == ISD::BITCAST) in isEssentiallyExtractHighSubvector() 15509 Mask = DAG.getNode(ISD::BITCAST, DL, in performSelectCombine() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 838 BITCAST, enumerator
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 75 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in initializeHVXLowering() 76 setOperationAction(ISD::BITCAST, MVT::i32, Custom); in initializeHVXLowering() 77 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in initializeHVXLowering() 78 setOperationAction(ISD::BITCAST, MVT::v16i1, Custom); in initializeHVXLowering() 79 setOperationAction(ISD::BITCAST, MVT::v128i1, Custom); in initializeHVXLowering() 80 setOperationAction(ISD::BITCAST, MVT::i128, Custom); in initializeHVXLowering() 2106 case ISD::BITCAST: return LowerHvxBitcast(Op, DAG); in LowerHvxOperation() 2220 case ISD::BITCAST: in ReplaceHvxNodeResults()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 308 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in RISCVTargetLowering() 337 setOperationAction(ISD::BITCAST, MVT::i32, Custom); in RISCVTargetLowering() 650 setOperationAction(ISD::BITCAST, VT, Custom); in RISCVTargetLowering() 781 setOperationAction(ISD::BITCAST, VT, Custom); in RISCVTargetLowering() 790 setOperationAction(ISD::BITCAST, MVT::i8, Custom); in RISCVTargetLowering() 791 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in RISCVTargetLowering() 792 setOperationAction(ISD::BITCAST, MVT::i32, Custom); in RISCVTargetLowering() 793 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in RISCVTargetLowering() 1942 case ISD::BITCAST: { in LowerOperation() 4817 case ISD::BITCAST: { in ReplaceNodeResults() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1789 case PtrToInt: return ISD::BITCAST; in InstructionOpcodeToISD() 1790 case IntToPtr: return ISD::BITCAST; in InstructionOpcodeToISD() 1791 case BitCast: return ISD::BITCAST; in InstructionOpcodeToISD()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 1134 Op0 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op0); in PreprocessISelDAG() 1135 Op1 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op1); in PreprocessISelDAG() 1145 Res = CurDAG->getNode(ISD::BITCAST, dl, VecVT, Res); in PreprocessISelDAG() 4052 if (L.getOpcode() == ISD::BITCAST && L.hasOneUse()) { in matchVPTERNLOG() 4181 if (Op.getOpcode() == ISD::BITCAST && Op.hasOneUse()) in tryVPTERNLOG() 4392 if (N0Temp.getOpcode() == ISD::BITCAST && N0Temp.hasOneUse()) in tryVPTESTM() 4419 if (L.getOpcode() == ISD::BITCAST && L.hasOneUse()) { in tryVPTESTM() 4781 case ISD::BITCAST: in Select()
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