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Searched refs:DstVT (Results 1 – 25 of 32) sorted by relevance

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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td1769 ValueType DstVT> {
1788 !if(!eq(DstVT.Size, 1),
1813 !if(!eq(DstVT.Size, 1),
1822 !if(!eq(DstVT.Size, 1),
1909 !if(!eq(DstVT.Size, 1),
1935 !if(!eq(DstVT.Size, 1),
1962 ValueType DstVT = i32> {
1964 !if(!eq(DstVT.Size, 1),
1993 !if(!eq(DstVT.Size, 64),
2010 !if(!eq(DstVT.Size, 64),
[all …]
H A DVOP3Instructions.td18 list<dag> ret3 = [(set P.DstVT:$vdst,
23 list<dag> ret2 = [(set P.DstVT:$vdst,
27 list<dag> ret1 = [(set P.DstVT:$vdst,
41 list<dag> ret3 = [(set P.DstVT:$vdst,
46 list<dag> ret2 = [(set P.DstVT:$vdst,
51 list<dag> ret1 = [(set P.DstVT:$vdst,
62 list<dag> ret3 = [(set P.DstVT:$vdst,
67 list<dag> ret2 = [(set P.DstVT:$vdst,
71 list<dag> ret1 = [(set P.DstVT:$vdst,
80 list<dag> ret3 = [(set P.DstVT:$vdst,
[all …]
H A DVOPInstructions.td124 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
506 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
628 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
774 !subst(P.DstRC, P.DstVT, tmp)));
H A DVOP1Instructions.td51 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
98 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
100 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
102 [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]
H A DVOP2Instructions.td72 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
120 [(set P.DstVT:$vdst,
126 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FastISel.cpp1245 EVT DstVT = VA.getValVT(); in X86SelectRet() local
1247 if (SrcVT != DstVT) { in X86SelectRet()
1544 if (!TLI.isTypeLegal(DstVT)) in X86SelectZExt()
1562 if (DstVT == MVT::i64) { in X86SelectZExt()
1589 } else if (DstVT != MVT::i8) { in X86SelectZExt()
1602 if (!TLI.isTypeLegal(DstVT)) in X86SelectSExt()
1625 if (DstVT == MVT::i16) { in X86SelectSExt()
2525 if (DstVT != MVT::i8 && DstVT != MVT::i1) in X86SelectTrunc()
3628 if (DstVT.bitsGT(SrcVT)) in fastSelectInstruction()
3630 if (DstVT.bitsLT(SrcVT)) in fastSelectInstruction()
[all …]
H A DX86SelectionDAGInfo.cpp279 EVT DstVT = Dst.getValueType(); in emitConstantSizeRepmov() local
283 DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)), in emitConstantSizeRepmov()
H A DX86ISelLowering.cpp11564 DstVT = MVT::getVectorVT(DstVT, NumSrcElts); in matchShuffleAsVTRUNC()
11567 DstVT = MVT::getVectorVT(DstVT, 128 / EltSizeInBits); in matchShuffleAsVTRUNC()
11616 if (DstVT != TruncVT) in getAVX512TruncNode()
20494 (DstVT == MVT::f32 || DstVT == MVT::f64)) in LowerUINT_TO_FP()
20902 if (SrcVT == DstVT) in truncateVectorWithPACK()
21543 EVT TmpVT = DstVT; in LowerFP_TO_INT_SAT()
35051 DstVT = MVT::getVectorVT(DstVT, NumDstElts); in matchUnaryShuffle()
35316 DstVT = MaskVT; in matchBinaryShuffle()
39738 !(DstVT.isVector() && DstVT.getVectorElementType() == MVT::i1 && in combineCastedMaskArithmetic()
47649 EVT CMovVT = DstVT; in combineSextInRegCmov()
[all …]
H A DX86ISelDAGToDAG.cpp1211 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1214 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1222 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1238 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
1249 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, in PreprocessISelDAG()
1267 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1270 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1278 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1323 SDVTList VTs = CurDAG->getVTList(DstVT, MVT::Other); in PreprocessISelDAG()
1334 assert(DstVT == MemVT && "Unexpected VT!"); in PreprocessISelDAG()
[all …]
H A DX86InstrAVX512.td7043 let ExeDomain = DstVT.ExeDomain, Uses = _Uses,
7047 (ins DstVT.FRC:$src1, SrcRC:$src),
7052 (ins DstVT.FRC:$src1, x86memop:$src),
7057 (ins DstVT.RC:$src1, SrcRC:$src2),
7059 [(set DstVT.RC:$dst,
7060 (OpNode (DstVT.VT DstVT.RC:$src1), SrcRC:$src2))]>,
7066 [(set DstVT.RC:$dst,
7067 (OpNode (DstVT.VT DstVT.RC:$src1),
7085 [(set DstVT.RC:$dst,
7086 (OpNode (DstVT.VT DstVT.RC:$src1),
[all …]
H A DX86ISelLowering.h1376 std::pair<SDValue, SDValue> BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL,
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1062 MVT DstVT; in SelectIToFP() local
1064 if (!isTypeLegal(DstTy, DstVT)) in SelectIToFP()
1067 if (DstVT != MVT::f32 && DstVT != MVT::f64) in SelectIToFP()
1088 if (DstVT == MVT::f32) in SelectIToFP()
1111 if (DstVT == MVT::f32 && !Subtarget->hasFPCVT()) in SelectIToFP()
1133 if (DstVT == MVT::f32) in SelectIToFP()
1187 MVT DstVT, SrcVT; in SelectFPToI() local
1189 if (!isTypeLegal(DstTy, DstVT)) in SelectFPToI()
1192 if (DstVT != MVT::i32 && DstVT != MVT::i64) in SelectFPToI()
1234 if (DstVT == MVT::i32) in SelectFPToI()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp663 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
664 if (SrcVT == DstVT) in SimplifyMultipleUseDemandedBits()
672 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
694 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
812 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
6660 EVT DstVT = Node->getValueType(0); in expandFP_TO_SINT() local
6734 EVT DstVT = Node->getValueType(0); in expandFP_TO_UINT() local
6743 if (DstVT.isVector() && (!isOperationLegalOrCustom(SIntOpcode, DstVT) || in expandFP_TO_UINT()
6839 EVT DstVT = Node->getValueType(0); in expandUINT_TO_FP() local
7298 EVT DstVT = LD->getValueType(0); in scalarizeVectorLoad() local
[all …]
H A DFastISel.cpp1359 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectCast() local
1361 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1362 !DstVT.isSimple()) in selectCast()
1367 if (!TLI.isTypeLegal(DstVT)) in selectCast()
1407 MVT DstVT = DstEVT.getSimpleVT(); in selectBitCast() local
1414 if (SrcVT == DstVT) { in selectBitCast()
1416 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); in selectBitCast()
1427 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); in selectBitCast()
1782 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectOperator() local
1783 if (DstVT.bitsGT(SrcVT)) in selectOperator()
[all …]
H A DDAGCombiner.cpp551 SDValue foldSubToUSubSat(EVT DstVT, SDNode *N);
3161 if (DstVT == SrcVT) in getTruncatedUSUBSAT()
3162 return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS); in getTruncatedUSUBSAT()
3176 RHS = DAG.getNode(ISD::TRUNCATE, DL, DstVT, RHS); in getTruncatedUSUBSAT()
3177 LHS = DAG.getNode(ISD::TRUNCATE, DL, DstVT, LHS); in getTruncatedUSUBSAT()
3178 return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS); in getTruncatedUSUBSAT()
3183 SDValue DAGCombiner::foldSubToUSubSat(EVT DstVT, SDNode *N) { in foldSubToUSubSat() argument
3185 !(!LegalOperations || hasOperation(ISD::USUBSAT, DstVT))) in foldSubToUSubSat()
10419 EVT DstVT = N->getValueType(0); in CombineExtLoad() local
10450 !DstVT.isVector() || !DstVT.isPow2VectorType() || in CombineExtLoad()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DScalarizer.cpp695 VectorType *DstVT = dyn_cast<VectorType>(BCI.getDestTy()); in visitBitCastInst() local
697 if (!DstVT || !SrcVT) in visitBitCastInst()
700 unsigned DstNumElems = cast<FixedVectorType>(DstVT)->getNumElements(); in visitBitCastInst()
709 Res[I] = Builder.CreateBitCast(Op0[I], DstVT->getElementType(), in visitBitCastInst()
715 auto *MidTy = FixedVectorType::get(DstVT->getElementType(), FanOut); in visitBitCastInst()
741 Res[ResI] = Builder.CreateBitCast(V, DstVT->getElementType(), in visitBitCastInst()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h287 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
289 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td3608 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3610 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3668 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3676 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3681 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3685 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3689 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3691 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3700 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3704 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
[all …]
H A DMipsFastISel.cpp1099 MVT DstVT, SrcVT; in selectFPToInt() local
1104 if (!isTypeLegal(DstTy, DstVT)) in selectFPToInt()
1107 if (DstVT != MVT::i32) in selectFPToInt()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp876 auto DstVT = TLI->getValueType(DL, Dst); in getExtractWithExtendCost() local
883 if (!VecLT.second.isVector() || !TLI->isTypeLegal(DstVT)) in getExtractWithExtendCost()
889 if (DstVT.getFixedSizeInBits() < SrcVT.getFixedSizeInBits()) in getExtractWithExtendCost()
905 if (DstVT.getSizeInBits() != 64u || SrcVT.getSizeInBits() == 32u) in getExtractWithExtendCost()
H A DAArch64ISelDAGToDAG.cpp1273 EVT DstVT = N->getValueType(0); in tryIndexedLoad() local
1296 DstVT = MVT::i32; in tryIndexedLoad()
1300 if (DstVT == MVT::i64) in tryIndexedLoad()
1306 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1309 DstVT = MVT::i32; in tryIndexedLoad()
1313 if (DstVT == MVT::i64) in tryIndexedLoad()
1319 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1322 DstVT = MVT::i32; in tryIndexedLoad()
1343 SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT, in tryIndexedLoad()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1525 MVT DstVT; in SelectIToFP() local
1527 if (!isTypeLegal(Ty, DstVT)) in SelectIToFP()
1559 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
1570 MVT DstVT; in SelectFPToI() local
1572 if (!isTypeLegal(RetTy, DstVT)) in SelectFPToI()
1592 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
H A DARMISelLowering.cpp5894 EVT DstVT = BC->getValueType(0); in CombineVMOVDRRCandidateWithVecOp() local
5927 *DAG.getContext(), DstVT.getScalarType(), in CombineVMOVDRRCandidateWithVecOp()
5948 EVT DstVT = N->getValueType(0); in ExpandBITCAST() local
5951 (DstVT == MVT::f16 || DstVT == MVT::bf16)) in ExpandBITCAST()
5955 if ((DstVT == MVT::i16 || DstVT == MVT::i32) && in ExpandBITCAST()
5958 ISD::TRUNCATE, SDLoc(N), DstVT, in ExpandBITCAST()
16916 EVT DstVT = N->getValueType(0); in PerformBITCASTCombine() local
17248 !DstVT.isInteger()) in isTruncateFree()
17251 unsigned DestBits = DstVT.getSizeInBits(); in isTruncateFree()
18908 LC = RTLIB::getFPEXT(SrcVT, DstVT); in LowerFP_EXTEND()
[all …]
H A DARMISelLowering.h440 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp1281 EVT DstVT = TLI.getValueType(DL, CI->getType()); in OptimizeNoopCopyExpression() local
1284 if (SrcVT.isInteger() != DstVT.isInteger()) in OptimizeNoopCopyExpression()
1289 if (SrcVT.bitsLT(DstVT)) return false; in OptimizeNoopCopyExpression()
1297 if (TLI.getTypeAction(CI->getContext(), DstVT) == in OptimizeNoopCopyExpression()
1299 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); in OptimizeNoopCopyExpression()
1302 if (SrcVT != DstVT) in OptimizeNoopCopyExpression()

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