1//===-- VOPInstructions.td - Vector Instruction Definitions ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// dummies for outer let 10class LetDummies { 11 bit TRANS; 12 bit ReadsModeReg; 13 bit mayRaiseFPException; 14 bit isCommutable; 15 bit isConvertibleToThreeAddress; 16 bit isMoveImm; 17 bit isReMaterializable; 18 bit isAsCheapAsAMove; 19 bit VOPAsmPrefer32Bit; 20 bit FPDPRounding; 21 Predicate SubtargetPredicate; 22 string Constraints; 23 string DisableEncoding; 24 list<SchedReadWrite> SchedRW; 25 list<Register> Uses; 26 list<Register> Defs; 27} 28 29class VOP <string opName> { 30 string OpName = opName; 31} 32 33class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 34 InstSI <outs, ins, asm, pattern> { 35 36 let mayLoad = 0; 37 let mayStore = 0; 38 let hasSideEffects = 0; 39 let UseNamedOperandTable = 1; 40 let VALU = 1; 41 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 42} 43 44class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins, 45 string asm, list<dag> pattern> : 46 InstSI <outs, ins, asm, pattern>, 47 VOP <opName>, 48 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> { 49 let isPseudo = 1; 50 let isCodeGenOnly = 1; 51 let UseNamedOperandTable = 1; 52 53 string Mnemonic = opName; 54 VOPProfile Pfl = P; 55 56 string AsmOperands; 57} 58 59class VOP3Common <dag outs, dag ins, string asm = "", 60 list<dag> pattern = [], bit HasMods = 0, 61 bit VOP3Only = 0> : 62 VOPAnyCommon <outs, ins, asm, pattern> { 63 64 // Using complex patterns gives VOP3 patterns a very high complexity rating, 65 // but standalone patterns are almost always preferred, so we need to adjust the 66 // priority lower. The goal is to use a high number to reduce complexity to 67 // zero (or less than zero). 68 let AddedComplexity = -1000; 69 70 let VOP3 = 1; 71 72 let AsmVariantName = AMDGPUAsmVariants.VOP3; 73 let AsmMatchConverter = !if(HasMods, "cvtVOP3", ""); 74 75 let isCodeGenOnly = 0; 76 77 int Size = 8; 78 79 // Because SGPRs may be allowed if there are multiple operands, we 80 // need a post-isel hook to insert copies in order to avoid 81 // violating constant bus requirements. 82 let hasPostISelHook = 1; 83} 84 85class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [], 86 bit VOP3Only = 0, bit isVOP3P = 0, bit isVop3OpSel = 0> : 87 VOP_Pseudo <opName, "_e64", P, P.Outs64, 88 !if(isVop3OpSel, 89 P.InsVOP3OpSel, 90 !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)), 91 "", pattern> { 92 93 let VOP3_OPSEL = isVop3OpSel; 94 let IsPacked = P.IsPacked; 95 let IsMAI = P.IsMAI; 96 97 let AsmOperands = !if(isVop3OpSel, 98 P.AsmVOP3OpSel, 99 !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64)); 100 101 let Size = 8; 102 let mayLoad = 0; 103 let mayStore = 0; 104 let hasSideEffects = 0; 105 106 // Because SGPRs may be allowed if there are multiple operands, we 107 // need a post-isel hook to insert copies in order to avoid 108 // violating constant bus requirements. 109 let hasPostISelHook = 1; 110 111 // Using complex patterns gives VOP3 patterns a very high complexity rating, 112 // but standalone patterns are almost always preferred, so we need to adjust the 113 // priority lower. The goal is to use a high number to reduce complexity to 114 // zero (or less than zero). 115 let AddedComplexity = -1000; 116 117 let VOP3 = 1; 118 let VALU = 1; 119 let FPClamp = P.HasFPClamp; 120 let IntClamp = P.HasIntClamp; 121 let ClampLo = P.HasClampLo; 122 let ClampHi = P.HasClampHi; 123 124 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 125 126 let mayRaiseFPException = ReadsModeReg; 127 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 128 129 let AsmVariantName = AMDGPUAsmVariants.VOP3; 130 let AsmMatchConverter = 131 !if(isVOP3P, 132 "cvtVOP3P", 133 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 134 "cvtVOP3", 135 "")); 136} 137 138class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> : 139 VOP3_Pseudo<opName, P, pattern, 1, 1> { 140 let VOP3P = 1; 141} 142 143class VOP_Real<VOP_Pseudo ps> { 144 Instruction Opcode = !cast<Instruction>(NAME); 145 bit IsSingle = ps.Pfl.IsSingle; 146} 147 148class VOP3_Real <VOP_Pseudo ps, int EncodingFamily> : 149 VOP_Real <ps>, 150 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 151 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 152 153 let isPseudo = 0; 154 let isCodeGenOnly = 0; 155 let UseNamedOperandTable = 1; 156 157 let Constraints = ps.Constraints; 158 let DisableEncoding = ps.DisableEncoding; 159 160 // copy relevant pseudo op flags 161 let SubtargetPredicate = ps.SubtargetPredicate; 162 let OtherPredicates = ps.OtherPredicates; 163 let AsmMatchConverter = ps.AsmMatchConverter; 164 let AsmVariantName = ps.AsmVariantName; 165 let Constraints = ps.Constraints; 166 let DisableEncoding = ps.DisableEncoding; 167 let TSFlags = ps.TSFlags; 168 let UseNamedOperandTable = ps.UseNamedOperandTable; 169 let Uses = ps.Uses; 170 let Defs = ps.Defs; 171 let SchedRW = ps.SchedRW; 172 173 VOPProfile Pfl = ps.Pfl; 174} 175 176// XXX - Is there any reason to distinguish this from regular VOP3 177// here? 178class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily> : 179 VOP3_Real<ps, EncodingFamily>; 180 181class VOP3a<VOPProfile P> : Enc64 { 182 bits<4> src0_modifiers; 183 bits<9> src0; 184 bits<3> src1_modifiers; 185 bits<9> src1; 186 bits<3> src2_modifiers; 187 bits<9> src2; 188 bits<1> clamp; 189 bits<2> omod; 190 191 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 192 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); 193 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); 194 195 let Inst{31-26} = 0x34; //encoding 196 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 197 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 198 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 199 let Inst{60-59} = !if(P.HasOMod, omod, 0); 200 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 201 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 202 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 203} 204 205class VOP3a_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a<p> { 206 let Inst{11} = !if(p.HasClamp, clamp{0}, 0); 207 let Inst{25-17} = op; 208} 209 210class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> { 211 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 212 let Inst{25-16} = op; 213 let Inst{31-26} = 0x35; 214} 215 216class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> { 217 let Inst{25-16} = op; 218 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 219} 220 221class VOP3e_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a_gfx6_gfx7<op, p> { 222 bits<8> vdst; 223 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 224} 225 226class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> { 227 bits<8> vdst; 228 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 229} 230 231class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> { 232 bits<8> vdst; 233 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0); 234} 235 236class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 237 let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0); 238 let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0); 239 let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0); 240 let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0); 241} 242 243class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 244 let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0); 245 let Inst{12} = !if(p.HasSrc1, src1_modifiers{2}, 0); 246 let Inst{13} = !if(p.HasSrc2, src2_modifiers{2}, 0); 247 let Inst{14} = !if(p.HasDst, src0_modifiers{3}, 0); 248} 249 250// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa 251class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 252 bits<2> attrchan; 253 bits<6> attr; 254 bits<1> high; 255 256 let Inst{8} = 0; // No modifiers for src0 257 let Inst{61} = 0; 258 259 let Inst{9} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 260 let Inst{62} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 261 262 let Inst{37-32} = attr; 263 let Inst{39-38} = attrchan; 264 let Inst{40} = !if(P.HasHigh, high, 0); 265 266 let Inst{49-41} = src0; 267} 268 269class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 270 bits<6> attr; 271 bits<2> attrchan; 272 bits<1> high; 273 274 let Inst{8} = 0; 275 let Inst{9} = !if(p.HasSrc0Mods, src0_modifiers{1}, 0); 276 let Inst{37-32} = attr; 277 let Inst{39-38} = attrchan; 278 let Inst{40} = !if(p.HasHigh, high, 0); 279 let Inst{49-41} = src0; 280 let Inst{61} = 0; 281 let Inst{62} = !if(p.HasSrc0Mods, src0_modifiers{0}, 0); 282} 283 284class VOP3be <VOPProfile P> : Enc64 { 285 bits<8> vdst; 286 bits<2> src0_modifiers; 287 bits<9> src0; 288 bits<2> src1_modifiers; 289 bits<9> src1; 290 bits<2> src2_modifiers; 291 bits<9> src2; 292 bits<7> sdst; 293 bits<2> omod; 294 295 let Inst{7-0} = vdst; 296 let Inst{14-8} = sdst; 297 let Inst{31-26} = 0x34; //encoding 298 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 299 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 300 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 301 let Inst{60-59} = !if(P.HasOMod, omod, 0); 302 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 303 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 304 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 305} 306 307class VOP3Pe <bits<7> op, VOPProfile P> : Enc64 { 308 bits<8> vdst; 309 // neg, neg_hi, op_sel put in srcN_modifiers 310 bits<4> src0_modifiers; 311 bits<9> src0; 312 bits<4> src1_modifiers; 313 bits<9> src1; 314 bits<4> src2_modifiers; 315 bits<9> src2; 316 bits<1> clamp; 317 318 let Inst{7-0} = vdst; 319 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0 320 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1 321 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2 322 323 let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) 324 let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) 325 let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) 326 327 let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) 328 329 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 330 331 let Inst{22-16} = op; 332 let Inst{31-23} = 0x1a7; //encoding 333 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 334 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 335 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 336 let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) 337 let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) 338 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) 339 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) 340 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) 341} 342 343class VOP3Pe_MAI <bits<7> op, VOPProfile P, bit acc_cd = 0> : Enc64 { 344 bits<8> vdst; 345 bits<10> src0; 346 bits<10> src1; 347 bits<9> src2; 348 bits<3> blgp; 349 bits<3> cbsz; 350 bits<4> abid; 351 352 let Inst{7-0} = vdst; 353 354 let Inst{10-8} = !if(P.HasSrc1, cbsz, 0); 355 let Inst{14-11} = !if(P.HasSrc1, abid, 0); 356 357 let Inst{15} = acc_cd; 358 359 let Inst{22-16} = op; 360 let Inst{31-23} = 0x1a7; //encoding 361 let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0); 362 let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0); 363 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 364 365 let Inst{59} = !if(P.HasSrc0, src0{9}, 0); // acc(0) 366 let Inst{60} = !if(P.HasSrc1, src1{9}, 0); // acc(1) 367 368 let Inst{63-61} = !if(P.HasSrc1, blgp, 0); 369} 370 371 372class VOP3Pe_gfx10 <bits<7> op, VOPProfile P> : VOP3Pe<op, P> { 373 let Inst{31-23} = 0x198; //encoding 374} 375 376class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> { 377 let Inst{25-17} = op; 378} 379 380class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> { 381 bits<1> clamp; 382 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 383 let Inst{25-16} = op; 384 let Inst{31-26} = 0x35; 385} 386 387class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> { 388 bits<1> clamp; 389 let Inst{25-16} = op; 390 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 391} 392 393def SDWA { 394 // sdwa_sel 395 int BYTE_0 = 0; 396 int BYTE_1 = 1; 397 int BYTE_2 = 2; 398 int BYTE_3 = 3; 399 int WORD_0 = 4; 400 int WORD_1 = 5; 401 int DWORD = 6; 402 403 // dst_unused 404 int UNUSED_PAD = 0; 405 int UNUSED_SEXT = 1; 406 int UNUSED_PRESERVE = 2; 407} 408 409class VOP_SDWAe<VOPProfile P> : Enc64 { 410 bits<8> src0; 411 bits<3> src0_sel; 412 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 413 bits<3> src1_sel; 414 bits<2> src1_modifiers; 415 bits<3> dst_sel; 416 bits<2> dst_unused; 417 bits<1> clamp; 418 419 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 420 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 421 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 422 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 423 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 424 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 425 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 426 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 427 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 428 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 429} 430 431// GFX9 adds two features to SDWA: 432// 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD. 433// a. S0 and S1 indicate that source 0 and 1 respectively are SGPRs rather 434// than VGPRs (at most 1 can be an SGPR); 435// b. OMOD is the standard output modifier (result *2, *4, /2) 436// 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This 437// replaces OMOD and the dest fields with SD and SDST (SGPR destination) 438// field. 439// a. When SD=1, the SDST is used as the destination for the compare result; 440// b. When SD=0, VCC is used. 441// 442// In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA 443 444// gfx9 SDWA basic encoding 445class VOP_SDWA9e<VOPProfile P> : Enc64 { 446 bits<9> src0; // {src0_sgpr{0}, src0{7-0}} 447 bits<3> src0_sel; 448 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 449 bits<3> src1_sel; 450 bits<2> src1_modifiers; 451 bits<1> src1_sgpr; 452 453 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 454 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 455 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 456 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 457 let Inst{55} = !if(P.HasSrc0, src0{8}, 0); 458 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 459 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 460 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 461 let Inst{63} = 0; // src1_sgpr - should be specified in subclass 462} 463 464// gfx9 SDWA-A 465class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> { 466 bits<3> dst_sel; 467 bits<2> dst_unused; 468 bits<1> clamp; 469 bits<2> omod; 470 471 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 472 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 473 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 474 let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0); 475} 476 477// gfx9 SDWA-B 478class VOP_SDWA9Be<VOPProfile P> : VOP_SDWA9e<P> { 479 bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}} 480 481 let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?); 482 let Inst{47} = !if(P.EmitDst, sdst{7}, 0); 483} 484 485class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> : 486 InstSI <P.OutsSDWA, P.InsSDWA, "", pattern>, 487 VOP <opName>, 488 SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> { 489 490 let isPseudo = 1; 491 let isCodeGenOnly = 1; 492 let UseNamedOperandTable = 1; 493 494 string Mnemonic = opName; 495 string AsmOperands = P.AsmSDWA; 496 string AsmOperands9 = P.AsmSDWA9; 497 498 let Size = 8; 499 let mayLoad = 0; 500 let mayStore = 0; 501 let hasSideEffects = 0; 502 503 let VALU = 1; 504 let SDWA = 1; 505 506 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 507 508 let mayRaiseFPException = ReadsModeReg; 509 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 510 511 let SubtargetPredicate = HasSDWA; 512 let AssemblerPredicate = HasSDWA; 513 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA, 514 AMDGPUAsmVariants.Disable); 515 let DecoderNamespace = "SDWA"; 516 517 VOPProfile Pfl = P; 518} 519 520class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> : 521 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 522 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> { 523 524 let isPseudo = 0; 525 let isCodeGenOnly = 0; 526 527 let Defs = ps.Defs; 528 let Uses = ps.Uses; 529 let hasSideEffects = ps.hasSideEffects; 530 531 let Constraints = ps.Constraints; 532 let DisableEncoding = ps.DisableEncoding; 533 534 // Copy relevant pseudo op flags 535 let SubtargetPredicate = ps.SubtargetPredicate; 536 let AssemblerPredicate = ps.AssemblerPredicate; 537 let AsmMatchConverter = ps.AsmMatchConverter; 538 let AsmVariantName = ps.AsmVariantName; 539 let UseNamedOperandTable = ps.UseNamedOperandTable; 540 let DecoderNamespace = ps.DecoderNamespace; 541 let Constraints = ps.Constraints; 542 let DisableEncoding = ps.DisableEncoding; 543 let TSFlags = ps.TSFlags; 544 let SchedRW = ps.SchedRW; 545} 546 547class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 548 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> { 549 550 let isPseudo = 0; 551 let isCodeGenOnly = 0; 552 553 let Defs = ps.Defs; 554 let Uses = ps.Uses; 555 let SchedRW = ps.SchedRW; 556 let hasSideEffects = ps.hasSideEffects; 557 558 let Constraints = ps.Constraints; 559 let DisableEncoding = ps.DisableEncoding; 560 561 let SubtargetPredicate = HasSDWA9; 562 let AssemblerPredicate = HasSDWA9; 563 let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9, 564 AMDGPUAsmVariants.Disable); 565 let DecoderNamespace = "SDWA9"; 566 567 // Copy relevant pseudo op flags 568 let AsmMatchConverter = ps.AsmMatchConverter; 569 let UseNamedOperandTable = ps.UseNamedOperandTable; 570 let Constraints = ps.Constraints; 571 let DisableEncoding = ps.DisableEncoding; 572 let TSFlags = ps.TSFlags; 573 let SchedRW = ps.SchedRW; 574} 575 576class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 577 Base_VOP_SDWA9_Real <ps >, 578 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>; 579 580class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> { 581 let SubtargetPredicate = HasSDWA10; 582 let AssemblerPredicate = HasSDWA10; 583 let DecoderNamespace = "SDWA10"; 584} 585 586class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : 587 Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>; 588 589class VOP_DPPe<VOPProfile P, bit IsDPP16=0> : Enc64 { 590 bits<2> src0_modifiers; 591 bits<8> src0; 592 bits<2> src1_modifiers; 593 bits<9> dpp_ctrl; 594 bits<1> bound_ctrl; 595 bits<4> bank_mask; 596 bits<4> row_mask; 597 bit fi; 598 599 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 600 let Inst{48-40} = dpp_ctrl; 601 let Inst{50} = !if(IsDPP16, fi, ?); 602 let Inst{51} = bound_ctrl; 603 let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg 604 let Inst{53} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs 605 let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg 606 let Inst{55} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs 607 let Inst{59-56} = bank_mask; 608 let Inst{63-60} = row_mask; 609} 610 611class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 612 InstSI <P.OutsDPP, P.InsDPP, OpName#P.AsmDPP, pattern>, 613 VOP <OpName>, 614 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> { 615 616 let isPseudo = 1; 617 let isCodeGenOnly = 1; 618 619 let mayLoad = 0; 620 let mayStore = 0; 621 let hasSideEffects = 0; 622 let UseNamedOperandTable = 1; 623 624 let VALU = 1; 625 let DPP = 1; 626 let Size = 8; 627 628 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 629 630 let mayRaiseFPException = ReadsModeReg; 631 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 632 let isConvergent = 1; 633 634 string Mnemonic = OpName; 635 string AsmOperands = P.AsmDPP; 636 637 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 638 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 639 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 640 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 641 AMDGPUAsmVariants.Disable); 642 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 643 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 644 let DecoderNamespace = "DPP"; 645 646 VOPProfile Pfl = P; 647} 648 649class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> : 650 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 651 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 652 653 let isPseudo = 0; 654 let isCodeGenOnly = 0; 655 656 let Defs = ps.Defs; 657 let Uses = ps.Uses; 658 let SchedRW = ps.SchedRW; 659 let hasSideEffects = ps.hasSideEffects; 660 661 let Constraints = ps.Constraints; 662 let DisableEncoding = ps.DisableEncoding; 663 664 // Copy relevant pseudo op flags 665 let isConvergent = ps.isConvergent; 666 let SubtargetPredicate = ps.SubtargetPredicate; 667 let AssemblerPredicate = ps.AssemblerPredicate; 668 let AsmMatchConverter = ps.AsmMatchConverter; 669 let AsmVariantName = ps.AsmVariantName; 670 let UseNamedOperandTable = ps.UseNamedOperandTable; 671 let DecoderNamespace = ps.DecoderNamespace; 672 let Constraints = ps.Constraints; 673 let DisableEncoding = ps.DisableEncoding; 674 let TSFlags = ps.TSFlags; 675 let SchedRW = ps.SchedRW; 676} 677 678class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16, 679 dag InsDPP = !if(IsDPP16, P.InsDPP16, P.InsDPP), 680 string AsmDPP = !if(IsDPP16, P.AsmDPP16, P.AsmDPP)> : 681 InstSI <P.OutsDPP, InsDPP, OpName#AsmDPP, []>, 682 VOP_DPPe<P, IsDPP16> { 683 684 let mayLoad = 0; 685 let mayStore = 0; 686 let hasSideEffects = 0; 687 let UseNamedOperandTable = 1; 688 689 let VALU = 1; 690 let DPP = 1; 691 let Size = 8; 692 693 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 694 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 695 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 696 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 697 AMDGPUAsmVariants.Disable); 698 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 699 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 700 let DecoderNamespace = "DPP"; 701} 702 703class VOP_DPP8e<VOPProfile P> : Enc64 { 704 bits<8> src0; 705 bits<24> dpp8; 706 bits<9> fi; 707 708 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 709 let Inst{63-40} = dpp8{23-0}; 710} 711 712class VOP_DPP8<string OpName, VOPProfile P> : 713 InstSI<P.OutsDPP8, P.InsDPP8, OpName#P.AsmDPP8, []>, 714 VOP_DPP8e<P> { 715 716 let mayLoad = 0; 717 let mayStore = 0; 718 let hasSideEffects = 0; 719 let UseNamedOperandTable = 1; 720 721 let VALU = 1; 722 let DPP = 1; 723 let Size = 8; 724 725 let AsmMatchConverter = "cvtDPP8"; 726 let SubtargetPredicate = HasDPP8; 727 let AssemblerPredicate = HasDPP8; 728 let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP, 729 AMDGPUAsmVariants.Disable); 730 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 731 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 732} 733 734def DPP8Mode { 735 int FI_0 = 0xE9; 736 int FI_1 = 0xEA; 737} 738 739class getNumNodeArgs<SDPatternOperator Op> { 740 SDNode N = !cast<SDNode>(Op); 741 SDTypeProfile TP = N.TypeProfile; 742 int ret = TP.NumOperands; 743} 744 745 746class getDivergentFrag<SDPatternOperator Op> { 747 748 int NumSrcArgs = getNumNodeArgs<Op>.ret; 749 PatFrag ret = PatFrag < 750 !if(!eq(NumSrcArgs, 1), 751 (ops node:$src0), 752 !if(!eq(NumSrcArgs, 2), 753 (ops node:$src0, node:$src1), 754 (ops node:$src0, node:$src1, node:$src2))), 755 !if(!eq(NumSrcArgs, 1), 756 (Op $src0), 757 !if(!eq(NumSrcArgs, 2), 758 (Op $src0, $src1), 759 (Op $src0, $src1, $src2))), 760 [{ return N->isDivergent(); }] 761 >; 762} 763 764class VOPPatGen<SDPatternOperator Op, VOPProfile P> { 765 766 PatFrag Operator = getDivergentFrag < Op >.ret; 767 768 dag Ins = !foreach(tmp, P.Ins32, !subst(ins, Operator, 769 !subst(P.Src0RC32, P.Src0VT, 770 !subst(P.Src1RC32, P.Src1VT, tmp)))); 771 772 773 dag Outs = !foreach(tmp, P.Outs32, !subst(outs, set, 774 !subst(P.DstRC, P.DstVT, tmp))); 775 776 list<dag> ret = [!con(Outs, (set Ins))]; 777} 778 779class VOPPatOrNull<SDPatternOperator Op, VOPProfile P> { 780 list<dag> ret = !if(!ne(P.NeedPatGen,PatGenMode.NoPattern), VOPPatGen<Op, P>.ret, []); 781} 782 783class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> { 784 SDPatternOperator ret = !if(!eq(P.NeedPatGen,PatGenMode.Pattern), 785 !if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op); 786} 787 788class getVSrcOp<ValueType vt> { 789 RegisterOperand ret = !if(!eq(vt.Size, 32), VSrc_b32, VSrc_b16); 790} 791 792// Class for binary integer operations with the clamp bit set for saturation 793// TODO: Add sub with negated inline constant pattern. 794class VOPBinOpClampPat<SDPatternOperator node, Instruction inst, ValueType vt> : 795 GCNPat<(node vt:$src0, vt:$src1), 796 (inst getVSrcOp<vt>.ret:$src0, getVSrcOp<vt>.ret:$src1, 797 DSTCLAMP.ENABLE) 798>; 799 800 801include "VOPCInstructions.td" 802include "VOP1Instructions.td" 803include "VOP2Instructions.td" 804include "VOP3Instructions.td" 805include "VOP3PInstructions.td" 806 807 808class VOPInfoTable <string Format> : GenericTable { 809 let FilterClass = Format # "_Real"; 810 let CppTypeName = "VOPInfo"; 811 let Fields = ["Opcode", "IsSingle"]; 812 813 let PrimaryKey = ["Opcode"]; 814 let PrimaryKeyName = "get" # Format # "OpcodeHelper"; 815} 816 817def VOP1InfoTable : VOPInfoTable<"VOP1">; 818def VOP2InfoTable : VOPInfoTable<"VOP2">; 819def VOP3InfoTable : VOPInfoTable<"VOP3">; 820