| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 62 if (getOpcode() < ISD::BUILTIN_OP_END) in getOperationName()
115 case ISD::Constant: in getOperationName()
142 case ISD::INTRINSIC_WO_CHAIN: in getOperationName()
143 case ISD::INTRINSIC_VOID: in getOperationName()
144 case ISD::INTRINSIC_W_CHAIN: { in getOperationName()
157 case ISD::TargetConstant: in getOperationName()
405 case ISD::PSEUDO_PROBE: in getOperationName()
411 case ISD::PREALLOCATED_SETUP: in getOperationName()
413 case ISD::PREALLOCATED_ARG: in getOperationName()
435 case ISD::CONDCODE: in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 363 case ISD::ADD: in LegalizeOp()
364 case ISD::SUB: in LegalizeOp()
365 case ISD::MUL: in LegalizeOp()
379 case ISD::AND: in LegalizeOp()
380 case ISD::OR: in LegalizeOp()
381 case ISD::XOR: in LegalizeOp()
382 case ISD::SHL: in LegalizeOp()
383 case ISD::SRA: in LegalizeOp()
384 case ISD::SRL: in LegalizeOp()
389 case ISD::ABS: in LegalizeOp()
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| H A D | LegalizeDAG.cpp | 749 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
1668 ISD::ADD : ISD::SUB; in ExpandDYNAMIC_STACKALLOC()
2210 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3137 case ISD::SMAX: Pred = ISD::SETGT; break; in ExpandNode()
3138 case ISD::SMIN: Pred = ISD::SETLT; break; in ExpandNode()
3139 case ISD::UMAX: Pred = ISD::SETUGT; break; in ExpandNode()
3140 case ISD::UMIN: Pred = ISD::SETULT; break; in ExpandNode()
3273 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI; in ExpandNode()
3288 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS; in ExpandNode()
3416 unsigned Op = IsAdd ? ISD::ADD : ISD::SUB; in ExpandNode()
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| H A D | LegalizeIntegerTypes.cpp | 835 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB; in PromoteIntRes_ADDSUBSHLSAT()
1020 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; in PromoteIntRes_SADDSUBO()
1294 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; in PromoteIntRes_UADDSUBO()
2398 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; in ExpandShiftWithKnownAmountBit()
2400 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; in ExpandShiftWithKnownAmountBit()
2564 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY, in ExpandIntRes_ADDSUB()
3269 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT, in ExpandIntRes_LOAD()
4280 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
4282 case ISD::SETUGT: LowCC = ISD::SETUGT; break; in IntegerExpandSetCCOperands()
4284 case ISD::SETULE: LowCC = ISD::SETULE; break; in IntegerExpandSetCCOperands()
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| H A D | LegalizeFloatTypes.cpp | 2590 case ISD::FABS: in SoftPromoteHalfResult()
2593 case ISD::FCOS: in SoftPromoteHalfResult()
2594 case ISD::FEXP: in SoftPromoteHalfResult()
2597 case ISD::FLOG: in SoftPromoteHalfResult()
2601 case ISD::FNEG: in SoftPromoteHalfResult()
2606 case ISD::FSIN: in SoftPromoteHalfResult()
2612 case ISD::FADD: in SoftPromoteHalfResult()
2613 case ISD::FDIV: in SoftPromoteHalfResult()
2618 case ISD::FMUL: in SoftPromoteHalfResult()
2619 case ISD::FPOW: in SoftPromoteHalfResult()
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| H A D | TargetLowering.cpp | 3451 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in simplifySetCCWithCTPOP()
3473 unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR; in simplifySetCCWithCTPOP()
3841 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; in SimplifySetCC()
3909 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC()
3929 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
4142 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
4217 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; in SimplifySetCC()
6929 Node->getOpcode() == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT; in expandFMINNUM_FMAXNUM()
8326 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT; in expandUADDSUBO()
8406 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, in expandMULO()
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| H A D | LegalizeVectorTypes.cpp | 72 case ISD::ABS: in ScalarizeVectorResult()
111 case ISD::ADD: in ScalarizeVectorResult()
112 case ISD::AND: in ScalarizeVectorResult()
138 case ISD::MUL: in ScalarizeVectorResult()
139 case ISD::OR: in ScalarizeVectorResult()
142 case ISD::SUB: in ScalarizeVectorResult()
145 case ISD::XOR: in ScalarizeVectorResult()
146 case ISD::SHL: in ScalarizeVectorResult()
147 case ISD::SRA: in ScalarizeVectorResult()
148 case ISD::SRL: in ScalarizeVectorResult()
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| H A D | DAGCombiner.cpp | 1213 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD in PromoteOperand()
1450 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD in PromoteLoad()
3284 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA; in visitSUB()
6070 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) in isBSwapHWordElement()
6075 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL) in isBSwapHWordElement()
6096 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) { in isBSwapHWordElement()
7811 unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND; in visitXOR()
7823 unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND; in visitXOR()
10767 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; in foldExtendedSignBitTest()
15457 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB); in SplitIndexingFromLoad()
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| H A D | SelectionDAG.cpp | 438 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) { in getExtForLoadExtType()
441 return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in getExtForLoadExtType()
453 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { in getSetCCSwappedOperands()
476 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, EVT Type) { in getSetCCInverse()
480 ISD::CondCode ISD::GlobalISel::getSetCCInverse(ISD::CondCode Op, in getSetCCInverse()
504 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCOrOperation()
525 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCAndOperation()
533 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); in getSetCCAndOperation()
2242 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) in FoldSetCC()
7809 if (Opcode == ISD::FMUL || Opcode == ISD::FDIV) in simplifyFPBinop()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 271 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || in getArithmeticInstrCost()
276 if (ISD == ISD::SDIV || ISD == ISD::SREM) { in getArithmeticInstrCost()
754 ISD = ISD::MUL; in getArithmeticInstrCost()
997 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || in getArithmeticInstrCost()
998 ISD == ISD::UDIV || ISD == ISD::UREM)) { in getArithmeticInstrCost()
2792 ISD = ISD::ABS; in getTypeBasedIntrinsicInstrCost()
2801 ISD = ISD::CTLZ; in getTypeBasedIntrinsicInstrCost()
2807 ISD = ISD::CTTZ; in getTypeBasedIntrinsicInstrCost()
2818 ISD = ISD::SMAX; in getTypeBasedIntrinsicInstrCost()
2821 ISD = ISD::SMIN; in getTypeBasedIntrinsicInstrCost()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 586 case ISD::FADD: in fnegFoldsIntoOp()
587 case ISD::FSUB: in fnegFoldsIntoOp()
588 case ISD::FMUL: in fnegFoldsIntoOp()
589 case ISD::FMA: in fnegFoldsIntoOp()
820 case ISD::FMA: in getNegatedExpression()
1679 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
1680 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
2318 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF; in isCtlzOpc()
2322 return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF; in isCttzOpc()
2737 OpOpcode == ISD::FP_TO_SINT ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerFP_TO_INT()
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| H A D | R600ISelLowering.cpp | 459 case ISD::FCOS: in LowerOperation()
463 case ISD::LOAD: { in LowerOperation()
749 case ISD::FCOS: in LowerTrig()
752 case ISD::FSIN: in LowerTrig()
796 ISD::SETCC, in lowerFP_TO_UINT()
806 ISD::SETCC, in lowerFP_TO_SINT()
921 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode); in LowerSELECT_CC()
927 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT); in LowerSELECT_CC()
952 case ISD::SETNE: in LowerSELECT_CC()
1529 ISD::LoadExtType Ext = ISD::NON_EXTLOAD; in LowerFormalArguments()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 524 if ((ISD == ISD::SIGN_EXTEND || ISD == ISD::ZERO_EXTEND) && in getCastInstrCost()
552 ((ISD == ISD::FP_ROUND && SrcTy.getScalarType() == MVT::f64 && in getCastInstrCost()
554 (ISD == ISD::FP_EXTEND && SrcTy.getScalarType() == MVT::f32 && in getCastInstrCost()
746 if (ISD == ISD::FP_ROUND || ISD == ISD::FP_EXTEND) { in getCastInstrCost()
762 if (ISD == ISD::TRUNCATE && ST->hasMVEIntegerOps() && in getCastInstrCost()
844 if (CostKind == TTI::TCK_CodeSize && ISD == ISD::SELECT && in getCmpSelInstrCost()
1258 case ISD::AND: in getArithmeticInstrCost()
1259 case ISD::XOR: in getArithmeticInstrCost()
1261 case ISD::OR: in getArithmeticInstrCost()
1803 switch (ISD) { in maybeLoweredToCall()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEISelDAGToDAG.cpp | 31 case ISD::SETEQ: in intCondCode2Icc()
33 case ISD::SETNE: in intCondCode2Icc()
35 case ISD::SETLT: in intCondCode2Icc()
37 case ISD::SETGT: in intCondCode2Icc()
39 case ISD::SETLE: in intCondCode2Icc()
41 case ISD::SETGE: in intCondCode2Icc()
61 case ISD::SETEQ: in fpCondCode2Fcc()
64 case ISD::SETNE: in fpCondCode2Fcc()
67 case ISD::SETLT: in fpCondCode2Fcc()
70 case ISD::SETGT: in fpCondCode2Fcc()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 342 case ISD::SRL: in LowerOperation()
977 case ISD::SHL: in LowerShifts()
982 case ISD::SRA: in LowerShifts()
983 case ISD::SRL: in LowerShifts()
1049 case ISD::SETEQ: in EmitCMP()
1056 case ISD::SETNE: in EmitCMP()
1063 case ISD::SETULE: in EmitCMP()
1091 case ISD::SETLE: in EmitCMP()
1094 case ISD::SETGE: in EmitCMP()
1105 case ISD::SETGT: in EmitCMP()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 976 switch (ISD) { in getArithmeticInstrCost()
1045 case ISD::MUL: in getArithmeticInstrCost()
1058 case ISD::ADD: in getArithmeticInstrCost()
1059 case ISD::XOR: in getArithmeticInstrCost()
1060 case ISD::OR: in getArithmeticInstrCost()
1061 case ISD::AND: in getArithmeticInstrCost()
1110 if (isa<FixedVectorType>(ValTy) && ISD == ISD::SELECT) { in getCmpSelInstrCost()
1594 switch (ISD) { in getArithmeticReductionCostSVE()
1595 case ISD::ADD: in getArithmeticReductionCostSVE()
1596 case ISD::AND: in getArithmeticReductionCostSVE()
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| H A D | AArch64ISelLowering.cpp | 1413 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
1421 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM}) in addTypeForNEON()
2395 (CC == ISD::SETEQ || CC == ISD::SETNE); in isCMN()
2772 if (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) in getCmpOperandFoldingProfit()
2802 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; in getAArch64Cmp()
2812 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getAArch64Cmp()
2823 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getAArch64Cmp()
2834 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getAArch64Cmp()
7141 if ((CC == ISD::SETEQ || CC == ISD::SETOEQ || CC == ISD::SETUEQ) && in LowerSELECT_CC()
7144 else if ((CC == ISD::SETNE || CC == ISD::SETONE || CC == ISD::SETUNE) && in LowerSELECT_CC()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 518 case ISD::ATOMIC_CMP_SWAP: { in getOUTLINE_ATOMIC()
522 case ISD::ATOMIC_SWAP: { in getOUTLINE_ATOMIC()
526 case ISD::ATOMIC_LOAD_ADD: { in getOUTLINE_ATOMIC()
530 case ISD::ATOMIC_LOAD_OR: { in getOUTLINE_ATOMIC()
640 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); in InitCmpLibcallCCs()
910 case ISD::SDIV: in canOpTrap()
911 case ISD::UDIV: in canOpTrap()
912 case ISD::SREM: in canOpTrap()
913 case ISD::UREM: in canOpTrap()
1632 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; in GetReturnInfo()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGNodes.h | 84 namespace ISD {
1348 case ISD::STORE:
1399 assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||
1581 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0,
1720 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
1798 : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
2255 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
2357 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
2663 namespace ISD {
2747 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 166 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) in RISCVTargetLowering()
299 ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, in RISCVTargetLowering()
300 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT, in RISCVTargetLowering()
301 ISD::SETGE, ISD::SETNE, ISD::SETO, ISD::SETUO}; in RISCVTargetLowering()
304 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP, in RISCVTargetLowering()
415 ISD::VP_ADD, ISD::VP_SUB, ISD::VP_MUL, ISD::VP_SDIV, ISD::VP_UDIV, in RISCVTargetLowering()
416 ISD::VP_SREM, ISD::VP_UREM, ISD::VP_AND, ISD::VP_OR, ISD::VP_XOR, in RISCVTargetLowering()
417 ISD::VP_ASHR, ISD::VP_LSHR, ISD::VP_SHL}; in RISCVTargetLowering()
546 ISD::SETO, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, in RISCVTargetLowering()
547 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUO, in RISCVTargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 85 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, ISD::UDIVREM, ISD::SDIVREM, in M68kTargetLowering()
86 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
92 for (auto OP : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
98 for (auto OP : {ISD::SMULO, ISD::UMULO}) { in M68kTargetLowering()
253 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) { in MatchingStackOffset()
1748 case ISD::OR: in EmitTest()
1915 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
1926 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
2222 if (Opc != ISD::OR && Opc != ISD::AND) in isAndOrOfSetCCs()
2300 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || in LowerBRCOND()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 60 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { in AVRTargetLowering()
286 case ISD::SHL: in LowerShifts()
316 case ISD::SRA: in LowerShifts()
319 case ISD::ROTL: in LowerShifts()
323 case ISD::ROTR: in LowerShifts()
327 case ISD::SRL: in LowerShifts()
330 case ISD::SHL: in LowerShifts()
420 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
790 case ISD::SHL: in LowerOperation()
791 case ISD::SRA: in LowerOperation()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 104 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE, in WebAssemblyTargetLowering()
105 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
109 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
114 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
128 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU, in WebAssemblyTargetLowering()
129 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS, in WebAssemblyTargetLowering()
130 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { in WebAssemblyTargetLowering()
199 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP, ISD::SDIV, ISD::UDIV, in WebAssemblyTargetLowering()
200 ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) in WebAssemblyTargetLowering()
205 for (auto Op : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in WebAssemblyTargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1385 case ISD::SETEQ: in FPCondCCodeToFCC()
1387 case ISD::SETNE: in FPCondCCodeToFCC()
1389 case ISD::SETLT: in FPCondCCodeToFCC()
1391 case ISD::SETGT: in FPCondCCodeToFCC()
2702 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2911 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
2913 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
3055 case ISD::FABS: in LowerOperation()
3059 case ISD::ADDC: in LowerOperation()
3060 case ISD::ADDE: in LowerOperation()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 3472 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in LowerSETCC()
8334 assert((Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP || in LowerINT_TO_FPVector()
13559 if (CC == ISD::SETNE || CC == ISD::SETEQ) { in combineSetCC()
14678 case ISD::ADD: in PerformDAGCombine()
14680 case ISD::SHL: in PerformDAGCombine()
14682 case ISD::SRA: in PerformDAGCombine()
14684 case ISD::SRL: in PerformDAGCombine()
14686 case ISD::MUL: in PerformDAGCombine()
14688 case ISD::FMA: in PerformDAGCombine()
15304 assert((CC == ISD::SETEQ || CC == ISD::SETNE) && in PerformDAGCombine()
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