/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MicroMipsInstrFormats.td | 61 bits<16> Inst; 75 bits<16> Inst; 87 bits<16> Inst; 100 bits<16> Inst; 114 bits<16> Inst; 127 bits<16> Inst; 139 bits<16> Inst; 150 bits<16> Inst; 161 bits<16> Inst; 172 bits<16> Inst; [all …]
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H A D | MicroMips32r6InstrFormats.td | 40 bits<16> Inst; 50 bits<16> Inst; 60 bits<16> Inst; 72 bits<32> Inst; 85 bits<32> Inst; 96 bits<16> Inst; 107 bits<16> Inst; 119 bits<32> Inst; 133 bits<32> Inst; 147 bits<32> Inst; [all …]
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H A D | MipsInstrFormats.td | 179 bits<32> Inst; 193 bits<32> Inst; 208 bits<32> Inst; 221 bits<32> Inst; 236 bits<32> Inst; 249 bits<32> Inst; 265 bits<32> Inst; 281 bits<32> Inst; 293 bits<32> Inst; 306 bits<32> Inst; [all …]
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H A D | MipsMSAInstrFormats.td | 37 let Inst{18-16} = m; 38 let Inst{15-11} = ws; 39 let Inst{10-6} = wd; 50 let Inst{19-16} = m; 52 let Inst{10-6} = wd; 63 let Inst{20-16} = m; 65 let Inst{10-6} = wd; 75 let Inst{22} = 0b0; 76 let Inst{21-16} = m; 120 let Inst{16} = df; [all …]
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H A D | MicroMipsDSPInstrFormats.td | 30 let Inst{25-21} = rt; 31 let Inst{20-16} = rs; 32 let Inst{15-11} = rd; 33 let Inst{10-0} = op; 41 let Inst{25-21} = rt; 42 let Inst{20-16} = rs; 43 let Inst{15-6} = op; 53 let Inst{25-21} = rt; 54 let Inst{20-16} = rs; 55 let Inst{15-14} = ac; [all …]
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H A D | Mips32r6InstrFormats.td | 181 bits<32> Inst; 196 bits<32> Inst; 207 bits<32> Inst; 223 bits<32> Inst; 238 bits<32> Inst; 252 bits<32> Inst; 264 bits<32> Inst; 276 bits<32> Inst; 288 bits<32> Inst; 300 bits<32> Inst; [all …]
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H A D | MipsDSPInstrFormats.td | 72 let Inst{25-21} = rs; 73 let Inst{20-16} = rt; 74 let Inst{15-11} = rd; 75 let Inst{10-6} = op; 85 let Inst{25-21} = rs; 86 let Inst{20-16} = 0; 87 let Inst{15-11} = rd; 101 let Inst{15-11} = 0; 141 let Inst{25-21} = 0; 263 let Inst{10-6} = 0; [all …]
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H A D | Mips16InstrFormats.td | 58 field bits<16> Inst; 221 let Inst{7} = nd; 222 let Inst{6} = l; 223 let Inst{5} = ra; 287 let Inst{4} = f; 395 let Inst{7} = s; 396 let Inst{6} = ra; 397 let Inst{5} = s0; 398 let Inst{4} = s1; 547 let Inst{4} = f; [all …]
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H A D | MipsMTInstrFormats.td | 40 bits<32> Inst; 45 let Inst{20-16} = rt; 54 bits<32> Inst; 63 let Inst{20-16} = rt; 64 let Inst{15-11} = rd; 66 let Inst{5} = u; 67 let Inst{4} = h; 73 bits<32> Inst; 79 let Inst{25-21} = rs; 80 let Inst{20-16} = rt; [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepInstrFormats.td | 13 let Inst{12-8} = Vu32{4-0}; 17 let Inst{4-0} = Vdd32{4-0}; 21 let Inst{11-5} = Ii{6-0}; 25 let Inst{1-0} = Pd4{1-0}; 33 let Inst{1-0} = Pd4{1-0}; 38 let Inst{7-1} = Ii{8-2}; 45 let Inst{8-8} = n1{0-0}; 50 let Inst{7-7} = Ii{0-0}; 52 let Inst{11-8} = II{5-2}; 53 let Inst{6-5} = II{1-0}; [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 286 Inst.setOpcode(XCore::ADD_3r); in Decode2OpInstructionFail() 289 Inst.setOpcode(XCore::SUB_3r); in Decode2OpInstructionFail() 292 Inst.setOpcode(XCore::SHL_3r); in Decode2OpInstructionFail() 295 Inst.setOpcode(XCore::SHR_3r); in Decode2OpInstructionFail() 298 Inst.setOpcode(XCore::EQ_3r); in Decode2OpInstructionFail() 301 Inst.setOpcode(XCore::AND_3r); in Decode2OpInstructionFail() 304 Inst.setOpcode(XCore::OR_3r); in Decode2OpInstructionFail() 307 Inst.setOpcode(XCore::LDW_3r); in Decode2OpInstructionFail() 334 Inst.setOpcode(XCore::LSS_3r); in Decode2OpInstructionFail() 337 Inst.setOpcode(XCore::LSU_3r); in Decode2OpInstructionFail() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 188 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand() 193 return decodeUImmOperand<2>(Inst, Imm); in decodeU2ImmOperand() 198 return decodeUImmOperand<3>(Inst, Imm); in decodeU3ImmOperand() 203 return decodeUImmOperand<4>(Inst, Imm); in decodeU4ImmOperand() 208 return decodeUImmOperand<6>(Inst, Imm); in decodeU6ImmOperand() 213 return decodeUImmOperand<8>(Inst, Imm); in decodeU8ImmOperand() 218 return decodeUImmOperand<12>(Inst, Imm); in decodeU12ImmOperand() 223 return decodeUImmOperand<16>(Inst, Imm); in decodeU16ImmOperand() 233 return decodeSImmOperand<8>(Inst, Imm); in decodeS8ImmOperand() 477 uint64_t Inst = 0; in getInstruction() local [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrFormats.td | 15 field bits<32> Inst; 22 let Inst{0-5} = opcode; 80 field bits<64> Inst; 232 let Inst{6-10} = A; 233 let Inst{11-15} = B; 568 let Inst{6} = 0; 573 let Inst{31} = 0; 614 let Inst{15} = L; 1676 let Inst{6} = 0; 1678 let Inst{15} = 0; [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/Disassembler/ |
H A D | PPCDisassembler.cpp | 76 Inst.addOperand(MCOperand::createImm(Offset)); in decodeDirectBrTarget() 106 return decodeRegisterClass(Inst, RegNo, FRegs); in DecodeF4RCRegisterClass() 197 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand() 213 Inst.addOperand(MCOperand::createImm(Imm)); in decodeImmZeroOperand() 236 switch (Inst.getOpcode()) { in decodeMemRIOperands() 252 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands() 271 if (Inst.getOpcode() == PPC::LDU) in decodeMemRIXOperands() 274 else if (Inst.getOpcode() == PPC::STDU) in decodeMemRIXOperands() 275 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands() 294 Inst.addOperand(MCOperand::createImm(Disp)); in decodeMemRIHashOperands() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrFormatsV.td | 75 let Inst{31} = 1; 76 let Inst{30} = 1; 92 let Inst{31} = 0; 108 let Inst{31} = 1; 128 let Inst{25} = vm; 148 let Inst{25} = vm; 167 let Inst{25} = vm; 187 let Inst{25} = vm; 206 let Inst{25} = vm; 228 let Inst{25} = vm; [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1549 switch (Inst.getOpcode()) { in DecodeRegListOperand() 1678 switch (Inst.getOpcode()) { in DecodeCopMemInstruction() 1755 switch (Inst.getOpcode()) { in DecodeCopMemInstruction() 1816 switch (Inst.getOpcode()) { in DecodeCopMemInstruction() 1858 switch (Inst.getOpcode()) { in DecodeAddrMode2IdxInstruction() 1878 switch (Inst.getOpcode()) { in DecodeAddrMode2IdxInstruction() 2011 switch (Inst.getOpcode()) { in DecodeAddrMode3Instruction() 2307 Inst.addOperand( in DecodeMemMultipleWritebackInstruction() 2785 switch(Inst.getOpcode()) { in DecodeVLDInstruction() 3674 switch(Inst.getOpcode()) { in DecodeThumbAddSpecialReg() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 986 switch (Inst.getOpcode()) { in DecodeThreeAddrSRegInstruction() 1046 switch (Inst.getOpcode()) { in DecodeMoveImmInstruction() 1065 Inst.addOperand(Inst.getOperand(0)); in DecodeMoveImmInstruction() 1081 switch (Inst.getOpcode()) { in DecodeUnsignedLdStInstruction() 1146 switch (Inst.getOpcode()) { in DecodeSignedLdStInstruction() 1199 switch (Inst.getOpcode()) { in DecodeSignedLdStInstruction() 1339 unsigned Opcode = Inst.getOpcode(); in DecodeExclusiveLdStInstruction() 1428 unsigned Opcode = Inst.getOpcode(); in DecodePairLdStInstruction() 1557 switch (Inst.getOpcode()) { in DecodeAuthLoadInstruction() 1593 switch (Inst.getOpcode()) { in DecodeAddSubERegInstruction() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
H A D | ARCInstrFormats.td | 14 field bits<64> Inst; 162 let Inst{5} = N; 181 let Inst{4} = 0; 203 let Inst{17} = 1; 211 let Inst{17} = 0; 232 let Inst{16} = 1; 236 let Inst{5} = N; 238 let Inst{3} = 0; 305 let Inst{5} = 0; 405 let Inst{6} = x; [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/ |
H A D | RISCVDisassembler.cpp | 74 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass() 85 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR16RegisterClass() 254 if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP || in addImplySP() 255 Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP || in addImplySP() 256 Inst.getOpcode() == RISCV::C_FLWSP || in addImplySP() 257 Inst.getOpcode() == RISCV::C_FSWSP || in addImplySP() 258 Inst.getOpcode() == RISCV::C_FLDSP || in addImplySP() 273 addImplySP(Inst, Address, Decoder); in decodeUImmOperand() 291 addImplySP(Inst, Address, Decoder); in decodeSImmOperand() 385 Inst.addOperand(Inst.getOperand(0)); in decodeRVCInstrRdRs1UImm() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRInstrFormats.td | 30 field bits<16> Inst; 39 field bits<32> Inst; 110 let Inst{3} = 0; 111 let Inst{2-0} = t; 170 let Inst{12} = 0; 203 let Inst{12} = 0; 238 let Inst{1} = e; 239 let Inst{0} = p; 276 let Inst{8} = f; 323 let Inst{8} = f; [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 1543 if (Inst.getOpcode() == Mips::SC || in DecodeMem() 1544 Inst.getOpcode() == Mips::SCD) in DecodeMem() 1723 switch(Inst.getOpcode()) in DecodeMSA128Mem() 1758 switch (Inst.getOpcode()) { in DecodeMemMMImm4() 1782 switch (Inst.getOpcode()) { in DecodeMemMMImm4() 1845 switch (Inst.getOpcode()) { in DecodeMemMMReglistImm4Lsl2() 1876 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6) in DecodeMemMMImm9() 1897 switch (Inst.getOpcode()) { in DecodeMemMMImm12() 1911 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) in DecodeMemMMImm12() 2056 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ in DecodeSpecial3LlSc() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Analysis/ |
H A D | CFLGraph.h | 278 auto *Ptr = &Inst; in visitIntToPtrInst() 284 addAssignEdge(Src, &Inst); in visitCastInst() 291 addAssignEdge(Src, &Inst); in visitFreezeInst() 351 void visitAllocaInst(AllocaInst &Inst) { addNode(&Inst); } in visitAllocaInst() argument 355 auto *Val = &Inst; in visitLoadInst() 478 auto *Val = &Inst; in visitExtractElementInst() 486 addStoreEdge(Val, &Inst); in visitInsertElementInst() 501 addStoreEdge(Val, &Inst); in visitInsertValueInst() 506 addLoadEdge(Ptr, &Inst); in visitExtractValueInst() 613 return !isa<CmpInst>(Inst) && !isa<FenceInst>(Inst) && in hasUsefulEdges() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 5748 Inst.addOperand(Inst.getOperand(0)); in cvtThumbMultiply() 7928 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) in validateInstruction() 7946 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) in validateInstruction() 8160 if (Inst.getOperand(0).isImm() && Inst.getOperand(2).isImm()) { in validateInstruction() 8688 Inst = TmpInst; in processInstruction() 10400 Inst.insert(Inst.begin(), in processInstruction() 10430 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction() 10431 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction() 10441 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction() 10442 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
H A D | VEInstrFormats.td | 25 field bits<64> Inst; 31 let Inst{63-56} = op; 78 let Inst{55} = cx; 80 let Inst{47} = cy; 82 let Inst{39} = cz; 127 let Inst{55} = cx; 131 let Inst{47} = cy; 133 let Inst{39} = cz; 167 let Inst{7} = cw; 223 let Inst{52} = 0; [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
H A D | EarlyCSE.cpp | 134 return isa<CastInst>(Inst) || isa<UnaryOperator>(Inst) || in canHandle() 136 isa<CmpInst>(Inst) || isa<SelectInst>(Inst) || in canHandle() 139 isa<InsertValueInst>(Inst) || isa<FreezeInst>(Inst); in canHandle() 211 Instruction *Inst = Val.Inst; in getHashValueImpl() local 286 assert((isa<CallInst>(Inst) || isa<GetElementPtrInst>(Inst) || in getHashValueImpl() 329 Instruction *LHSI = LHS.Inst, *RHSI = RHS.Inst; in isEqualImpl() 489 Instruction *Inst = Val.Inst; in getHashValue() local 498 Instruction *LHSI = LHS.Inst, *RHSI = RHS.Inst; in isEqual() 681 : Inst(Inst) { in ParseMemoryInst() 1375 AvailableValues.insert(&Inst, &Inst); in processNode() [all …]
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