| /netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineMulDivRem.cpp | 220 if (isa<Constant>(Op1)) { in visitMul()
235 if (Op0 == Op1) { in visitMul()
269 Value *Y = Op1; in visitMul()
586 Op1 != Y) { in visitFMul()
587 Value *XX = Builder.CreateFMulFMF(Op1, Op1, &I); in visitFMul()
603 Y = Op1; in visitFMul()
905 ShiftLeft = Op1; in foldUDivShl()
915 if (Op1 != ShiftLeft) in foldUDivShl()
1122 if (I.isExact() && ((match(Op1, m_Power2()) && match(Op1, m_NonNegative())) || in visitSDiv()
1126 Op1 = ConstantExpr::getNeg(cast<Constant>(Op1)); in visitSDiv()
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| H A D | InstCombineAddSub.cpp | 829 if (!match(Op1, m_Constant(Op1C))) in foldNoWrapAdd()
836 if (match(Op1, m_APInt(C1)) && in foldNoWrapAdd()
867 if (!match(Op1, m_ImmConstant(Op1C))) in foldAddWithConstant()
884 match(Op1, m_AllOnes())) in foldAddWithConstant()
901 if (!match(Op1, m_APInt(C))) in foldAddWithConstant()
1261 if (!Op0 || !Op1 || !(Op0->hasOneUse() || Op1->hasOneUse())) in factorizeMathWithShlOps()
1944 Y, Builder.CreateNot(Op1, Op1->getName() + ".not")); in visitSub()
2028 Value *NotA = Op0, *MinMax = Op1; in visitSub()
2031 NotA = Op1; in visitSub()
2270 if (match(Op1, m_ImmConstant(C))) in visitFSub()
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| H A D | InstCombineShifts.cpp | 374 assert(Op0->getType() == Op1->getType()); in commonShiftTransforms()
378 if (match(Op1, m_OneUse(m_SExt(m_Value(Y))))) { in commonShiftTransforms()
393 if (Constant *CUI = dyn_cast<Constant>(Op1)) in commonShiftTransforms()
414 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Constant(C))) && in commonShiftTransforms()
667 if (!match(Op1, m_APInt(Op1C))) in FoldShiftByConstant()
746 m_Specific(Op1)))) { in FoldShiftByConstant()
778 m_Specific(Op1)))) { in FoldShiftByConstant()
912 if (match(Op1, m_APInt(ShAmtAPInt))) { in visitShl()
1011 if (match(Op1, m_Constant(C1))) { in visitShl()
1052 if (match(Op1, m_APInt(ShAmtAPInt))) { in visitLShr()
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| H A D | InstCombineAndOrXor.cpp | 1496 std::swap(Op0, Op1); in reassociateFCmps()
1677 Value *Op1 = I.getOperand(1); in foldAndToXor() local
1703 Value *Op1 = I.getOperand(1); in foldOrToXor() local
1758 if (!match(Op1, m_ZExt(m_Value(X))) || Op1->hasNUsesOrMore(3)) in narrowMaskedBinOp()
1817 match(Op1, m_One())) { in visitAnd()
1825 if (match(Op1, m_APInt(C))) { in visitAnd()
2227 std::swap(Op0, Op1); in matchOrConcat()
2797 std::swap(Op0, Op1); in visitOr()
2836 std::swap(Op0, Op1); in visitOr()
2986 Value *Op1 = I.getOperand(1); in foldXorToXor() local
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| H A D | InstCombineCompares.cpp | 2852 (isa<Constant>(Op1) || isa<BitCastInst>(Op1))) { in foldICmpBitCast()
2858 Op1 = Builder.CreateBitCast(Op1, BCSrcOp->getType()); in foldICmpBitCast()
3287 if (Op1 && Op2) in foldICmpInstWithConstantNotInt()
3302 if (!Op1) in foldICmpInstWithConstantNotInt()
3821 if ((A == Op1 || B == Op1) && NoOp0WrapProblem) in foldICmpBinOp()
4245 if (A == Op1 || B == Op1) { // (A^B) == A -> B == 0 in foldICmpEquality()
4303 Op1 = Builder.CreateAnd(Op1, Z); in foldICmpEquality()
4396 A = Op1; in foldICmpEquality()
5551 ((Pred == ICmpInst::ICMP_ULT && (Op1 == A || Op1 == B)) || in foldICmpOfUAddOv()
6206 if (!match(Op1, m_PosZeroFP()) && isKnownNeverNaN(Op1, &TLI)) in visitFCmpInst()
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| H A D | InstructionCombining.cpp | 419 if (Op1 && Op1->getOpcode() == Opcode) { in SimplifyAssociativeOrCommutative()
467 if (Op1 && Op1->getOpcode() == Opcode) { in SimplifyAssociativeOrCommutative()
490 if (Op0 && Op1 && in SimplifyAssociativeOrCommutative()
715 if (Op1) in SimplifyUsingDistributiveLaws()
733 if (Op1) in SimplifyUsingDistributiveLaws()
779 if (Op1 && leftDistributesOverRight(TopLevelOpcode, Op1->getOpcode())) { in SimplifyUsingDistributiveLaws()
782 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1); in SimplifyUsingDistributiveLaws()
949 std::swap(Op0, Op1); in foldOperationIntoSelectOperand()
1047 std::swap(Op0, Op1); in foldOperationIntoPhiValue()
1928 if (!Op1) in visitGetElementPtrInst()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 346 unsigned Op1, Op2; in Decode2RInstruction() local
359 unsigned Op1, Op2; in Decode2RImmInstruction() local
372 unsigned Op1, Op2; in DecodeR2RInstruction() local
385 unsigned Op1, Op2; in Decode2RSrcDstInstruction() local
399 unsigned Op1, Op2; in DecodeRUSInstruction() local
412 unsigned Op1, Op2; in DecodeRUSBitpInstruction() local
425 unsigned Op1, Op2; in DecodeRUSSrcDstBitpInstruction() local
510 unsigned Op1, Op2; in DecodeL2RInstruction() local
524 unsigned Op1, Op2; in DecodeLR2RInstruction() local
538 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 322 if (Op1 && Op1->getOpcode() == Opcode) { in SimplifyAssociativeBinOp()
364 if (Op1 && Op1->getOpcode() == Opcode) { in SimplifyAssociativeBinOp()
619 return Op1; in SimplifyAddInst()
873 if (Q.isUndefValue(Op1) || match(Op1, m_Zero())) in SimplifyMulInst()
1575 return Op1; in simplifyOrOfICmpsWithSameOperands()
2005 return Op1; in SimplifyAndInst()
2036 return Op1; in SimplifyAndInst()
2153 if (Q.isUndefValue(Op1) || match(Op1, m_AllOnes())) in SimplifyOrInst()
2158 if (Op0 == Op1 || match(Op1, m_Zero())) in SimplifyOrInst()
2168 return Op1; in SimplifyOrInst()
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| H A D | OverflowInstAnalysis.cpp | 22 bool llvm::isCheckForZeroAndMulWithOverflow(Value *Op0, Value *Op1, bool IsAnd, in isCheckForZeroAndMulWithOverflow() argument
57 matchMulOverflowCheck(Op1)) || in isCheckForZeroAndMulWithOverflow()
59 match(Op1, m_Not(m_Value(NotOp1))) && matchMulOverflowCheck(NotOp1)); in isCheckForZeroAndMulWithOverflow()
68 bool llvm::isCheckForZeroAndMulWithOverflow(Value *Op0, Value *Op1, in isCheckForZeroAndMulWithOverflow() argument
71 return isCheckForZeroAndMulWithOverflow(Op0, Op1, IsAnd, Y); in isCheckForZeroAndMulWithOverflow()
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| /netbsd/sys/external/bsd/acpica/dist/compiler/ |
| H A D | asltree.c | 549 Op1, Op1 ? UtGetOpName(Op1->Asl.ParseOpcode) : NULL, in TrLinkPeerOp()
556 return (Op1); in TrLinkPeerOp()
563 return (Op1); in TrLinkPeerOp()
566 if (!Op1) in TrLinkPeerOp()
571 if (Op1 == Op2) in TrLinkPeerOp()
575 Op1); in TrLinkPeerOp()
578 return (Op1); in TrLinkPeerOp()
588 Next = Op1; in TrLinkPeerOp()
595 return (Op1); in TrLinkPeerOp()
686 Op1, Op1 ? UtGetOpName(Op1->Asl.ParseOpcode): NULL, in TrLinkChildOp()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| H A D | ConstraintElimination.cpp | 57 Value *Op0, *Op1; in decompose() local
70 {1, Op1}}; in decompose()
100 Value *Op1; in decompose() local
104 if (match(V, m_NUWAdd(m_Value(Op0), m_Value(Op1)))) in decompose()
105 return {{0, nullptr}, {1, Op0}, {1, Op1}}; in decompose()
109 if (match(V, m_NUWSub(m_Value(Op0), m_Value(Op1)))) in decompose()
110 return {{0, nullptr}, {1, Op0}, {1, Op1}}; in decompose()
161 if (Pred == CmpInst::ICMP_NE && match(Op1, m_Zero())) { in getConstraint()
287 Value *Op0, *Op1; in eliminateConstraints() local
289 match(Op0, m_Cmp()) && match(Op1, m_Cmp())) { in eliminateConstraints()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 346 int32_t Prof1 = Op1.isImm() ? profitImm(Op1.getImm()) : 0; in profit()
701 assert(Op0.isReg() && Op1.isImm()); in splitImmediate()
702 uint64_t V = Op1.getImm(); in splitImmediate()
737 if (!Op1.isReg()) { in splitCombine()
739 .add(Op1); in splitCombine()
742 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
765 unsigned RS = getRegState(Op1); in splitExt()
768 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg()); in splitExt()
770 .addReg(Op1.getReg(), RS, Op1.getSubReg()) in splitExt()
799 unsigned RS = getRegState(Op1); in splitShift()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 282 bool VLIWPacketizerList::alias(const MachineMemOperand &Op1, in alias() argument
285 if (!Op1.getValue() || !Op2.getValue()) in alias()
288 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
289 int64_t Overlapa = Op1.getSize() + Op1.getOffset() - MinOffset; in alias()
293 AA->alias(MemoryLocation(Op1.getValue(), Overlapa, in alias()
294 UseTBAA ? Op1.getAAInfo() : AAMDNodes()), in alias()
307 for (const MachineMemOperand *Op1 : MI1.memoperands()) in alias() local
309 if (alias(*Op1, *Op2, UseTBAA)) in alias()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.cpp | 142 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
145 Ops[2].getAsInteger(10, Op1); in parseGenericRegister()
149 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
157 uint32_t Op1 = (Bits >> 11) & 0x7; in genericRegisterString() local
162 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" + in genericRegisterString()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCCodeEmitter.cpp | 189 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRiMemoryOpValue() local
193 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
199 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 18); in getRiMemoryOpValue()
221 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRrMemoryOpValue() local
225 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
226 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 15); in getRrMemoryOpValue()
260 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getSplsOpValue() local
264 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
270 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 12); in getSplsOpValue()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| H A D | BypassSlowDivision.cpp | 89 Value *insertOperandRuntimeCheck(Value *Op1, Value *Op2);
203 Value *Op1 = I->getOperand(1); in isHashLikeValue() local
204 ConstantInt *C = dyn_cast<ConstantInt>(Op1); in isHashLikeValue()
205 if (!C && isa<BitCastInst>(Op1)) in isHashLikeValue()
206 C = dyn_cast<ConstantInt>(cast<BitCastInst>(Op1)->getOperand(0)); in isHashLikeValue()
330 Value *FastDivInsertionTask::insertOperandRuntimeCheck(Value *Op1, Value *Op2) { in insertOperandRuntimeCheck() argument
331 assert((Op1 || Op2) && "Nothing to check"); in insertOperandRuntimeCheck()
336 if (Op1 && Op2) in insertOperandRuntimeCheck()
337 OrV = Builder.CreateOr(Op1, Op2); in insertOperandRuntimeCheck()
339 OrV = Op1 ? Op1 : Op2; in insertOperandRuntimeCheck()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | SVEIntrinsicOpts.cpp | 289 IntrinsicInst *Op1 = dyn_cast<IntrinsicInst>(I->getArgOperand(0)); in optimizePTest() local
292 if (Op1 && Op2 && in optimizePTest()
293 Op1->getIntrinsicID() == Intrinsic::aarch64_sve_convert_to_svbool && in optimizePTest()
295 Op1->getArgOperand(0)->getType() == Op2->getArgOperand(0)->getType()) { in optimizePTest()
297 Value *Ops[] = {Op1->getArgOperand(0), Op2->getArgOperand(0)}; in optimizePTest()
298 Type *Tys[] = {Op1->getArgOperand(0)->getType()}; in optimizePTest()
306 if (Op1->use_empty()) in optimizePTest()
307 Op1->eraseFromParent(); in optimizePTest()
308 if (Op1 != Op2 && Op2->use_empty()) in optimizePTest()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCBranchCoalescing.cpp | 341 const MachineOperand &Op1 = OpList1[i]; in identicalOperands() local
344 LLVM_DEBUG(dbgs() << "Op1: " << Op1 << "\n" in identicalOperands()
347 if (Op1.isIdenticalTo(Op2)) { in identicalOperands()
349 if (Op1.isReg() && in identicalOperands()
350 Register::isPhysicalRegister(Op1.getReg()) in identicalOperands()
353 && !(Op1.isUse() && MRI->isConstantPhysReg(Op1.getReg()))) { in identicalOperands()
364 if (Op1.isReg() && Op2.isReg() && in identicalOperands()
365 Register::isVirtualRegister(Op1.getReg()) && in identicalOperands()
367 MachineInstr *Op1Def = MRI->getVRegDef(Op1.getReg()); in identicalOperands()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 228 void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
229 void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
464 const SrcOp &Op1);
488 const SrcOp &Op1) { in buildPtrMask() argument
489 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1}); in buildPtrMask()
558 const SrcOp &Op0, const SrcOp &Op1, in buildUAdde() argument
561 {Op0, Op1, CarryIn}); in buildUAdde()
566 const SrcOp &Op0, const SrcOp &Op1, in buildUSube() argument
569 {Op0, Op1, CarryIn}); in buildUSube()
577 {Op0, Op1, CarryIn}); in buildSAdde()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGTargetInfo.h | 52 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemcpy() argument
68 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, in EmitTargetCodeForMemmove() argument
81 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemset() argument
94 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
131 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand() argument
171 if (Op1.getType() != Op2.getType()) in isSameOperand()
174 switch (Op1.getType()) { in isSameOperand()
176 return Op1.getReg() == Op2.getReg(); in isSameOperand()
178 return Op1.getImm() == Op2.getImm(); in isSameOperand()
293 MachineOperand &Op1 = AluIter->getOperand(1); in isSuitableAluInstr() local
298 if (!isSameOperand(Dest, Base) || !isSameOperand(Dest, Op1)) in isSuitableAluInstr()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 155 MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0); in optimizeVcndVcmpPair() local
157 if (Op1->isImm() && Op2->isReg()) in optimizeVcndVcmpPair()
158 std::swap(Op1, Op2); in optimizeVcndVcmpPair()
159 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1) in optimizeVcndVcmpPair()
162 Register SelReg = Op1->getReg(); in optimizeVcndVcmpPair()
163 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, *MRI, LIS); in optimizeVcndVcmpPair()
171 Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
174 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() || in optimizeVcndVcmpPair()
175 Op1->getImm() != 0 || Op2->getImm() != 1) in optimizeVcndVcmpPair()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblySelectionDAGInfo.h | 26 SDValue Chain, SDValue Op1, SDValue Op2,
33 SDValue Op1, SDValue Op2, SDValue Op3,
38 SDValue Chain, SDValue Op1, SDValue Op2,
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | PatternMatch.h | 1420 T0 Op1; member
1422 OneOps_match(const T0 &Op1) : Op1(Op1) {} in OneOps_match()
1435 T0 Op1; member
1438 TwoOps_match(const T0 &Op1, const T1 &Op2) : Op1(Op1), Op2(Op2) {} in TwoOps_match()
1452 T0 Op1; member
1457 : Op1(Op1), Op2(Op2), Op3(Op3) {} in ThreeOps_match()
1508 T0 Op1; member
1513 : Op1(Op1), Op2(Op2), Mask(Mask) {} in Shuffle_match()
1990 Value *Op1; in match() local
2399 T1 Op1;
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/AggressiveInstCombine/ |
| H A D | AggressiveInstCombine.cpp | 220 Value *Op0, *Op1; in matchAndOrChain() local
229 if (match(V, m_And(m_Value(Op0), m_Value(Op1)))) in matchAndOrChain()
230 return matchAndOrChain(Op0, MOps) && matchAndOrChain(Op1, MOps); in matchAndOrChain()
233 if (match(V, m_Or(m_Value(Op0), m_Value(Op1)))) in matchAndOrChain()
234 return matchAndOrChain(Op0, MOps) && matchAndOrChain(Op1, MOps); in matchAndOrChain()
329 Value *Op1 = I.getOperand(1); in tryToRecognizePopCount() local
333 match(Op1, m_SpecificInt(MaskShift))) { in tryToRecognizePopCount()
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