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Searched refs:RREG8 (Results 1 – 7 of 7) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_mxgpu_ai.c82 return RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2; in xgpu_ai_peek_ack()
91 reg = RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE); in xgpu_ai_poll_ack()
H A Damdgpu_mxgpu_nv.c83 return RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2; in xgpu_nv_peek_ack()
92 reg = RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE); in xgpu_nv_poll_ack()
H A Damdgpu.h1047 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) macro
/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_legacy_tv.c298 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) in radeon_wait_pll_lock()
H A Dradeon.h2580 #define RREG8(r) bus_space_read_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r)) macro
2585 #define RREG8(reg) readb((rdev->rmmio) + (reg)) macro
H A Dradeon_r100.c3802 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); in r100_mc_stop()
3855 tmp = RREG8(R_0003C2_GENMO_WT); in r100_vga_render_disable()
H A Dradeon_combios.c1155 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; in radeon_legacy_get_lvds_info_from_regs()