| /netbsd/external/bsd/pcc/dist/pcc/cc/ccom/ |
| H A D | softfloat.c | 156 #define SHL(x,b) ((dword)(x) << b) in soft_div() macro
157 T = SHL(1,55) | SHL(DMANTH(t), 48) | in soft_div()
158 SHL(t.fd2, 32) | SHL(t.fd3, 16) | t.fd4; in soft_div()
159 N = SHL(1,55) | SHL(DMANTH(n), 48) | in soft_div()
160 SHL(n.fd2, 32) | SHL(n.fd3, 16) | n.fd4; in soft_div()
252 mant = SHL(1,55) | SHL(DMANTH(sf), 48) | in soft_val()
253 SHL(sf.fd2, 32) | SHL(sf.fd3, 16) | sf.fd4; in soft_val()
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| /netbsd/external/bsd/pcc/dist/pcc/cc/cxxcom/ |
| H A D | softfloat.c | 156 #define SHL(x,b) ((dword)(x) << b) in soft_div() macro
157 T = SHL(1,55) | SHL(DMANTH(t), 48) | in soft_div()
158 SHL(t.fd2, 32) | SHL(t.fd3, 16) | t.fd4; in soft_div()
159 N = SHL(1,55) | SHL(DMANTH(n), 48) | in soft_div()
160 SHL(n.fd2, 32) | SHL(n.fd3, 16) | n.fd4; in soft_div()
252 mant = SHL(1,55) | SHL(DMANTH(sf), 48) | in soft_val()
253 SHL(sf.fd2, 32) | SHL(sf.fd3, 16) | sf.fd4; in soft_val()
|
| /netbsd/external/bsd/pcc/dist/pcc/arch/i86/ |
| H A D | table.c | 153 SHL, T32,
154 SHL, T32,
262 SHL, T32,
271 SHL, T32,
312 SHL, T32,
600 SHL, T32,
614 SHL, T32,
686 SHL, T32,
754 SHL, T32,
936 SHL, T32,
[all …]
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiAluCode.h | 35 SHL = 0x17, enumerator
92 case SHL: in lanaiAluCodeToString()
112 .Case("sh", SHL) in stringToLanaiAluCode()
134 case ISD::SHL: in isdToLanaiAluCode()
135 return AluCode::SHL; in isdToLanaiAluCode()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1053 if (T1.getOpcode() != ISD::SHL) in ppAddrReorderAddShl()
1622 case ISD::SHL: in isOpcodeHandled()
1749 if (Val.getOpcode() != ISD::SHL || in findSHL()
1816 if (Val.getOpcode() == ISD::SHL) { in getPowerOf2Factor()
1835 } else if (V.getOpcode() == ISD::SHL) { in willShiftRightEliminate()
1856 } else if (V.getOpcode() == ISD::SHL) { in factorOutPowerOf2()
1947 if (NOpcode == ISD::SHL) in balanceSubTree()
2035 if (ChildOpcode == ISD::SHL) in balanceSubTree()
2128 WeightedLeaf SHL = Leaves.findSHL(31); in balanceSubTree() local
2129 if (SHL.Value.getNode()) { in balanceSubTree()
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 635 { ISD::SHL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
641 { ISD::SHL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
677 { ISD::SHL, MVT::v16i8, 1 }, in getArithmeticInstrCost()
680 { ISD::SHL, MVT::v8i16, 1 }, in getArithmeticInstrCost()
683 { ISD::SHL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
686 { ISD::SHL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
690 { ISD::SHL, MVT::v32i8, 2+2 }, in getArithmeticInstrCost()
693 { ISD::SHL, MVT::v16i16, 2+2 }, in getArithmeticInstrCost()
696 { ISD::SHL, MVT::v8i32, 2+2 }, in getArithmeticInstrCost()
712 ShiftISD = ISD::SHL; in getArithmeticInstrCost()
[all …]
|
| /netbsd/sys/dev/microcode/siop/ |
| H A D | esiop.ss | 142 MOVE SCRATCHC1 SHL SFBR;
143 MOVE SFBR SHL DSA0; target * 4 in dsa
160 MOVE SCRATCHC2 SHL SFBR;
161 MOVE SFBR SHL SFBR;
162 MOVE SFBR SHL SFBR; lun * 8
180 MOVE SCRATCHA2 SHL SCRATCHA2;
181 MOVE SCRATCHA3 SHL SCRATCHA3;
182 MOVE SCRATCHA2 SHL SCRATCHA2;
183 MOVE SCRATCHA3 SHL SCRATCHA3; TAG * 4 to SCRATCHA(2,3)
|
| /netbsd/crypto/external/bsd/openssl.old/dist/crypto/bn/asm/ |
| H A D | ppc.pl | 123 $SHL= "slw"; # shift left
147 $SHL= "sld"; # shift left
1658 $SHL r3,r3,r7 # h = (h<< i)
1660 $SHL r5,r5,r7 # d<<=i
1662 $SHL r4,r4,r7 # l <<=i
|
| H A D | bn-c64xplus.asm | 196 [!A2] SHL A6,A0,A6 ; normalize dv
200 ||[!A2] SHL A4,1,A5:A4 ; lo<<1
209 || SHL A4,1,A5:A4 ; lo<<1
|
| /netbsd/crypto/external/bsd/openssl/dist/crypto/bn/asm/ |
| H A D | ppc.pl | 126 $SHL= "slw"; # shift left
150 $SHL= "sld"; # shift left
1662 $SHL r3,r3,r7 # h = (h<< i)
1664 $SHL r5,r5,r7 # d<<=i
1666 $SHL r4,r4,r7 # l <<=i
|
| H A D | bn-c64xplus.asm | 195 [!A2] SHL A6,A0,A6 ; normalize dv
199 ||[!A2] SHL A4,1,A5:A4 ; lo<<1
208 || SHL A4,1,A5:A4 ; lo<<1
|
| /netbsd/external/gpl3/binutils.old/dist/gas/ |
| H A D | rl78-parse.h | 147 SHL = 357, enumerator
267 #define SHL 357 macro
|
| /netbsd/external/gpl3/binutils/dist/gas/config/ |
| H A D | rl78-parse.h | 156 SHL = 357, /* SHL */ enumerator
281 #define SHL 357 macro
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kInstrShiftRotate.td | 15 /// SHL [~] ASR [~] LSR [~] SWAP [ ]
87 defm SHL : MxSROp<"lsl", shl, MxRODI_L, MxROOP_LS>;
|
| /netbsd/external/gpl3/gdb/dist/gas/testsuite/gas/sparc/ |
| H A D | fpcmpshl-diag.s | 1 # Diagnostic tests for FPCP{ULE8,UGT8,EQ8,NE}{8,16,32}SHL instructions.
|
| H A D | fpcmpshl.s | 1 # Test FPCMP{ULE8,UGT8,EQ8,NE,DE,UR}{8,16,32}SHL instructions.
|
| /netbsd/external/gpl3/gdb.old/dist/gas/testsuite/gas/sparc/ |
| H A D | fpcmpshl-diag.s | 1 # Diagnostic tests for FPCP{ULE8,UGT8,EQ8,NE}{8,16,32}SHL instructions.
|
| H A D | fpcmpshl.s | 1 # Test FPCMP{ULE8,UGT8,EQ8,NE,DE,UR}{8,16,32}SHL instructions.
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 1523 case ISD::SHL: in PromoteIntegerOperand()
2169 case ISD::SHL: in ExpandIntegerResult()
2270 if (N->getOpcode() == ISD::SHL) { in ExpandShiftByConstant()
2370 case ISD::SHL: in ExpandShiftWithKnownAmountBit()
2398 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; in ExpandShiftWithKnownAmountBit()
2404 if (N->getOpcode() != ISD::SHL) in ExpandShiftWithKnownAmountBit()
2416 if (N->getOpcode() != ISD::SHL) in ExpandShiftWithKnownAmountBit()
2452 case ISD::SHL: in ExpandShiftWithUnknownAmountBit()
3745 if (N->getOpcode() == ISD::SHL) { in ExpandIntRes_Shift()
3789 if (N->getOpcode() == ISD::SHL) { in ExpandIntRes_Shift()
[all …]
|
| H A D | TargetLowering.cpp | 756 case ISD::SHL: { in SimplifyMultipleUseDemandedBits()
1441 case ISD::SHL: { in SimplifyDemandedBits()
1461 unsigned Opc = ISD::SHL; in SimplifyDemandedBits()
1564 if (Op0.getOpcode() == ISD::SHL) { in SimplifyDemandedBits()
1573 Opc = ISD::SHL; in SimplifyDemandedBits()
2838 case ISD::SHL: in SimplifyDemandedVectorElts()
3321 case ISD::SHL: in optimizeSetCCByHoistingAndByConstFromLogicalShift()
3325 NewShiftOpcode = ISD::SHL; in optimizeSetCCByHoistingAndByConstFromLogicalShift()
4000 if (RHS.getOpcode() == ISD::SHL && in SimplifySetCC()
4008 if (LHS.getOpcode() == ISD::SHL && in SimplifySetCC()
[all …]
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSelectionDAGInfo.cpp | 173 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, IPM, in addIPMSequence() local
175 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, in addIPMSequence()
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl; in getShiftOpcForNode()
|
| /netbsd/usr.bin/xlint/lint1/ |
| H A D | scan.l | 88 "<<" return lex_operator(T_SHIFT, SHL);
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 83 setOperationAction(ISD::SHL, MVT::i8, Custom); in AVRTargetLowering()
86 setOperationAction(ISD::SHL, MVT::i16, Custom); in AVRTargetLowering()
286 case ISD::SHL: in LowerShifts()
330 case ISD::SHL: in LowerShifts()
339 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) { in LowerShifts()
352 } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) { in LowerShifts()
368 case ISD::SHL: in LowerShifts()
381 case ISD::SHL: in LowerShifts()
398 case ISD::SHL: in LowerShifts()
790 case ISD::SHL: in LowerOperation()
|
| /netbsd/external/gpl3/gdb/dist/gas/config/ |
| H A D | rl78-parse.y | 178 %token SAR SARW SEL SET1 SHL SHLW SHR SHRW
985 | SHL A ',' EXPR
990 | SHL B ',' EXPR
995 | SHL C ',' EXPR
1326 OPC(SHL),
|