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Searched refs:WREG32_FIELD (Results 1 – 9 of 9) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vce_v3_0.c170 WREG32_FIELD(VCE_RB_ARB_CTRL, VCE_CGTT_OVERRIDE, override ? 1 : 0); in vce_v3_0_override_vce_clock_gating()
254 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v3_0_firmware_loaded()
256 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v3_0_firmware_loaded()
308 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1); in vce_v3_0_start()
313 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1); in vce_v3_0_start()
315 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v3_0_start()
321 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0); in vce_v3_0_start()
350 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 0); in vce_v3_0_stop()
353 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v3_0_stop()
577 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1); in vce_v3_0_mc_resume()
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H A Damdgpu_vce_v2_0.c206 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1); in vce_v2_0_mc_resume()
262 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1); in vce_v2_0_start()
263 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v2_0_start()
265 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v2_0_start()
516 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1); in vce_v2_0_soft_reset()
H A Damdgpu_gfx_v8_0.c3763 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF); in gfx_v8_0_constants_init()
3980 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1); in gfx_v8_0_init_save_restore_list()
4019 WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1); in gfx_v8_0_enable_save_restore_machine()
4079 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v8_0_rlc_stop()
4087 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v8_0_rlc_reset()
4090 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v8_0_rlc_reset()
4096 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v8_0_rlc_start()
4588 WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v8_0_mqd_commit()
4692 WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v8_0_set_mec_doorbell_range()
5629 WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1); in gfx_v8_0_update_medium_grain_clock_gating()
[all …]
H A Damdgpu_uvd_v6_0.c722 WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0); in uvd_v6_0_start()
725 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1); in uvd_v6_0_start()
741 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0); in uvd_v6_0_start()
776 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0); in uvd_v6_0_start()
796 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1); in uvd_v6_0_start()
798 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0); in uvd_v6_0_start()
843 WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0); in uvd_v6_0_start()
H A Damdgpu_vce_v4_0.c722 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
727 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10);
732 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
914 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i);
933 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
H A Damdgpu_gfx_v6_0.c2436 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v6_0_enable_lbpw()
2505 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v6_0_rlc_reset()
2507 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v6_0_rlc_reset()
2780 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); in gfx_v6_0_enable_gfx_cgpg()
2781 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); in gfx_v6_0_enable_gfx_cgpg()
2783 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); in gfx_v6_0_enable_gfx_cgpg()
2833 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); in gfx_v6_0_init_gfx_cgpg()
H A Damdgpu_uvd_v4_2.c612 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v4_2_set_dcm()
H A Damdgpu_amdkfd_gfx_v8.c460 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0); in kgd_hqd_destroy()
H A Damdgpu.h1105 #define WREG32_FIELD(reg, field, val) \ macro