| /netbsd/sys/arch/aarch64/aarch64/ |
| H A D | cpufunc.c | 46 u_int arm_dcache_align; /* compat arm */ variable
191 arm_dcache_align = sizeof(int) << arm_dcache_maxline; in aarch64_parsecacheinfo()
192 arm_dcache_align_mask = arm_dcache_align - 1; in aarch64_parsecacheinfo()
196 if (coherency_unit < arm_dcache_align) in aarch64_parsecacheinfo()
198 coherency_unit, arm_dcache_align); in aarch64_parsecacheinfo()
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| /netbsd/sys/arch/arm/arm/ |
| H A D | cpufunc.c | 117 u_int arm_dcache_align; variable
1431 arm_dcache_align = arm_pcache.dcache_line_size; in get_cachetype_cp15()
1435 if (arm_scache.dcache_line_size < arm_dcache_align) in get_cachetype_cp15()
1436 arm_dcache_align = arm_scache.dcache_line_size; in get_cachetype_cp15()
1509 arm_dcache_align = arm_pcache.dcache_line_size; in get_cachetype_cp15()
1517 KASSERTMSG(arm_dcache_align <= CACHE_LINE_SIZE, in get_cachetype_cp15()
1519 arm_dcache_align, CACHE_LINE_SIZE); in get_cachetype_cp15()
1520 arm_dcache_align_mask = arm_dcache_align - 1; in get_cachetype_cp15()
1590 arm_dcache_align = arm_pcache.dcache_line_size; in get_cachetype_table()
1591 arm_dcache_align_mask = arm_dcache_align - 1; in get_cachetype_table()
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| /netbsd/sys/arch/aarch64/include/ |
| H A D | cpufunc.h | 117 extern u_int arm_dcache_align;
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| /netbsd/sys/arch/arm/ixp12x0/ |
| H A D | ixp12x0_pci.c | 109 arm_dcache_align); in ixp12x0_pci_init()
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| /netbsd/sys/arch/evbarm/marvell/ |
| H A D | marvell_machdep.c | 586 "cache-line-size", arm_dcache_align); in marvell_device_register()
831 "cache-line-size", arm_dcache_align); in marvell_device_register()
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| /netbsd/sys/arch/arm/xscale/ |
| H A D | i80312_pci.c | 119 pci_configure_bus(pc, pcires, sbus, arm_dcache_align); in i80312_pci_init()
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| H A D | i80321_pci.c | 128 pci_configure_bus(pc, pcires, busno, arm_dcache_align); in i80321_pci_init()
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| H A D | ixp425_pci.c | 102 arm_dcache_align); in ixp425_pci_init()
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| H A D | becc_pci.c | 137 pci_configure_bus(pc, pcires, 0, arm_dcache_align); in becc_pci_init()
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| /netbsd/sys/arch/arm/nxp/ |
| H A D | imx6_pcie.c | 239 int error = pci_configure_bus(&sc->sc_pc, pcires, 0, arm_dcache_align); in imx6_pcie_configure()
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| /netbsd/sys/arch/evbarm/ifpga/ |
| H A D | ifpga.c | 308 arm_dcache_align); in ifpga_attach()
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| /netbsd/sys/arch/arm/gemini/ |
| H A D | gemini_pci.c | 212 pci_configure_bus(pc, pcires, 0, arm_dcache_align); in gemini_pci_init()
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| /netbsd/sys/arch/arm/include/ |
| H A D | cpufunc.h | 412 extern u_int arm_dcache_align;
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| /netbsd/sys/arch/evbarm/armadaxp/ |
| H A D | armadaxp_machdep.c | 587 "cache-line-size", arm_dcache_align); in axp_device_register()
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| /netbsd/sys/arch/arm/broadcom/ |
| H A D | bcm53xx_eth.c | 1074 bus_dmamap_sync(sc->sc_dmat, map, 0, arm_dcache_align, in bcmeth_rxq_consume()
1503 misalignment = mtod(mext, vaddr_t) & arm_dcache_align; in bcmeth_copy_packet()
1521 if (((oldoff ^ off) & arm_dcache_align) != 0 || off < oldoff) { in bcmeth_copy_packet()
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| /netbsd/sys/arch/arm/s3c2xx0/ |
| H A D | s3c2800_pci.c | 307 pci_configure_bus(&sspci_chipset, pcires, 0, arm_dcache_align); in sspci_attach()
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| /netbsd/sys/arch/arm/fdt/ |
| H A D | pcihost_fdt.c | 60 #define PCIHOST_CACHELINE_SIZE arm_dcache_align
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| /netbsd/sys/arch/arm/nvidia/ |
| H A D | tegra_pcie.c | 252 arm_dcache_align); in tegra_pcie_attach()
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| /netbsd/sys/arch/arm/arm32/ |
| H A D | bus_dma.c | 888 const size_t line_size = arm_dcache_align; in _bus_dmamap_sync_segment()
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