v1i64 (reference) in projects: netbsd - OpenGrok search results

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Searched refs:v1i64 (Results 1 – 25 of 27) sorted by relevance

/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A D	ARMCallingConv.td	33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 186 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 213 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 236 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
H A D	ARMInstrNEON.td	3502 v1i64, v1i64, OpNode, Commutable>; 3610 v1i64, v1i64, IntOp, Commutable>; 3624 v1i64, v1i64, IntOp>; 5477 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 DPR:$src1), 5871 def : Pat<(v1i64 (ARMvshls (v1i64 DPR:$Dn), (v1i64 DPR:$Dm))), 5888 def : Pat<(v1i64 (ARMvshlu (v1i64 DPR:$Dn), (v1i64 DPR:$Dm))), 7417 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>; 7451 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>; 7452 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>; 7453 def : Pat<(v1i64 (bitconvert (v4f16 DPR:$src))), (v1i64 DPR:$src)>; [all …]
H A D	ARMScheduleA57.td	`1120 "VSLI(v8i8\|v4i16\|v2i32\|v1i64)", "VSRI(v8i8\|v4i16\|v2i32\|v1i64)")>; 1128 "VSHL(s\|u)(v8i8\|v4i16\|v2i32\|v1i64)")>; 1137 "VQRSHL(s\|u)(v8i8\|v4i16\|v2i32\|v1i64)", "VQSHL(s\|u)(v8i8\|v4i16\|v2i32\|v1i64)", 1138 "VRSHL(s\|u)(v8i8\|v4i16\|v2i32\|v1i64)")>; 1213 "VMOV(v8i8\|v16i8\|v4i16\|v8i16\|v2i32\|v4i32\|v1i64\|v2i64\|v2f32\|v4f32)",`
H A D	ARMRegisterInfo.td	`432 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64, 453 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64, 460 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,`
H A D	ARMTargetTransformInfo.cpp	`1276 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost() 1277 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost() 1278 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost() 1279 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()`
H A D	ARMScheduleR52.td	`775 (instregex "(VADD\|VSUB)(v8i8\|v4i16\|v2i32\|v1i64)")>; 819 def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VQABS(v8i8\|v4i16\|v2i32\|v1i64)")>; 822 (instregex "(VQADD\|VQSUB)(u\|s)(v8i8\|v4i16\|v2i32\|v1i64)")>;`
H A D	ARMISelLowering.cpp	218 VT != MVT::v2i64 && VT != MVT::v1i64) in addTypeForNEON() 800 addDRTypeForNEON(MVT::v1i64); in ARMTargetLowering() 893 setOperationAction(ISD::MUL, MVT::v1i64, Expand); in ARMTargetLowering() 926 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom); in ARMTargetLowering() 929 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand); in ARMTargetLowering() 936 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom); in ARMTargetLowering() 946 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom); in ARMTargetLowering() 1585 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: in findRepresentativeClass() 5743 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; in LowerFCOPYSIGN() 5757 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64, in LowerFCOPYSIGN() [all …]
H A D	ARMISelDAGToDAG.cpp	`2103 case MVT::v1i64: OpcodeIndex = 3; break; in SelectVLD() 2248 case MVT::v1i64: OpcodeIndex = 3; break; in SelectVST() 2961 case MVT::v1i64: OpcodeIndex = 3; break; in SelectVLDDup()`
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A D	AArch64ISelDAGToDAG.cpp	4240 } else if (VT == MVT::v1i64 \|\| VT == MVT::v1f64) { in Select() 4268 } else if (VT == MVT::v1i64 \|\| VT == MVT::v1f64) { in Select() 4296 } else if (VT == MVT::v1i64 \|\| VT == MVT::v1f64) { in Select() 4324 } else if (VT == MVT::v1i64 \|\| VT == MVT::v1f64) { in Select() 4352 } else if (VT == MVT::v1i64 \|\| VT == MVT::v1f64) { in Select() 4380 } else if (VT == MVT::v1i64 \|\| VT == MVT::v1f64) { in Select() 4408 } else if (VT == MVT::v1i64 \|\| VT == MVT::v1f64) { in Select() 4436 } else if (VT == MVT::v1i64 \|\| VT == MVT::v1f64) { in Select() 4464 } else if (VT == MVT::v1i64 \|\| VT == MVT::v1f64) { in Select() 4492 } else if (VT == MVT::v1i64 \|\| VT == MVT::v1f64) { in Select() [all …]
H A D	AArch64SchedA57.td	348 // D form - v1i8, v1i16, v1i32, v1i64 380 …ite_5cyc_1W_Mul_Forward], (instregex "^MUL(v8i8\|v4i16\|v2i32\|v1i8\|v1i16\|v1i32\|v1i64)(_indexed)?$")>; 408 def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64\|v2i64)")>; 424 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8\|v1i16\|v1i32\|v1i64\|v8i8\|v4i16\|v2… 437 // D form - v1i32, v1i64 459 …InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32\|v1i32\|v2i32\|v1i64)")>; 490 def : InstRW<[A57Write_5cyc_1V_FP_Forward], (instregex "^FMULX?(v2f32\|v1i32\|v2i32\|v1i64\|32\|64)")>; 504 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32\|v1i32\|v2i32\|v1i64)")>; 519 // D form - v1i8, v1i16, v1i32, v1i64 533 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP\|RSQRT)(E\|X)(v2f32\|v1i32\|v2i32\|v1i64)")>; [all …]
H A D	AArch64SchedFalkorDetails.td	591 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ\|LE\|GE\|GT\|LT)(v1i32\|v1i64\|v2i32)rz$")>; 598 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVT(N\|M\|P\|Z\|A)(S\|U)(v1i32\|v1i64\|v2f32)$")>; 658 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^ADD(v1i64\|v2i32\|v4i16\|v8i8)$")>; 662 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^NEG(v1i64\|v2i32\|v4i16\|v8i8)$")>; 663 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^SUB(v1i64\|v2i32\|v4i16\|v8i8)$")>; 670 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ\|GE\|HS\|GT\|HI)(v1i64\|v2i32\|v4i16\|v8i8)$")>; 671 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ\|LE\|GE\|GT\|LT)(v1i64\|v2i32\|v4i16\|v8i8)rz$")>; 672 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CMTST(v1i64\|v2i32\|v4i16\|v8i8)$")>; 694 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8\|v1i16\|v1i32\|v1i64\|v2i32\|v4i16\|v8i8)$"… 695 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8\|v1i16\|v1i32\|v1i64)$")>; [all …]
H A D	AArch64InstrInfo.td	6339 def : Pat<(v1i64 (AArch64vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn), 6353 def : Pat<(v1i64 (AArch64vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn), 7112 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>; 7249 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>; 7250 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>; 7251 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>; 7252 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>; 7253 def : Pat<(v1i64 (bitconvert (v4bf16 FPR64:$src))), (v1i64 FPR64:$src)>; 7254 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>; 7270 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>; [all …]
H A D	AArch64CallingConvention.td	112 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 121 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16], 156 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 238 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 255 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16], 276 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 298 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 360 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
H A D	AArch64SchedKryoDetails.td	147 (instregex "(S\|U)CVTF(v1i32\|v2i32\|v1i64\|v2f32\|d\|s)(_shift)?")>; 213 (instregex "(S\|U\|SU\|US)QADD(v1i8\|v1i16\|v2i16\|v1i32\|v1i64)")>; 261 (instregex "(S\|U)QSUB(v8i8\|v4i16\|v2i32\|v1i64\|v1i32\|v1i16\|v1i8)")>; 285 (instregex "(S\|U)SHL(d\|v8i8\|v4i16\|v2i32\|v1i64)$")>; 375 (instregex "(ADD\|SUB)(v8i8\|v4i16\|v2i32\|v1i64)")>; 513 (instregex "CM(EQ\|GE\|HS\|GT\|HI\|TST)(v8i8\|v4i16\|v2i32\|v1i64)$")>; 525 (instregex "CM(EQ\|LE\|GE\|GT\|LT)(v8i8\|v4i16\|v2i32\|v1i64)rz$")>; 693 (instregex "FCM(EQ\|LE\|GE\|GT\|LT)(v1i32\|v1i64)rz")>; 771 (instregex "FCVTZ(S\|U)(v2f32\|v1i32\|v1i64\|v2i32(_shift)?)$")>; 1668 (instregex "NEG(v8i8\|v4i16\|v2i32\|v1i64)")>; [all …]
H A D	AArch64SchedTSV110.td	`523 // D form - v1i8, v1i16, v1i32, v1i64 553 …0Wr_4cyc_1FSU1], (instregex "^(MUL\|ML[AS]\|SQR?D(MULH))(v8i8\|v4i16\|v2i32\|v1i8\|v1i16\|v1i32\|v1i64)")>; 560 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v1i64\|v2i64)")>; 574 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v1i8\|v1i16\|v1i32\|v1i64\|v8i8\|v4i16… 601 // D form - v1i32, v1i64`
H A D	AArch64InstrFormats.td	5357 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS), 5615 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS), 5834 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd), 6778 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>; 6784 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>; 7006 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>; 7043 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn))), 7058 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))), 8940 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))), 8953 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn), [all …]
H A D	AArch64SchedThunderX2T99.td	`1274 def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^PMULL(v1i64\|v2i64)")>; 1306 "(v8i8\|v4i16\|v2i32\|v1i8\|v1i16\|v1i32\|v1i64)" # 1335 "(v1i8\|v1i16\|v1i32\|v1i64\|v8i8\|v4i16\|v2i32\|b\|d\|h\|s)")>; 1342 (instregex "(ADD\|SUB)(v8i8\|v4i16\|v2i32\|v1i64)")>; 1421 (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32\|v1i32\|v2i32\|v1i64)")>; 1458 (instregex "^FMULX?(v2f32\|v1i32\|v2i32\|v1i64\|32\|64)")>; 1468 (instregex "^FML[AS](v2f32\|v1i32\|v2i32\|v1i64)")>;`
H A D	AArch64SchedThunderX3T110.td	`1382 def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^PMULL(v1i64\|v2i64)")>; 1414 "(v8i8\|v4i16\|v2i32\|v1i8\|v1i16\|v1i32\|v1i64)" # 1443 "(v1i8\|v1i16\|v1i32\|v1i64\|v8i8\|v4i16\|v2i32\|b\|d\|h\|s)")>; 1450 (instregex "(ADD\|SUB)(v8i8\|v4i16\|v2i32\|v1i64)")>; 1529 (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32\|v1i32\|v2i32\|v1i64)")>; 1567 (instregex "^FMULX?(v2f32\|v1i32\|v2i32\|v1i64\|32\|64)")>; 1578 (instregex "^FML[AS](v2f32\|v1i32\|v2i32\|v1i64)")>;`
H A D	AArch64ISelLowering.cpp	264 addDRTypeForNEON(MVT::v1i64); in AArch64TargetLowering() 989 setOperationAction(ISD::MUL, MVT::v1i64, Expand); in AArch64TargetLowering() 1286 setOperationAction(ISD::CTLZ, MVT::v1i64, Custom); in AArch64TargetLowering() 1288 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom); in AArch64TargetLowering() 1289 setOperationAction(ISD::MUL, MVT::v1i64, Custom); in AArch64TargetLowering() 1301 setOperationAction(ISD::SDIV, MVT::v1i64, Custom); in AArch64TargetLowering() 1303 setOperationAction(ISD::SMAX, MVT::v1i64, Custom); in AArch64TargetLowering() 1305 setOperationAction(ISD::SMIN, MVT::v1i64, Custom); in AArch64TargetLowering() 1313 setOperationAction(ISD::UDIV, MVT::v1i64, Custom); in AArch64TargetLowering() 1315 setOperationAction(ISD::UMAX, MVT::v1i64, Custom); in AArch64TargetLowering() [all …]
H A D	AArch64SchedA64FX.td	`1650 def : InstRW<[A64FXWrite_8Cyc_GI03], (instregex "^PMULL(v1i64\|v2i64)")>; 1682 "(v8i8\|v4i16\|v2i32\|v1i8\|v1i16\|v1i32\|v1i64)" # 1723 "(v1i8\|v1i16\|v1i32\|v1i64\|v8i8\|v4i16\|v2i32\|b\|d\|h\|s)")>; 1730 (instregex "(ADD\|SUB)(v8i8\|v4i16\|v2i32\|v1i64)")>; 1814 (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32\|v1i32\|v2i32\|v1i64)")>; 1851 (instregex "^FMULX?(v2f32\|v1i32\|v2i32\|v1i64\|32\|64)")>; 1861 (instregex "^FML[AS](v2f32\|v1i32\|v2i32\|v1i64)")>;`
H A D	AArch64RegisterInfo.td	`437 v1i64, v4f16, v4bf16], 440 [v8i8, v4i16, v2i32, v1i64, v4f16, v4bf16, v2f32,`
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A D	MachineValueType.h	`109 v1i64 = 59, // 1 x i64 enumerator 384 SimpleTy == MVT::v1i64 \|\| SimpleTy == MVT::v4f16 \|\| in is64BitVector() 576 case v1i64: in getVectorElementType() 792 case v1i64: in getVectorMinNumElements() 892 case v1i64: in getSizeInBits() 1186 if (NumElements == 1) return MVT::v1i64; in getVectorVT()`
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A D	ValueTypes.td	`85 def v1i64 : ValueType<64, 59>; // 1 x i64 vector value`
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A D	ValueTypes.cpp	`290 case MVT::v1i64: in getTypeForEVT()`
/netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/
H A D	CodeGenTarget.cpp	`125 case MVT::v1i64: return "MVT::v1i64"; in getEnumName()`