| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
| H A D | MachineValueType.h | 73 v1i8 = 26, // 1 x i8 enumerator
524 case v1i8: in getVectorElementType()
789 case v1i8: in getVectorMinNumElements()
850 case v1i8: in getSizeInBits()
1147 if (NumElements == 1) return MVT::v1i8; in getVectorVT()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedA57.td | 348 // D form - v1i8, v1i16, v1i32, v1i64
380 def : InstRW<[A57Write_5cyc_1W_Mul_Forward], (instregex "^MUL(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i…
382 def : InstRW<[A57Write_5cyc_1W], (instregex "^(PMUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1…
424 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
519 // D form - v1i8, v1i16, v1i32, v1i64
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| H A D | AArch64SchedFalkorDetails.td | 681 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
683 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2…
685 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
690 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v…
694 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$"…
695 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>;
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| H A D | AArch64SchedTSV110.td | 523 // D form - v1i8, v1i16, v1i32, v1i64
553 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v8i8|v4i16|v2i32|v1i8|v1i…
574 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16…
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| H A D | AArch64SchedKryoDetails.td | 213 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>;
231 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;
261 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>;
273 (instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>;
1824 (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>;
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| H A D | AArch64SchedThunderX2T99.td | 1306 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1335 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
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| H A D | AArch64SchedThunderX3T110.td | 1414 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1443 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
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| H A D | AArch64SchedA64FX.td | 1682 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1723 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
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| H A D | AArch64InstrFormats.td | 6787 def v1i8 : BaseSIMDThreeScalar<U, 0b001, opc, FPR8 , asm, []>;
7040 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR8 , asm, []>;
7055 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
7070 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR16, asm, []>;
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| H A D | AArch64ISelLowering.cpp | 16820 if (VT == MVT::v1i8 || VT == MVT::v1i16 || VT == MVT::v1i32 || in getPreferredVectorAction()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.td | 49 def v1i8 : ValueType<8, 26>; // 1 x i8 vector value
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | ValueTypes.cpp | 224 case MVT::v1i8: in getTypeForEVT()
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| /netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 93 case MVT::v1i8: return "MVT::v1i8"; in getEnumName()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | Intrinsics.td | 275 def llvm_v1i8_ty : LLVMType<v1i8>; // 1 x i8
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1419 assert(IntegerViaVecVT == MVT::v1i8 && "Unexpected mask vector type"); in lowerBUILD_VECTOR()
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