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Searched refs:GENMASK (Results 1 – 25 of 52) sorted by relevance

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/openbsd/sys/dev/ic/
H A Dqwxreg.h126 #define WMI_TLV_LEN GENMASK(15, 0)
127 #define WMI_TLV_TAG GENMASK(31, 16)
130 #define WMI_CMD_HDR_CMD_ID GENMASK(23, 0)
3538 #define WMI_CHAN_INFO_MODE GENMASK(5, 0)
7850 #define HAL_TLV_HDR_TAG GENMASK(9, 1)
7851 #define HAL_TLV_HDR_LEN GENMASK(25, 10)
7852 #define HAL_TLV_USR_ID GENMASK(31, 26)
12628 #define HTT_T2H_MSG_TYPE GENMASK(7, 0)
12779 #define HTT_TLV_TAG GENMASK(11, 0)
12780 #define HTT_TLV_LEN GENMASK(23, 12)
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H A Dqwzreg.h122 #define WMI_TLV_LEN GENMASK(15, 0)
123 #define WMI_TLV_TAG GENMASK(31, 16)
126 #define WMI_CMD_HDR_CMD_ID GENMASK(23, 0)
3534 #define WMI_CHAN_INFO_MODE GENMASK(5, 0)
8040 #define HAL_TLV_HDR_TAG GENMASK(9, 1)
8041 #define HAL_TLV_HDR_LEN GENMASK(25, 10)
8042 #define HAL_TLV_USR_ID GENMASK(31, 26)
8051 #define HAL_TLV_64_HDR_TAG GENMASK(9, 1)
13059 #define HTT_T2H_MSG_TYPE GENMASK(7, 0)
13210 #define HTT_TLV_TAG GENMASK(11, 0)
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H A Dqwzvar.h492 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1)
493 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10)
987 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
988 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18)
993 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
994 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
995 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
1044 #define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0)
1045 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9)
1047 #define DP_REO_QREF_NUM GENMASK(31, 16)
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H A Dqwxvar.h512 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1)
513 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10)
992 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
993 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18)
998 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
999 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
1000 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
/openbsd/sys/dev/pci/drm/i915/gt/uc/
H A Dguc_capture_fwif.h71 #define GUC_CAPTURELISTHDR_NUMDESCR GENMASK(15, 0)
115 #define CAP_HDR_CAPTURE_VFID GENMASK(7, 0)
117 #define CAP_HDR_CAPTURE_TYPE GENMASK(3, 0) /* see enum guc_capture_type */
118 #define CAP_HDR_ENGINE_CLASS GENMASK(7, 4) /* see GUC_MAX_ENGINE_CLASSES */
119 #define CAP_HDR_ENGINE_INSTANCE GENMASK(11, 8)
123 #define CAP_HDR_NUM_MMIOS GENMASK(9, 0)
139 #define CAP_GRP_HDR_CAPTURE_VFID GENMASK(7, 0)
141 #define CAP_GRP_HDR_NUM_CAPTURES GENMASK(7, 0)
142 #define CAP_GRP_HDR_CAPTURE_TYPE GENMASK(15, 8) /* guc_capture_group_types */
H A Dintel_guc_fwif.h66 #define WQ_TYPE_MASK GENMASK(7, 0)
67 #define WQ_LEN_MASK GENMASK(26, 16)
69 #define WQ_GUC_ID_MASK GENMASK(15, 0)
70 #define WQ_RING_TAIL_MASK GENMASK(28, 18)
374 #define GUC_REGSET_STEERING_GROUP GENMASK(15, 12)
375 #define GUC_REGSET_STEERING_INSTANCE GENMASK(23, 20)
H A Dintel_gsc_binary_headers.h72 #define INTEL_GSC_BPDT_ENTRY_TYPE_MASK GENMASK(15, 0)
102 #define INTEL_GSC_CPD_ENTRY_OFFSET_MASK GENMASK(24, 0)
H A Dintel_gsc_proxy.c58 #define GSC_PROXY_TYPE GENMASK(7, 0)
59 #define GSC_PROXY_PAYLOAD_LENGTH GENMASK(31, 16)
/openbsd/sys/dev/pci/drm/i915/pxp/
H A Dintel_pxp_cmd_interface_cmn.h34 #define PXP_CMDHDR_EXTDATA_SESSION_VALID GENMASK(0, 0)
35 #define PXP_CMDHDR_EXTDATA_APP_TYPE GENMASK(1, 1)
36 #define PXP_CMDHDR_EXTDATA_SESSION_ID GENMASK(17, 2)
H A Dintel_pxp_cmd_interface_43.h47 #define PXP43_INIT_SESSION_APPID GENMASK(17, 2)
/openbsd/sys/dev/pci/drm/apple/
H A Ddptxep.h35 #define DCPDPTX_REMOTE_PORT_CORE GENMASK(3, 0)
36 #define DCPDPTX_REMOTE_PORT_ATC GENMASK(7, 4)
37 #define DCPDPTX_REMOTE_PORT_DIE GENMASK(11, 8)
H A Dafk.c19 #define RBEP_TYPE GENMASK(63, 48)
38 #define GETBUF_SIZE GENMASK(31, 16)
39 #define GETBUF_TAG GENMASK(15, 0)
40 #define GETBUF_ACK_DVA GENMASK(47, 0)
42 #define INITRB_OFFSET GENMASK(47, 32)
43 #define INITRB_SIZE GENMASK(31, 16)
44 #define INITRB_TAG GENMASK(15, 0)
46 #define SEND_WPTR GENMASK(31, 0)
/openbsd/sys/dev/pci/
H A Dif_mwxreg.h97 #define MT_WTBL_LMAC_ID GENMASK(14, 8)
98 #define MT_WTBL_LMAC_DW GENMASK(7, 2)
108 #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16)
673 #define MT_TXD3_SEQ GENMASK(27, 16)
676 #define MT_TXD3_TX_COUNT GENMASK(10, 6)
715 #define MT_TXD7_PSE_FID GENMASK(27, 16)
716 #define MT_TXD7_SPE_IDX GENMASK(15, 11)
811 #define MT_RXD4_NORMAL_OFLD GENMASK(12, 11)
813 #define MT_RXD4_NORMAL_WOL GENMASK(18, 14)
814 #define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19)
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H A Dif_qwz_pci.c185 #define MHI_CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)
208 #define MHI_EV_CTX_RESERVED_MASK GENMASK(7, 0)
209 #define MHI_EV_CTX_INTMODC_MASK GENMASK(15, 8)
210 #define MHI_EV_CTX_INTMODT_MASK GENMASK(31, 16)
2134 #define MHI_CFG_NHWER_MASK GENMASK(31, 24)
2136 #define MHI_CFG_NER_MASK GENMASK(23, 16)
2138 #define MHI_CFG_NHWCH_MASK GENMASK(15, 8)
2140 #define MHI_CFG_NCH_MASK GENMASK(7, 0)
2214 #define MHI_BHI_STATUS_MASK GENMASK(31, 30)
2263 #define MHI_TRE_CMD_CHID_MASK GENMASK(31, 24)
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H A Dif_qwx_pci.c181 #define MHI_CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)
204 #define MHI_EV_CTX_RESERVED_MASK GENMASK(7, 0)
205 #define MHI_EV_CTX_INTMODC_MASK GENMASK(15, 8)
206 #define MHI_EV_CTX_INTMODT_MASK GENMASK(31, 16)
2202 #define MHI_CFG_NHWER_MASK GENMASK(31, 24)
2204 #define MHI_CFG_NER_MASK GENMASK(23, 16)
2206 #define MHI_CFG_NHWCH_MASK GENMASK(15, 8)
2208 #define MHI_CFG_NCH_MASK GENMASK(7, 0)
2282 #define MHI_BHI_STATUS_MASK GENMASK(31, 30)
2331 #define MHI_TRE_CMD_CHID_MASK GENMASK(31, 24)
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/openbsd/sys/dev/pci/drm/i915/gvt/
H A Dcmd_parser.c1034 (cmd_val(s, i) & GENMASK(22, 2))
1037 (cmd_val(s, i) & GENMASK(22, 18))
1040 (cmd_val(s, i) & GENMASK(31, 2))
1043 (cmd_val(s, i) & GENMASK(15, 0))
1202 gma = cmd_val(s, 2) & GENMASK(31, 3); in cmd_handler_pipe_control()
1303 v = (dword0 & GENMASK(21, 19)) >> 19; in gen8_decode_mi_display_flip()
1400 GENMASK(12, 10)) >> 10; in gen8_check_mi_display_flip()
1403 GENMASK(15, 6)) >> 6; in gen8_check_mi_display_flip()
1622 gma = cmd_val(s, 2) & GENMASK(31, 2); in cmd_handler_mi_store_data_imm()
1678 gma = cmd_val(s, 1) & GENMASK(31, 2); in cmd_handler_mi_op_2f()
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/openbsd/sys/dev/pci/drm/i915/
H A Di915_reg_defs.h48 ((u32)(GENMASK(__high, __low) + \
78 ((u8)(GENMASK(__high, __low) + \
171 ((u16)(GENMASK(__high, __low) + \
H A Di915_params.h35 #define ENABLE_GUC_MASK GENMASK(1, 0)
H A Dintel_step.c279 #define PVC_BD_REVID GENMASK(5, 3)
280 #define PVC_CT_REVID GENMASK(2, 0)
/openbsd/sys/dev/pci/drm/include/drm/
H A Ddrm_displayid.h131 #define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)
132 #define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)
/openbsd/sys/dev/pci/drm/i915/gt/
H A Dintel_lrc.h90 #define CTX_GTT_ADDRESS_MASK GENMASK(31, 12)
97 #define GEN12_CTX_PRIORITY_MASK GENMASK(10, 9)
H A Dintel_gpu_commands.h231 #define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 25)
243 #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfxhub_v1_2.c70 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_setup_vm_pt_regs()
427 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_gart_enable()
466 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_gart_disable()
524 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_set_fault_enable_default()
573 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_init()
/openbsd/sys/dev/pci/drm/i915/display/
H A Dintel_frontbuffer.h65 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
/openbsd/sys/dev/pci/drm/include/linux/
H A Dbitops.h33 #define GENMASK(h, l) (((~0UL) >> (BITS_PER_LONG - (h) - 1)) & ((~0UL) << (l))) macro

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