1 /* $OpenBSD: if_qwx_pci.c,v 1.23 2024/10/04 07:46:33 kevlo Exp $ */
2
3 /*
4 * Copyright 2023 Stefan Sperling <stsp@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 /*
20 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc.
21 * Copyright (c) 2018-2021 The Linux Foundation.
22 * All rights reserved.
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted (subject to the limitations in the disclaimer
26 * below) provided that the following conditions are met:
27 *
28 * * Redistributions of source code must retain the above copyright notice,
29 * this list of conditions and the following disclaimer.
30 *
31 * * Redistributions in binary form must reproduce the above copyright
32 * notice, this list of conditions and the following disclaimer in the
33 * documentation and/or other materials provided with the distribution.
34 *
35 * * Neither the name of [Owner Organization] nor the names of its
36 * contributors may be used to endorse or promote products derived from
37 * this software without specific prior written permission.
38 *
39 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY
40 * THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
41 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
42 * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
43 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
44 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
45 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
46 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
47 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
48 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
49 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
50 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 */
52
53 #include "bpfilter.h"
54
55 #include <sys/param.h>
56 #include <sys/mbuf.h>
57 #include <sys/lock.h>
58 #include <sys/socket.h>
59 #include <sys/systm.h>
60 #include <sys/malloc.h>
61 #include <sys/device.h>
62 #include <sys/endian.h>
63
64 #include <machine/bus.h>
65 #include <machine/intr.h>
66
67 #include <net/if.h>
68 #include <net/if_media.h>
69
70 #include <netinet/in.h>
71 #include <netinet/if_ether.h>
72
73 #include <net80211/ieee80211_var.h>
74 #include <net80211/ieee80211_radiotap.h>
75
76 #include <dev/pci/pcireg.h>
77 #include <dev/pci/pcivar.h>
78 #include <dev/pci/pcidevs.h>
79
80 /* XXX linux porting goo */
81 #ifdef __LP64__
82 #define BITS_PER_LONG 64
83 #else
84 #define BITS_PER_LONG 32
85 #endif
86 #define GENMASK(h, l) (((~0UL) >> (BITS_PER_LONG - (h) - 1)) & ((~0UL) << (l)))
87 #define __bf_shf(x) (__builtin_ffsll(x) - 1)
88 #define FIELD_GET(_m, _v) ((typeof(_m))(((_v) & (_m)) >> __bf_shf(_m)))
89 #define BIT(x) (1UL << (x))
90 #define test_bit(i, a) ((a) & (1 << (i)))
91 #define clear_bit(i, a) ((a)) &= ~(1 << (i))
92 #define set_bit(i, a) ((a)) |= (1 << (i))
93
94 /* #define QWX_DEBUG */
95
96 #include <dev/ic/qwxreg.h>
97 #include <dev/ic/qwxvar.h>
98
99 #ifdef QWX_DEBUG
100 /* Headers needed for RDDM dump */
101 #include <sys/namei.h>
102 #include <sys/pledge.h>
103 #include <sys/vnode.h>
104 #include <sys/fcntl.h>
105 #include <sys/stat.h>
106 #include <sys/proc.h>
107 #endif
108
109 #define ATH11K_PCI_IRQ_CE0_OFFSET 3
110 #define ATH11K_PCI_IRQ_DP_OFFSET 14
111
112 #define ATH11K_PCI_CE_WAKE_IRQ 2
113
114 #define ATH11K_PCI_WINDOW_ENABLE_BIT 0x40000000
115 #define ATH11K_PCI_WINDOW_REG_ADDRESS 0x310c
116 #define ATH11K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
117 #define ATH11K_PCI_WINDOW_START 0x80000
118 #define ATH11K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
119
120 /* BAR0 + 4k is always accessible, and no need to force wakeup. */
121 #define ATH11K_PCI_ACCESS_ALWAYS_OFF 0xFE0 /* 4K - 32 = 0xFE0 */
122
123 #define TCSR_SOC_HW_VERSION 0x0224
124 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
125 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
126
127 /*
128 * pci.h
129 */
130 #define PCIE_SOC_GLOBAL_RESET 0x3008
131 #define PCIE_SOC_GLOBAL_RESET_V 1
132
133 #define WLAON_WARM_SW_ENTRY 0x1f80504
134 #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c
135
136 #define PCIE_Q6_COOKIE_ADDR 0x01f80500
137 #define PCIE_Q6_COOKIE_DATA 0xc0000000
138
139 /* register to wake the UMAC from power collapse */
140 #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040
141
142 /* register used for handshake mechanism to validate UMAC is awake */
143 #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004
144
145 #define PCIE_PCIE_PARF_LTSSM 0x1e081b0
146 #define PARM_LTSSM_VALUE 0x111
147
148 #define GCC_GCC_PCIE_HOT_RST 0x1e402bc
149 #define GCC_GCC_PCIE_HOT_RST_VAL 0x10
150
151 #define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228
152 #define PCIE_SMLH_REQ_RST_LINK_DOWN 0x2
153 #define PCIE_INT_CLEAR_ALL 0xffffffff
154
155 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(sc) \
156 (sc->hw_params.regs->pcie_qserdes_sysclk_en_sel)
157 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL 0x10
158 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK 0xffffffff
159 #define PCIE_PCS_OSC_DTCT_CONFIG1_REG(sc) \
160 (sc->hw_params.regs->pcie_pcs_osc_dtct_config_base)
161 #define PCIE_PCS_OSC_DTCT_CONFIG1_VAL 0x02
162 #define PCIE_PCS_OSC_DTCT_CONFIG2_REG(sc) \
163 (sc->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0x4)
164 #define PCIE_PCS_OSC_DTCT_CONFIG2_VAL 0x52
165 #define PCIE_PCS_OSC_DTCT_CONFIG4_REG(sc) \
166 (sc->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0xc)
167 #define PCIE_PCS_OSC_DTCT_CONFIG4_VAL 0xff
168 #define PCIE_PCS_OSC_DTCT_CONFIG_MSK 0x000000ff
169
170 #define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
171 #define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
172
173 /*
174 * mhi.h
175 */
176 #define PCIE_TXVECDB 0x360
177 #define PCIE_TXVECSTATUS 0x368
178 #define PCIE_RXVECDB 0x394
179 #define PCIE_RXVECSTATUS 0x39C
180
181 #define MHI_CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)
182 #define MHI_CHAN_CTX_CHSTATE_DISABLED 0
183 #define MHI_CHAN_CTX_CHSTATE_ENABLED 1
184 #define MHI_CHAN_CTX_CHSTATE_RUNNING 2
185 #define MHI_CHAN_CTX_CHSTATE_SUSPENDED 3
186 #define MHI_CHAN_CTX_CHSTATE_STOP 4
187 #define MHI_CHAN_CTX_CHSTATE_ERROR 5
188 #define MHI_CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8)
189 #define MHI_CHAN_CTX_BRSTMODE_SHFT 8
190 #define MHI_CHAN_CTX_BRSTMODE_DISABLE 2
191 #define MHI_CHAN_CTX_BRSTMODE_ENABLE 3
192 #define MHI_CHAN_CTX_POLLCFG_MASK GENMASK(15, 10)
193 #define MHI_CHAN_CTX_RESERVED_MASK GENMASK(31, 16)
194
195 #define QWX_MHI_CONFIG_QCA6390_MAX_CHANNELS 128
196 #define QWX_MHI_CONFIG_QCA6390_TIMEOUT_MS 2000
197 #define QWX_MHI_CONFIG_QCA9074_MAX_CHANNELS 30
198
199 #define MHI_CHAN_TYPE_INVALID 0
200 #define MHI_CHAN_TYPE_OUTBOUND 1 /* to device */
201 #define MHI_CHAN_TYPE_INBOUND 2 /* from device */
202 #define MHI_CHAN_TYPE_INBOUND_COALESCED 3
203
204 #define MHI_EV_CTX_RESERVED_MASK GENMASK(7, 0)
205 #define MHI_EV_CTX_INTMODC_MASK GENMASK(15, 8)
206 #define MHI_EV_CTX_INTMODT_MASK GENMASK(31, 16)
207 #define MHI_EV_CTX_INTMODT_SHFT 16
208
209 #define MHI_ER_TYPE_INVALID 0
210 #define MHI_ER_TYPE_VALID 1
211
212 #define MHI_ER_DATA 0
213 #define MHI_ER_CTRL 1
214
215 #define MHI_CH_STATE_DISABLED 0
216 #define MHI_CH_STATE_ENABLED 1
217 #define MHI_CH_STATE_RUNNING 2
218 #define MHI_CH_STATE_SUSPENDED 3
219 #define MHI_CH_STATE_STOP 4
220 #define MHI_CH_STATE_ERROR 5
221
222 #define QWX_NUM_EVENT_CTX 2
223
224 /* Event context. Shared with device. */
225 struct qwx_mhi_event_ctxt {
226 uint32_t intmod;
227 uint32_t ertype;
228 uint32_t msivec;
229
230 uint64_t rbase;
231 uint64_t rlen;
232 uint64_t rp;
233 uint64_t wp;
234 } __packed;
235
236 /* Channel context. Shared with device. */
237 struct qwx_mhi_chan_ctxt {
238 uint32_t chcfg;
239 uint32_t chtype;
240 uint32_t erindex;
241
242 uint64_t rbase;
243 uint64_t rlen;
244 uint64_t rp;
245 uint64_t wp;
246 } __packed;
247
248 /* Command context. Shared with device. */
249 struct qwx_mhi_cmd_ctxt {
250 uint32_t reserved0;
251 uint32_t reserved1;
252 uint32_t reserved2;
253
254 uint64_t rbase;
255 uint64_t rlen;
256 uint64_t rp;
257 uint64_t wp;
258 } __packed;
259
260 struct qwx_mhi_ring_element {
261 uint64_t ptr;
262 uint32_t dword[2];
263 };
264
265 struct qwx_xfer_data {
266 bus_dmamap_t map;
267 struct mbuf *m;
268 };
269
270 #define QWX_PCI_XFER_MAX_DATA_SIZE 0xffff
271 #define QWX_PCI_XFER_RING_MAX_ELEMENTS 64
272
273 struct qwx_pci_xfer_ring {
274 struct qwx_dmamem *dmamem;
275 bus_size_t size;
276 uint32_t mhi_chan_id;
277 uint32_t mhi_chan_state;
278 uint32_t mhi_chan_direction;
279 uint32_t mhi_chan_event_ring_index;
280 uint32_t db_addr;
281 uint32_t cmd_status;
282 int num_elements;
283 int queued;
284 struct qwx_xfer_data data[QWX_PCI_XFER_RING_MAX_ELEMENTS];
285 uint64_t rp;
286 uint64_t wp;
287 struct qwx_mhi_chan_ctxt *chan_ctxt;
288 };
289
290
291 #define QWX_PCI_EVENT_RING_MAX_ELEMENTS 256
292
293 struct qwx_pci_event_ring {
294 struct qwx_dmamem *dmamem;
295 bus_size_t size;
296 uint32_t mhi_er_type;
297 uint32_t mhi_er_irq;
298 uint32_t mhi_er_irq_moderation_ms;
299 uint32_t db_addr;
300 int num_elements;
301 uint64_t rp;
302 uint64_t wp;
303 struct qwx_mhi_event_ctxt *event_ctxt;
304 };
305
306 struct qwx_cmd_data {
307 bus_dmamap_t map;
308 struct mbuf *m;
309 };
310
311 #define QWX_PCI_CMD_RING_MAX_ELEMENTS 128
312
313 struct qwx_pci_cmd_ring {
314 struct qwx_dmamem *dmamem;
315 bus_size_t size;
316 uint64_t rp;
317 uint64_t wp;
318 int num_elements;
319 int queued;
320 };
321
322 struct qwx_pci_ops;
323 struct qwx_msi_config;
324
325 #define QWX_NUM_MSI_VEC 32
326
327 struct qwx_pci_softc {
328 struct qwx_softc sc_sc;
329 pci_chipset_tag_t sc_pc;
330 pcitag_t sc_tag;
331 int sc_cap_off;
332 int sc_msi_off;
333 pcireg_t sc_msi_cap;
334 void *sc_ih[QWX_NUM_MSI_VEC];
335 char sc_ivname[QWX_NUM_MSI_VEC][16];
336 struct qwx_ext_irq_grp ext_irq_grp[ATH11K_EXT_IRQ_GRP_NUM_MAX];
337 int mhi_irq[2];
338 bus_space_tag_t sc_st;
339 bus_space_handle_t sc_sh;
340 bus_addr_t sc_map;
341 bus_size_t sc_mapsize;
342
343 pcireg_t sc_lcsr;
344 uint32_t sc_flags;
345 #define ATH11K_PCI_ASPM_RESTORE 1
346
347 uint32_t register_window;
348 const struct qwx_pci_ops *sc_pci_ops;
349
350 uint32_t bhi_off;
351 uint32_t bhi_ee;
352 uint32_t bhie_off;
353 uint32_t mhi_state;
354 uint32_t max_chan;
355
356 uint64_t wake_db;
357
358 /*
359 * DMA memory for AMSS.bin firmware image.
360 * This memory must remain available to the device until
361 * the device is powered down.
362 */
363 struct qwx_dmamem *amss_data;
364 struct qwx_dmamem *amss_vec;
365
366 struct qwx_dmamem *rddm_vec;
367 struct qwx_dmamem *rddm_data;
368 int rddm_triggered;
369 struct task rddm_task;
370 #define QWX_RDDM_DUMP_SIZE 0x420000
371
372 struct qwx_dmamem *chan_ctxt;
373 struct qwx_dmamem *event_ctxt;
374 struct qwx_dmamem *cmd_ctxt;
375
376
377 struct qwx_pci_xfer_ring xfer_rings[2];
378 #define QWX_PCI_XFER_RING_IPCR_OUTBOUND 0
379 #define QWX_PCI_XFER_RING_IPCR_INBOUND 1
380 struct qwx_pci_event_ring event_rings[QWX_NUM_EVENT_CTX];
381 struct qwx_pci_cmd_ring cmd_ring;
382 };
383
384 int qwx_pci_match(struct device *, void *, void *);
385 void qwx_pci_attach(struct device *, struct device *, void *);
386 int qwx_pci_detach(struct device *, int);
387 void qwx_pci_attach_hook(struct device *);
388 void qwx_pci_free_xfer_rings(struct qwx_pci_softc *);
389 int qwx_pci_alloc_xfer_ring(struct qwx_softc *, struct qwx_pci_xfer_ring *,
390 uint32_t, uint32_t, uint32_t, size_t);
391 int qwx_pci_alloc_xfer_rings_qca6390(struct qwx_pci_softc *);
392 int qwx_pci_alloc_xfer_rings_qcn9074(struct qwx_pci_softc *);
393 void qwx_pci_free_event_rings(struct qwx_pci_softc *);
394 int qwx_pci_alloc_event_ring(struct qwx_softc *,
395 struct qwx_pci_event_ring *, uint32_t, uint32_t, uint32_t, size_t);
396 int qwx_pci_alloc_event_rings(struct qwx_pci_softc *);
397 void qwx_pci_free_cmd_ring(struct qwx_pci_softc *);
398 int qwx_pci_init_cmd_ring(struct qwx_softc *, struct qwx_pci_cmd_ring *);
399 uint32_t qwx_pci_read(struct qwx_softc *, uint32_t);
400 void qwx_pci_write(struct qwx_softc *, uint32_t, uint32_t);
401
402 void qwx_pci_read_hw_version(struct qwx_softc *, uint32_t *, uint32_t *);
403 uint32_t qwx_pcic_read32(struct qwx_softc *, uint32_t);
404 void qwx_pcic_write32(struct qwx_softc *, uint32_t, uint32_t);
405
406 void qwx_pcic_ext_irq_enable(struct qwx_softc *);
407 void qwx_pcic_ext_irq_disable(struct qwx_softc *);
408 int qwx_pcic_config_irq(struct qwx_softc *, struct pci_attach_args *);
409
410 int qwx_pci_start(struct qwx_softc *);
411 void qwx_pci_stop(struct qwx_softc *);
412 void qwx_pci_aspm_disable(struct qwx_softc *);
413 void qwx_pci_aspm_restore(struct qwx_softc *);
414 int qwx_pci_power_up(struct qwx_softc *);
415 void qwx_pci_power_down(struct qwx_softc *);
416
417 int qwx_pci_bus_wake_up(struct qwx_softc *);
418 void qwx_pci_bus_release(struct qwx_softc *);
419 void qwx_pci_window_write32(struct qwx_softc *, uint32_t, uint32_t);
420 uint32_t qwx_pci_window_read32(struct qwx_softc *, uint32_t);
421
422 int qwx_mhi_register(struct qwx_softc *);
423 void qwx_mhi_unregister(struct qwx_softc *);
424 void qwx_mhi_ring_doorbell(struct qwx_softc *sc, uint64_t, uint64_t);
425 void qwx_mhi_device_wake(struct qwx_softc *);
426 void qwx_mhi_device_zzz(struct qwx_softc *);
427 int qwx_mhi_wake_db_clear_valid(struct qwx_softc *);
428 void qwx_mhi_init_xfer_rings(struct qwx_pci_softc *);
429 void qwx_mhi_init_event_rings(struct qwx_pci_softc *);
430 void qwx_mhi_init_cmd_ring(struct qwx_pci_softc *);
431 void qwx_mhi_init_dev_ctxt(struct qwx_pci_softc *);
432 int qwx_mhi_send_cmd(struct qwx_pci_softc *psc, uint32_t, uint32_t);
433 void * qwx_pci_xfer_ring_get_elem(struct qwx_pci_xfer_ring *, uint64_t);
434 struct qwx_xfer_data *qwx_pci_xfer_ring_get_data(struct qwx_pci_xfer_ring *,
435 uint64_t);
436 int qwx_mhi_submit_xfer(struct qwx_softc *sc, struct mbuf *m);
437 int qwx_mhi_start_channel(struct qwx_pci_softc *,
438 struct qwx_pci_xfer_ring *);
439 int qwx_mhi_start_channels(struct qwx_pci_softc *);
440 int qwx_mhi_start(struct qwx_pci_softc *);
441 void qwx_mhi_stop(struct qwx_softc *);
442 int qwx_mhi_reset_device(struct qwx_softc *, int);
443 void qwx_mhi_clear_vector(struct qwx_softc *);
444 int qwx_mhi_fw_load_handler(struct qwx_pci_softc *);
445 int qwx_mhi_await_device_reset(struct qwx_softc *);
446 int qwx_mhi_await_device_ready(struct qwx_softc *);
447 void qwx_mhi_ready_state_transition(struct qwx_pci_softc *);
448 void qwx_mhi_mission_mode_state_transition(struct qwx_pci_softc *);
449 void qwx_mhi_low_power_mode_state_transition(struct qwx_pci_softc *);
450 void qwx_mhi_set_state(struct qwx_softc *, uint32_t);
451 void qwx_mhi_init_mmio(struct qwx_pci_softc *);
452 int qwx_mhi_fw_load_bhi(struct qwx_pci_softc *, uint8_t *, size_t);
453 int qwx_mhi_fw_load_bhie(struct qwx_pci_softc *, uint8_t *, size_t);
454 void qwx_rddm_prepare(struct qwx_pci_softc *);
455 #ifdef QWX_DEBUG
456 void qwx_rddm_task(void *);
457 #endif
458 void * qwx_pci_event_ring_get_elem(struct qwx_pci_event_ring *, uint64_t);
459 void qwx_pci_intr_ctrl_event_mhi(struct qwx_pci_softc *, uint32_t);
460 void qwx_pci_intr_ctrl_event_ee(struct qwx_pci_softc *, uint32_t);
461 void qwx_pci_intr_ctrl_event_cmd_complete(struct qwx_pci_softc *,
462 uint64_t, uint32_t);
463 int qwx_pci_intr_ctrl_event(struct qwx_pci_softc *,
464 struct qwx_pci_event_ring *);
465 void qwx_pci_intr_data_event_tx(struct qwx_pci_softc *,
466 struct qwx_mhi_ring_element *);
467 int qwx_pci_intr_data_event(struct qwx_pci_softc *,
468 struct qwx_pci_event_ring *);
469 int qwx_pci_intr_mhi_ctrl(void *);
470 int qwx_pci_intr_mhi_data(void *);
471 int qwx_pci_intr(void *);
472
473 struct qwx_pci_ops {
474 int (*wakeup)(struct qwx_softc *);
475 void (*release)(struct qwx_softc *);
476 int (*get_msi_irq)(struct qwx_softc *, unsigned int);
477 void (*window_write32)(struct qwx_softc *, uint32_t, uint32_t);
478 uint32_t (*window_read32)(struct qwx_softc *, uint32_t);
479 int (*alloc_xfer_rings)(struct qwx_pci_softc *);
480 };
481
482
483 static const struct qwx_pci_ops qwx_pci_ops_qca6390 = {
484 .wakeup = qwx_pci_bus_wake_up,
485 .release = qwx_pci_bus_release,
486 #if notyet
487 .get_msi_irq = qwx_pci_get_msi_irq,
488 #endif
489 .window_write32 = qwx_pci_window_write32,
490 .window_read32 = qwx_pci_window_read32,
491 .alloc_xfer_rings = qwx_pci_alloc_xfer_rings_qca6390,
492 };
493
494 static const struct qwx_pci_ops qwx_pci_ops_qcn9074 = {
495 .wakeup = NULL,
496 .release = NULL,
497 #if notyet
498 .get_msi_irq = qwx_pci_get_msi_irq,
499 #endif
500 .window_write32 = qwx_pci_window_write32,
501 .window_read32 = qwx_pci_window_read32,
502 .alloc_xfer_rings = qwx_pci_alloc_xfer_rings_qcn9074,
503 };
504
505 const struct cfattach qwx_pci_ca = {
506 sizeof(struct qwx_pci_softc),
507 qwx_pci_match,
508 qwx_pci_attach,
509 qwx_pci_detach,
510 qwx_activate
511 };
512
513 /* XXX pcidev */
514 #define PCI_PRODUCT_QUALCOMM_QCA6390 0x1101
515 #define PCI_PRODUCT_QUALCOMM_QCN9074 0x1104
516
517 static const struct pci_matchid qwx_pci_devices[] = {
518 #if notyet
519 { PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCA6390 },
520 { PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCN9074 },
521 #endif
522 { PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCNFA765 }
523 };
524
525 int
qwx_pci_match(struct device * parent,void * match,void * aux)526 qwx_pci_match(struct device *parent, void *match, void *aux)
527 {
528 return pci_matchbyid(aux, qwx_pci_devices, nitems(qwx_pci_devices));
529 }
530
531 void
qwx_pci_init_qmi_ce_config(struct qwx_softc * sc)532 qwx_pci_init_qmi_ce_config(struct qwx_softc *sc)
533 {
534 struct qwx_qmi_ce_cfg *cfg = &sc->qmi_ce_cfg;
535
536 qwx_ce_get_shadow_config(sc, &cfg->shadow_reg_v2,
537 &cfg->shadow_reg_v2_len);
538 }
539
540 const struct qwx_msi_config qwx_msi_config_one_msi = {
541 .total_vectors = 1,
542 .total_users = 4,
543 .users = (struct qwx_msi_user[]) {
544 { .name = "MHI", .num_vectors = 1, .base_vector = 0 },
545 { .name = "CE", .num_vectors = 1, .base_vector = 0 },
546 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 },
547 { .name = "DP", .num_vectors = 1, .base_vector = 0 },
548 },
549 };
550
551 const struct qwx_msi_config qwx_msi_config[] = {
552 {
553 .total_vectors = 32,
554 .total_users = 4,
555 .users = (struct qwx_msi_user[]) {
556 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
557 { .name = "CE", .num_vectors = 10, .base_vector = 3 },
558 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
559 { .name = "DP", .num_vectors = 18, .base_vector = 14 },
560 },
561 .hw_rev = ATH11K_HW_QCA6390_HW20,
562 },
563 {
564 .total_vectors = 16,
565 .total_users = 3,
566 .users = (struct qwx_msi_user[]) {
567 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
568 { .name = "CE", .num_vectors = 5, .base_vector = 3 },
569 { .name = "DP", .num_vectors = 8, .base_vector = 8 },
570 },
571 .hw_rev = ATH11K_HW_QCN9074_HW10,
572 },
573 {
574 .total_vectors = 32,
575 .total_users = 4,
576 .users = (struct qwx_msi_user[]) {
577 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
578 { .name = "CE", .num_vectors = 10, .base_vector = 3 },
579 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
580 { .name = "DP", .num_vectors = 18, .base_vector = 14 },
581 },
582 .hw_rev = ATH11K_HW_WCN6855_HW20,
583 },
584 {
585 .total_vectors = 32,
586 .total_users = 4,
587 .users = (struct qwx_msi_user[]) {
588 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
589 { .name = "CE", .num_vectors = 10, .base_vector = 3 },
590 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
591 { .name = "DP", .num_vectors = 18, .base_vector = 14 },
592 },
593 .hw_rev = ATH11K_HW_WCN6855_HW21,
594 },
595 {
596 .total_vectors = 28,
597 .total_users = 2,
598 .users = (struct qwx_msi_user[]) {
599 { .name = "CE", .num_vectors = 10, .base_vector = 0 },
600 { .name = "DP", .num_vectors = 18, .base_vector = 10 },
601 },
602 .hw_rev = ATH11K_HW_WCN6750_HW10,
603 },
604 };
605
606 int
qwx_pcic_init_msi_config(struct qwx_softc * sc)607 qwx_pcic_init_msi_config(struct qwx_softc *sc)
608 {
609 const struct qwx_msi_config *msi_config;
610 int i;
611
612 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags)) {
613 sc->msi_cfg = &qwx_msi_config_one_msi;
614 return 0;
615 }
616 for (i = 0; i < nitems(qwx_msi_config); i++) {
617 msi_config = &qwx_msi_config[i];
618
619 if (msi_config->hw_rev == sc->sc_hw_rev)
620 break;
621 }
622
623 if (i == nitems(qwx_msi_config)) {
624 printf("%s: failed to fetch msi config, "
625 "unsupported hw version: 0x%x\n",
626 sc->sc_dev.dv_xname, sc->sc_hw_rev);
627 return EINVAL;
628 }
629
630 sc->msi_cfg = msi_config;
631 return 0;
632 }
633
634 int
qwx_pci_alloc_msi(struct qwx_softc * sc)635 qwx_pci_alloc_msi(struct qwx_softc *sc)
636 {
637 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
638 uint64_t addr;
639 pcireg_t data;
640
641 if (psc->sc_msi_cap & PCI_MSI_MC_C64) {
642 uint64_t addr_hi;
643 pcireg_t addr_lo;
644
645 addr_lo = pci_conf_read(psc->sc_pc, psc->sc_tag,
646 psc->sc_msi_off + PCI_MSI_MA);
647 addr_hi = pci_conf_read(psc->sc_pc, psc->sc_tag,
648 psc->sc_msi_off + PCI_MSI_MAU32);
649 addr = addr_hi << 32 | addr_lo;
650 data = pci_conf_read(psc->sc_pc, psc->sc_tag,
651 psc->sc_msi_off + PCI_MSI_MD64);
652 } else {
653 addr = pci_conf_read(psc->sc_pc, psc->sc_tag,
654 psc->sc_msi_off + PCI_MSI_MA);
655 data = pci_conf_read(psc->sc_pc, psc->sc_tag,
656 psc->sc_msi_off + PCI_MSI_MD32);
657 }
658
659 sc->msi_addr_lo = addr & 0xffffffff;
660 sc->msi_addr_hi = ((uint64_t)addr) >> 32;
661 sc->msi_data_start = data;
662
663 DPRINTF("%s: MSI addr: 0x%llx MSI data: 0x%x\n", sc->sc_dev.dv_xname,
664 addr, data);
665
666 return 0;
667 }
668
669 int
qwx_pcic_map_service_to_pipe(struct qwx_softc * sc,uint16_t service_id,uint8_t * ul_pipe,uint8_t * dl_pipe)670 qwx_pcic_map_service_to_pipe(struct qwx_softc *sc, uint16_t service_id,
671 uint8_t *ul_pipe, uint8_t *dl_pipe)
672 {
673 const struct service_to_pipe *entry;
674 int ul_set = 0, dl_set = 0;
675 int i;
676
677 for (i = 0; i < sc->hw_params.svc_to_ce_map_len; i++) {
678 entry = &sc->hw_params.svc_to_ce_map[i];
679
680 if (le32toh(entry->service_id) != service_id)
681 continue;
682
683 switch (le32toh(entry->pipedir)) {
684 case PIPEDIR_NONE:
685 break;
686 case PIPEDIR_IN:
687 *dl_pipe = le32toh(entry->pipenum);
688 dl_set = 1;
689 break;
690 case PIPEDIR_OUT:
691 *ul_pipe = le32toh(entry->pipenum);
692 ul_set = 1;
693 break;
694 case PIPEDIR_INOUT:
695 *dl_pipe = le32toh(entry->pipenum);
696 *ul_pipe = le32toh(entry->pipenum);
697 dl_set = 1;
698 ul_set = 1;
699 break;
700 }
701 }
702
703 if (!ul_set || !dl_set) {
704 DPRINTF("%s: found no uplink and no downlink\n", __func__);
705 return ENOENT;
706 }
707
708 return 0;
709 }
710
711 int
qwx_pcic_get_user_msi_vector(struct qwx_softc * sc,char * user_name,int * num_vectors,uint32_t * user_base_data,uint32_t * base_vector)712 qwx_pcic_get_user_msi_vector(struct qwx_softc *sc, char *user_name,
713 int *num_vectors, uint32_t *user_base_data, uint32_t *base_vector)
714 {
715 const struct qwx_msi_config *msi_config = sc->msi_cfg;
716 int idx;
717
718 for (idx = 0; idx < msi_config->total_users; idx++) {
719 if (strcmp(user_name, msi_config->users[idx].name) == 0) {
720 *num_vectors = msi_config->users[idx].num_vectors;
721 *base_vector = msi_config->users[idx].base_vector;
722 *user_base_data = *base_vector + sc->msi_data_start;
723
724 DPRINTF("%s: MSI assignment %s num_vectors %d "
725 "user_base_data %u base_vector %u\n", __func__,
726 user_name, *num_vectors, *user_base_data,
727 *base_vector);
728 return 0;
729 }
730 }
731
732 DPRINTF("%s: Failed to find MSI assignment for %s\n",
733 sc->sc_dev.dv_xname, user_name);
734
735 return EINVAL;
736 }
737
738 void
qwx_pci_attach(struct device * parent,struct device * self,void * aux)739 qwx_pci_attach(struct device *parent, struct device *self, void *aux)
740 {
741 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)self;
742 struct qwx_softc *sc = &psc->sc_sc;
743 struct ieee80211com *ic = &sc->sc_ic;
744 struct ifnet *ifp = &ic->ic_if;
745 uint32_t soc_hw_version_major, soc_hw_version_minor;
746 struct pci_attach_args *pa = aux;
747 pci_intr_handle_t ih;
748 pcireg_t memtype, reg;
749 const char *intrstr;
750 int error;
751 pcireg_t sreg;
752
753 sc->sc_dmat = pa->pa_dmat;
754 psc->sc_pc = pa->pa_pc;
755 psc->sc_tag = pa->pa_tag;
756
757 #ifdef __HAVE_FDT
758 sc->sc_node = PCITAG_NODE(pa->pa_tag);
759 #endif
760
761 rw_init(&sc->ioctl_rwl, "qwxioctl");
762
763 sreg = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_SUBSYS_ID_REG);
764 sc->id.bdf_search = ATH11K_BDF_SEARCH_DEFAULT;
765 sc->id.vendor = PCI_VENDOR(pa->pa_id);
766 sc->id.device = PCI_PRODUCT(pa->pa_id);
767 sc->id.subsystem_vendor = PCI_VENDOR(sreg);
768 sc->id.subsystem_device = PCI_PRODUCT(sreg);
769
770 strlcpy(sc->sc_bus_str, "pci", sizeof(sc->sc_bus_str));
771
772 sc->ops.read32 = qwx_pcic_read32;
773 sc->ops.write32 = qwx_pcic_write32;
774 sc->ops.start = qwx_pci_start;
775 sc->ops.stop = qwx_pci_stop;
776 sc->ops.power_up = qwx_pci_power_up;
777 sc->ops.power_down = qwx_pci_power_down;
778 sc->ops.submit_xfer = qwx_mhi_submit_xfer;
779 sc->ops.irq_enable = qwx_pcic_ext_irq_enable;
780 sc->ops.irq_disable = qwx_pcic_ext_irq_disable;
781 sc->ops.map_service_to_pipe = qwx_pcic_map_service_to_pipe;
782 sc->ops.get_user_msi_vector = qwx_pcic_get_user_msi_vector;
783
784 if (pci_get_capability(psc->sc_pc, psc->sc_tag, PCI_CAP_PCIEXPRESS,
785 &psc->sc_cap_off, NULL) == 0) {
786 printf(": can't find PCIe capability structure\n");
787 return;
788 }
789
790 if (pci_get_capability(psc->sc_pc, psc->sc_tag, PCI_CAP_MSI,
791 &psc->sc_msi_off, &psc->sc_msi_cap) == 0) {
792 printf(": can't find MSI capability structure\n");
793 return;
794 }
795
796 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
797 reg |= PCI_COMMAND_MASTER_ENABLE;
798 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);
799
800 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START);
801 if (pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0,
802 &psc->sc_st, &psc->sc_sh, &psc->sc_map, &psc->sc_mapsize, 0)) {
803 printf(": can't map mem space\n");
804 return;
805 }
806
807 sc->mem = psc->sc_map;
808
809 sc->num_msivec = 32;
810 if (pci_intr_enable_msivec(pa, sc->num_msivec) != 0) {
811 sc->num_msivec = 1;
812 if (pci_intr_map_msi(pa, &ih) != 0) {
813 printf(": can't map interrupt\n");
814 return;
815 }
816 clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags);
817 } else {
818 if (pci_intr_map_msivec(pa, 0, &ih) != 0 &&
819 pci_intr_map_msi(pa, &ih) != 0) {
820 printf(": can't map interrupt\n");
821 return;
822 }
823 set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags);
824 psc->mhi_irq[MHI_ER_CTRL] = 1;
825 psc->mhi_irq[MHI_ER_DATA] = 2;
826 }
827
828 intrstr = pci_intr_string(psc->sc_pc, ih);
829 snprintf(psc->sc_ivname[0], sizeof(psc->sc_ivname[0]), "%s:bhi",
830 sc->sc_dev.dv_xname);
831 psc->sc_ih[0] = pci_intr_establish(psc->sc_pc, ih, IPL_NET,
832 qwx_pci_intr, psc, psc->sc_ivname[0]);
833 if (psc->sc_ih[0] == NULL) {
834 printf(": can't establish interrupt");
835 if (intrstr != NULL)
836 printf(" at %s", intrstr);
837 printf("\n");
838 return;
839 }
840 printf(": %s\n", intrstr);
841
842 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags)) {
843 int msivec;
844
845 msivec = psc->mhi_irq[MHI_ER_CTRL];
846 if (pci_intr_map_msivec(pa, msivec, &ih) != 0 &&
847 pci_intr_map_msi(pa, &ih) != 0) {
848 printf(": can't map interrupt\n");
849 return;
850 }
851 snprintf(psc->sc_ivname[msivec],
852 sizeof(psc->sc_ivname[msivec]),
853 "%s:mhic", sc->sc_dev.dv_xname);
854 psc->sc_ih[msivec] = pci_intr_establish(psc->sc_pc, ih,
855 IPL_NET, qwx_pci_intr_mhi_ctrl, psc,
856 psc->sc_ivname[msivec]);
857 if (psc->sc_ih[msivec] == NULL) {
858 printf("%s: can't establish interrupt\n",
859 sc->sc_dev.dv_xname);
860 return;
861 }
862
863 msivec = psc->mhi_irq[MHI_ER_DATA];
864 if (pci_intr_map_msivec(pa, msivec, &ih) != 0 &&
865 pci_intr_map_msi(pa, &ih) != 0) {
866 printf(": can't map interrupt\n");
867 return;
868 }
869 snprintf(psc->sc_ivname[msivec],
870 sizeof(psc->sc_ivname[msivec]),
871 "%s:mhid", sc->sc_dev.dv_xname);
872 psc->sc_ih[msivec] = pci_intr_establish(psc->sc_pc, ih,
873 IPL_NET, qwx_pci_intr_mhi_data, psc,
874 psc->sc_ivname[msivec]);
875 if (psc->sc_ih[msivec] == NULL) {
876 printf("%s: can't establish interrupt\n",
877 sc->sc_dev.dv_xname);
878 return;
879 }
880 }
881
882 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
883
884 /* register PCI ops */
885 psc->sc_pci_ops = &qwx_pci_ops_qca6390;
886
887 switch (PCI_PRODUCT(pa->pa_id)) {
888 case PCI_PRODUCT_QUALCOMM_QCA6390:
889 qwx_pci_read_hw_version(sc, &soc_hw_version_major,
890 &soc_hw_version_minor);
891 switch (soc_hw_version_major) {
892 case 2:
893 sc->sc_hw_rev = ATH11K_HW_QCA6390_HW20;
894 break;
895 default:
896 printf(": unsupported QCA6390 SOC version: %d %d\n",
897 soc_hw_version_major, soc_hw_version_minor);
898 return;
899 }
900
901 psc->max_chan = QWX_MHI_CONFIG_QCA6390_MAX_CHANNELS;
902 break;
903 case PCI_PRODUCT_QUALCOMM_QCN9074:
904 psc->sc_pci_ops = &qwx_pci_ops_qcn9074;
905 sc->sc_hw_rev = ATH11K_HW_QCN9074_HW10;
906 psc->max_chan = QWX_MHI_CONFIG_QCA9074_MAX_CHANNELS;
907 break;
908 case PCI_PRODUCT_QUALCOMM_QCNFA765:
909 sc->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD;
910 qwx_pci_read_hw_version(sc, &soc_hw_version_major,
911 &soc_hw_version_minor);
912 switch (soc_hw_version_major) {
913 case 2:
914 switch (soc_hw_version_minor) {
915 case 0x00:
916 case 0x01:
917 sc->sc_hw_rev = ATH11K_HW_WCN6855_HW20;
918 break;
919 case 0x10:
920 case 0x11:
921 sc->sc_hw_rev = ATH11K_HW_WCN6855_HW21;
922 break;
923 default:
924 goto unsupported_wcn6855_soc;
925 }
926 break;
927 default:
928 unsupported_wcn6855_soc:
929 printf(": unsupported WCN6855 SOC version: %d %d\n",
930 soc_hw_version_major, soc_hw_version_minor);
931 return;
932 }
933
934 psc->max_chan = QWX_MHI_CONFIG_QCA6390_MAX_CHANNELS;
935 break;
936 default:
937 printf(": unsupported chip\n");
938 return;
939 }
940
941 error = qwx_pcic_init_msi_config(sc);
942 if (error)
943 goto err_pci_free_region;
944
945 error = qwx_pci_alloc_msi(sc);
946 if (error) {
947 printf("%s: failed to enable msi: %d\n", sc->sc_dev.dv_xname,
948 error);
949 goto err_pci_free_region;
950 }
951
952 error = qwx_init_hw_params(sc);
953 if (error)
954 goto err_pci_disable_msi;
955
956 psc->chan_ctxt = qwx_dmamem_alloc(sc->sc_dmat,
957 sizeof(struct qwx_mhi_chan_ctxt) * psc->max_chan, 0);
958 if (psc->chan_ctxt == NULL) {
959 printf("%s: could not allocate channel context array\n",
960 sc->sc_dev.dv_xname);
961 goto err_pci_disable_msi;
962 }
963
964 if (psc->sc_pci_ops->alloc_xfer_rings(psc)) {
965 printf("%s: could not allocate transfer rings\n",
966 sc->sc_dev.dv_xname);
967 goto err_pci_free_chan_ctxt;
968 }
969
970 psc->event_ctxt = qwx_dmamem_alloc(sc->sc_dmat,
971 sizeof(struct qwx_mhi_event_ctxt) * QWX_NUM_EVENT_CTX, 0);
972 if (psc->event_ctxt == NULL) {
973 printf("%s: could not allocate event context array\n",
974 sc->sc_dev.dv_xname);
975 goto err_pci_free_xfer_rings;
976 }
977
978 if (qwx_pci_alloc_event_rings(psc)) {
979 printf("%s: could not allocate event rings\n",
980 sc->sc_dev.dv_xname);
981 goto err_pci_free_event_ctxt;
982 }
983
984 psc->cmd_ctxt = qwx_dmamem_alloc(sc->sc_dmat,
985 sizeof(struct qwx_mhi_cmd_ctxt), 0);
986 if (psc->cmd_ctxt == NULL) {
987 printf("%s: could not allocate command context array\n",
988 sc->sc_dev.dv_xname);
989 goto err_pci_free_event_rings;
990 }
991
992 if (qwx_pci_init_cmd_ring(sc, &psc->cmd_ring)) {
993 printf("%s: could not allocate command ring\n",
994 sc->sc_dev.dv_xname);
995 goto err_pci_free_cmd_ctxt;
996 }
997
998 error = qwx_mhi_register(sc);
999 if (error) {
1000 printf(": failed to register mhi: %d\n", error);
1001 goto err_pci_free_cmd_ring;
1002 }
1003
1004 error = qwx_hal_srng_init(sc);
1005 if (error)
1006 goto err_mhi_unregister;
1007
1008 error = qwx_ce_alloc_pipes(sc);
1009 if (error) {
1010 printf(": failed to allocate ce pipes: %d\n", error);
1011 goto err_hal_srng_deinit;
1012 }
1013
1014 sc->sc_nswq = taskq_create("qwxns", 1, IPL_NET, 0);
1015 if (sc->sc_nswq == NULL)
1016 goto err_ce_free;
1017
1018 qwx_pci_init_qmi_ce_config(sc);
1019
1020 error = qwx_pcic_config_irq(sc, pa);
1021 if (error) {
1022 printf("%s: failed to config irq: %d\n",
1023 sc->sc_dev.dv_xname, error);
1024 goto err_ce_free;
1025 }
1026 #if notyet
1027 ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
1028 if (ret) {
1029 ath11k_err(ab, "failed to set irq affinity %d\n", ret);
1030 goto err_free_irq;
1031 }
1032
1033 /* kernel may allocate a dummy vector before request_irq and
1034 * then allocate a real vector when request_irq is called.
1035 * So get msi_data here again to avoid spurious interrupt
1036 * as msi_data will configured to srngs.
1037 */
1038 ret = ath11k_pci_config_msi_data(ab_pci);
1039 if (ret) {
1040 ath11k_err(ab, "failed to config msi_data: %d\n", ret);
1041 goto err_irq_affinity_cleanup;
1042 }
1043 #endif
1044 #ifdef QWX_DEBUG
1045 task_set(&psc->rddm_task, qwx_rddm_task, psc);
1046 #endif
1047 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
1048 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
1049 ic->ic_state = IEEE80211_S_INIT;
1050
1051 /* Set device capabilities. */
1052 ic->ic_caps =
1053 #if 0
1054 IEEE80211_C_QOS | IEEE80211_C_TX_AMPDU | /* A-MPDU */
1055 #endif
1056 IEEE80211_C_ADDBA_OFFLOAD | /* device sends ADDBA/DELBA frames */
1057 IEEE80211_C_WEP | /* WEP */
1058 IEEE80211_C_RSN | /* WPA/RSN */
1059 IEEE80211_C_SCANALL | /* device scans all channels at once */
1060 IEEE80211_C_SCANALLBAND | /* device scans all bands at once */
1061 #if 0
1062 IEEE80211_C_MONITOR | /* monitor mode supported */
1063 #endif
1064 IEEE80211_C_SHSLOT | /* short slot time supported */
1065 IEEE80211_C_SHPREAMBLE; /* short preamble supported */
1066
1067 ic->ic_sup_rates[IEEE80211_MODE_11A] = ieee80211_std_rateset_11a;
1068 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b;
1069 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g;
1070
1071 /* IBSS channel undefined for now. */
1072 ic->ic_ibss_chan = &ic->ic_channels[1];
1073
1074 ifp->if_softc = sc;
1075 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1076 ifp->if_ioctl = qwx_ioctl;
1077 ifp->if_start = qwx_start;
1078 ifp->if_watchdog = qwx_watchdog;
1079 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
1080 if_attach(ifp);
1081 ieee80211_ifattach(ifp);
1082 ieee80211_media_init(ifp, qwx_media_change, ieee80211_media_status);
1083
1084 ic->ic_node_alloc = qwx_node_alloc;
1085
1086 /* Override 802.11 state transition machine. */
1087 sc->sc_newstate = ic->ic_newstate;
1088 ic->ic_newstate = qwx_newstate;
1089 ic->ic_set_key = qwx_set_key;
1090 ic->ic_delete_key = qwx_delete_key;
1091 #if 0
1092 ic->ic_updatechan = qwx_updatechan;
1093 ic->ic_updateprot = qwx_updateprot;
1094 ic->ic_updateslot = qwx_updateslot;
1095 ic->ic_updateedca = qwx_updateedca;
1096 ic->ic_updatedtim = qwx_updatedtim;
1097 #endif
1098 /*
1099 * We cannot read the MAC address without loading the
1100 * firmware from disk. Postpone until mountroot is done.
1101 */
1102 config_mountroot(self, qwx_pci_attach_hook);
1103 return;
1104
1105 err_ce_free:
1106 qwx_ce_free_pipes(sc);
1107 err_hal_srng_deinit:
1108 err_mhi_unregister:
1109 err_pci_free_cmd_ring:
1110 qwx_pci_free_cmd_ring(psc);
1111 err_pci_free_cmd_ctxt:
1112 qwx_dmamem_free(sc->sc_dmat, psc->cmd_ctxt);
1113 psc->cmd_ctxt = NULL;
1114 err_pci_free_event_rings:
1115 qwx_pci_free_event_rings(psc);
1116 err_pci_free_event_ctxt:
1117 qwx_dmamem_free(sc->sc_dmat, psc->event_ctxt);
1118 psc->event_ctxt = NULL;
1119 err_pci_free_xfer_rings:
1120 qwx_pci_free_xfer_rings(psc);
1121 err_pci_free_chan_ctxt:
1122 qwx_dmamem_free(sc->sc_dmat, psc->chan_ctxt);
1123 psc->chan_ctxt = NULL;
1124 err_pci_disable_msi:
1125 err_pci_free_region:
1126 pci_intr_disestablish(psc->sc_pc, psc->sc_ih[0]);
1127 return;
1128 }
1129
1130 int
qwx_pci_detach(struct device * self,int flags)1131 qwx_pci_detach(struct device *self, int flags)
1132 {
1133 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)self;
1134 struct qwx_softc *sc = &psc->sc_sc;
1135
1136 if (psc->sc_ih[0]) {
1137 pci_intr_disestablish(psc->sc_pc, psc->sc_ih[0]);
1138 psc->sc_ih[0] = NULL;
1139 }
1140
1141 qwx_detach(sc);
1142
1143 qwx_pci_free_event_rings(psc);
1144 qwx_pci_free_xfer_rings(psc);
1145 qwx_pci_free_cmd_ring(psc);
1146
1147 if (psc->event_ctxt) {
1148 qwx_dmamem_free(sc->sc_dmat, psc->event_ctxt);
1149 psc->event_ctxt = NULL;
1150 }
1151 if (psc->chan_ctxt) {
1152 qwx_dmamem_free(sc->sc_dmat, psc->chan_ctxt);
1153 psc->chan_ctxt = NULL;
1154 }
1155 if (psc->cmd_ctxt) {
1156 qwx_dmamem_free(sc->sc_dmat, psc->cmd_ctxt);
1157 psc->cmd_ctxt = NULL;
1158 }
1159
1160 if (psc->amss_data) {
1161 qwx_dmamem_free(sc->sc_dmat, psc->amss_data);
1162 psc->amss_data = NULL;
1163 }
1164 if (psc->amss_vec) {
1165 qwx_dmamem_free(sc->sc_dmat, psc->amss_vec);
1166 psc->amss_vec = NULL;
1167 }
1168
1169 return 0;
1170 }
1171
1172 void
qwx_pci_attach_hook(struct device * self)1173 qwx_pci_attach_hook(struct device *self)
1174 {
1175 struct qwx_softc *sc = (void *)self;
1176 int s = splnet();
1177
1178 qwx_attach(sc);
1179
1180 splx(s);
1181 }
1182
1183 void
qwx_pci_free_xfer_rings(struct qwx_pci_softc * psc)1184 qwx_pci_free_xfer_rings(struct qwx_pci_softc *psc)
1185 {
1186 struct qwx_softc *sc = &psc->sc_sc;
1187 int i;
1188
1189 for (i = 0; i < nitems(psc->xfer_rings); i++) {
1190 struct qwx_pci_xfer_ring *ring = &psc->xfer_rings[i];
1191 if (ring->dmamem) {
1192 qwx_dmamem_free(sc->sc_dmat, ring->dmamem);
1193 ring->dmamem = NULL;
1194 }
1195 memset(ring, 0, sizeof(*ring));
1196 }
1197 }
1198
1199 int
qwx_pci_alloc_xfer_ring(struct qwx_softc * sc,struct qwx_pci_xfer_ring * ring,uint32_t id,uint32_t direction,uint32_t event_ring_index,size_t num_elements)1200 qwx_pci_alloc_xfer_ring(struct qwx_softc *sc, struct qwx_pci_xfer_ring *ring,
1201 uint32_t id, uint32_t direction, uint32_t event_ring_index,
1202 size_t num_elements)
1203 {
1204 bus_size_t size;
1205 int i, err;
1206
1207 memset(ring, 0, sizeof(*ring));
1208
1209 size = sizeof(struct qwx_mhi_ring_element) * num_elements;
1210 /* Hardware requires that rings are aligned to ring size. */
1211 ring->dmamem = qwx_dmamem_alloc(sc->sc_dmat, size, size);
1212 if (ring->dmamem == NULL)
1213 return ENOMEM;
1214
1215 ring->size = size;
1216 ring->mhi_chan_id = id;
1217 ring->mhi_chan_state = MHI_CH_STATE_DISABLED;
1218 ring->mhi_chan_direction = direction;
1219 ring->mhi_chan_event_ring_index = event_ring_index;
1220 ring->num_elements = num_elements;
1221
1222 memset(ring->data, 0, sizeof(ring->data));
1223 for (i = 0; i < ring->num_elements; i++) {
1224 struct qwx_xfer_data *xfer = &ring->data[i];
1225
1226 err = bus_dmamap_create(sc->sc_dmat, QWX_PCI_XFER_MAX_DATA_SIZE,
1227 1, QWX_PCI_XFER_MAX_DATA_SIZE, 0, BUS_DMA_NOWAIT,
1228 &xfer->map);
1229 if (err) {
1230 printf("%s: could not create xfer DMA map\n",
1231 sc->sc_dev.dv_xname);
1232 goto fail;
1233 }
1234
1235 if (direction == MHI_CHAN_TYPE_INBOUND) {
1236 struct mbuf *m;
1237
1238 m = m_gethdr(M_DONTWAIT, MT_DATA);
1239 if (m == NULL) {
1240 err = ENOBUFS;
1241 goto fail;
1242 }
1243
1244 MCLGETL(m, M_DONTWAIT, QWX_PCI_XFER_MAX_DATA_SIZE);
1245 if ((m->m_flags & M_EXT) == 0) {
1246 m_freem(m);
1247 err = ENOBUFS;
1248 goto fail;
1249 }
1250
1251 m->m_len = m->m_pkthdr.len = QWX_PCI_XFER_MAX_DATA_SIZE;
1252 err = bus_dmamap_load_mbuf(sc->sc_dmat, xfer->map,
1253 m, BUS_DMA_READ | BUS_DMA_NOWAIT);
1254 if (err) {
1255 printf("%s: can't map mbuf (error %d)\n",
1256 sc->sc_dev.dv_xname, err);
1257 m_freem(m);
1258 goto fail;
1259 }
1260
1261 bus_dmamap_sync(sc->sc_dmat, xfer->map, 0,
1262 QWX_PCI_XFER_MAX_DATA_SIZE, BUS_DMASYNC_PREREAD);
1263 xfer->m = m;
1264 }
1265 }
1266
1267 return 0;
1268 fail:
1269 for (i = 0; i < ring->num_elements; i++) {
1270 struct qwx_xfer_data *xfer = &ring->data[i];
1271
1272 if (xfer->map) {
1273 bus_dmamap_sync(sc->sc_dmat, xfer->map, 0,
1274 xfer->map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1275 bus_dmamap_unload(sc->sc_dmat, xfer->map);
1276 bus_dmamap_destroy(sc->sc_dmat, xfer->map);
1277 xfer->map = NULL;
1278 }
1279
1280 if (xfer->m) {
1281 m_freem(xfer->m);
1282 xfer->m = NULL;
1283 }
1284 }
1285 return 1;
1286 }
1287
1288 int
qwx_pci_alloc_xfer_rings_qca6390(struct qwx_pci_softc * psc)1289 qwx_pci_alloc_xfer_rings_qca6390(struct qwx_pci_softc *psc)
1290 {
1291 struct qwx_softc *sc = &psc->sc_sc;
1292 int ret;
1293
1294 ret = qwx_pci_alloc_xfer_ring(sc,
1295 &psc->xfer_rings[QWX_PCI_XFER_RING_IPCR_OUTBOUND],
1296 20, MHI_CHAN_TYPE_OUTBOUND, 1, 64);
1297 if (ret)
1298 goto fail;
1299
1300 ret = qwx_pci_alloc_xfer_ring(sc,
1301 &psc->xfer_rings[QWX_PCI_XFER_RING_IPCR_INBOUND],
1302 21, MHI_CHAN_TYPE_INBOUND, 1, 64);
1303 if (ret)
1304 goto fail;
1305
1306 return 0;
1307 fail:
1308 qwx_pci_free_xfer_rings(psc);
1309 return ret;
1310 }
1311
1312 int
qwx_pci_alloc_xfer_rings_qcn9074(struct qwx_pci_softc * psc)1313 qwx_pci_alloc_xfer_rings_qcn9074(struct qwx_pci_softc *psc)
1314 {
1315 struct qwx_softc *sc = &psc->sc_sc;
1316 int ret;
1317
1318 ret = qwx_pci_alloc_xfer_ring(sc,
1319 &psc->xfer_rings[QWX_PCI_XFER_RING_IPCR_OUTBOUND],
1320 20, MHI_CHAN_TYPE_OUTBOUND, 1, 32);
1321 if (ret)
1322 goto fail;
1323
1324 ret = qwx_pci_alloc_xfer_ring(sc,
1325 &psc->xfer_rings[QWX_PCI_XFER_RING_IPCR_INBOUND],
1326 21, MHI_CHAN_TYPE_INBOUND, 1, 32);
1327 if (ret)
1328 goto fail;
1329
1330 return 0;
1331 fail:
1332 qwx_pci_free_xfer_rings(psc);
1333 return ret;
1334 }
1335
1336 void
qwx_pci_free_event_rings(struct qwx_pci_softc * psc)1337 qwx_pci_free_event_rings(struct qwx_pci_softc *psc)
1338 {
1339 struct qwx_softc *sc = &psc->sc_sc;
1340 int i;
1341
1342 for (i = 0; i < nitems(psc->event_rings); i++) {
1343 struct qwx_pci_event_ring *ring = &psc->event_rings[i];
1344 if (ring->dmamem) {
1345 qwx_dmamem_free(sc->sc_dmat, ring->dmamem);
1346 ring->dmamem = NULL;
1347 }
1348 memset(ring, 0, sizeof(*ring));
1349 }
1350 }
1351
1352 int
qwx_pci_alloc_event_ring(struct qwx_softc * sc,struct qwx_pci_event_ring * ring,uint32_t type,uint32_t irq,uint32_t intmod,size_t num_elements)1353 qwx_pci_alloc_event_ring(struct qwx_softc *sc, struct qwx_pci_event_ring *ring,
1354 uint32_t type, uint32_t irq, uint32_t intmod, size_t num_elements)
1355 {
1356 bus_size_t size;
1357
1358 memset(ring, 0, sizeof(*ring));
1359
1360 size = sizeof(struct qwx_mhi_ring_element) * num_elements;
1361 /* Hardware requires that rings are aligned to ring size. */
1362 ring->dmamem = qwx_dmamem_alloc(sc->sc_dmat, size, size);
1363 if (ring->dmamem == NULL)
1364 return ENOMEM;
1365
1366 ring->size = size;
1367 ring->mhi_er_type = type;
1368 ring->mhi_er_irq = irq;
1369 ring->mhi_er_irq_moderation_ms = intmod;
1370 ring->num_elements = num_elements;
1371 return 0;
1372 }
1373
1374 int
qwx_pci_alloc_event_rings(struct qwx_pci_softc * psc)1375 qwx_pci_alloc_event_rings(struct qwx_pci_softc *psc)
1376 {
1377 struct qwx_softc *sc = &psc->sc_sc;
1378 int ret;
1379
1380 ret = qwx_pci_alloc_event_ring(sc, &psc->event_rings[0],
1381 MHI_ER_CTRL, psc->mhi_irq[MHI_ER_CTRL], 0, 32);
1382 if (ret)
1383 goto fail;
1384
1385 ret = qwx_pci_alloc_event_ring(sc, &psc->event_rings[1],
1386 MHI_ER_DATA, psc->mhi_irq[MHI_ER_DATA], 1, 256);
1387 if (ret)
1388 goto fail;
1389
1390 return 0;
1391 fail:
1392 qwx_pci_free_event_rings(psc);
1393 return ret;
1394 }
1395
1396 void
qwx_pci_free_cmd_ring(struct qwx_pci_softc * psc)1397 qwx_pci_free_cmd_ring(struct qwx_pci_softc *psc)
1398 {
1399 struct qwx_softc *sc = &psc->sc_sc;
1400 struct qwx_pci_cmd_ring *ring = &psc->cmd_ring;
1401
1402 if (ring->dmamem)
1403 qwx_dmamem_free(sc->sc_dmat, ring->dmamem);
1404
1405 memset(ring, 0, sizeof(*ring));
1406 }
1407
1408 int
qwx_pci_init_cmd_ring(struct qwx_softc * sc,struct qwx_pci_cmd_ring * ring)1409 qwx_pci_init_cmd_ring(struct qwx_softc *sc, struct qwx_pci_cmd_ring *ring)
1410 {
1411 memset(ring, 0, sizeof(*ring));
1412
1413 ring->num_elements = QWX_PCI_CMD_RING_MAX_ELEMENTS;
1414 ring->size = sizeof(struct qwx_mhi_ring_element) * ring->num_elements;
1415
1416 /* Hardware requires that rings are aligned to ring size. */
1417 ring->dmamem = qwx_dmamem_alloc(sc->sc_dmat, ring->size, ring->size);
1418 if (ring->dmamem == NULL)
1419 return ENOMEM;
1420
1421 return 0;
1422 }
1423
1424 uint32_t
qwx_pci_read(struct qwx_softc * sc,uint32_t addr)1425 qwx_pci_read(struct qwx_softc *sc, uint32_t addr)
1426 {
1427 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
1428
1429 return (bus_space_read_4(psc->sc_st, psc->sc_sh, addr));
1430 }
1431
1432 void
qwx_pci_write(struct qwx_softc * sc,uint32_t addr,uint32_t val)1433 qwx_pci_write(struct qwx_softc *sc, uint32_t addr, uint32_t val)
1434 {
1435 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
1436
1437 bus_space_write_4(psc->sc_st, psc->sc_sh, addr, val);
1438 }
1439
1440 void
qwx_pci_read_hw_version(struct qwx_softc * sc,uint32_t * major,uint32_t * minor)1441 qwx_pci_read_hw_version(struct qwx_softc *sc, uint32_t *major,
1442 uint32_t *minor)
1443 {
1444 uint32_t soc_hw_version;
1445
1446 soc_hw_version = qwx_pcic_read32(sc, TCSR_SOC_HW_VERSION);
1447 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, soc_hw_version);
1448 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, soc_hw_version);
1449 DPRINTF("%s: pci tcsr_soc_hw_version major %d minor %d\n",
1450 sc->sc_dev.dv_xname, *major, *minor);
1451 }
1452
1453 uint32_t
qwx_pcic_read32(struct qwx_softc * sc,uint32_t offset)1454 qwx_pcic_read32(struct qwx_softc *sc, uint32_t offset)
1455 {
1456 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
1457 int ret = 0;
1458 uint32_t val;
1459 bool wakeup_required;
1460
1461 /* for offset beyond BAR + 4K - 32, may
1462 * need to wakeup the device to access.
1463 */
1464 wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, sc->sc_flags)
1465 && offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF;
1466 if (wakeup_required && psc->sc_pci_ops->wakeup)
1467 ret = psc->sc_pci_ops->wakeup(sc);
1468
1469 if (offset < ATH11K_PCI_WINDOW_START)
1470 val = qwx_pci_read(sc, offset);
1471 else
1472 val = psc->sc_pci_ops->window_read32(sc, offset);
1473
1474 if (wakeup_required && !ret && psc->sc_pci_ops->release)
1475 psc->sc_pci_ops->release(sc);
1476
1477 return val;
1478 }
1479
1480 void
qwx_pcic_write32(struct qwx_softc * sc,uint32_t offset,uint32_t value)1481 qwx_pcic_write32(struct qwx_softc *sc, uint32_t offset, uint32_t value)
1482 {
1483 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
1484 int ret = 0;
1485 bool wakeup_required;
1486
1487 /* for offset beyond BAR + 4K - 32, may
1488 * need to wakeup the device to access.
1489 */
1490 wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, sc->sc_flags)
1491 && offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF;
1492 if (wakeup_required && psc->sc_pci_ops->wakeup)
1493 ret = psc->sc_pci_ops->wakeup(sc);
1494
1495 if (offset < ATH11K_PCI_WINDOW_START)
1496 qwx_pci_write(sc, offset, value);
1497 else
1498 psc->sc_pci_ops->window_write32(sc, offset, value);
1499
1500 if (wakeup_required && !ret && psc->sc_pci_ops->release)
1501 psc->sc_pci_ops->release(sc);
1502 }
1503
1504 void
qwx_pcic_ext_irq_disable(struct qwx_softc * sc)1505 qwx_pcic_ext_irq_disable(struct qwx_softc *sc)
1506 {
1507 clear_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, sc->sc_flags);
1508
1509 /* In case of one MSI vector, we handle irq enable/disable in a
1510 * uniform way since we only have one irq
1511 */
1512 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1513 return;
1514
1515 DPRINTF("%s not implemented\n", __func__);
1516 }
1517
1518 void
qwx_pcic_ext_irq_enable(struct qwx_softc * sc)1519 qwx_pcic_ext_irq_enable(struct qwx_softc *sc)
1520 {
1521 set_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, sc->sc_flags);
1522
1523 /* In case of one MSI vector, we handle irq enable/disable in a
1524 * uniform way since we only have one irq
1525 */
1526 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1527 return;
1528
1529 DPRINTF("%s not implemented\n", __func__);
1530 }
1531
1532 void
qwx_pcic_ce_irq_enable(struct qwx_softc * sc,uint16_t ce_id)1533 qwx_pcic_ce_irq_enable(struct qwx_softc *sc, uint16_t ce_id)
1534 {
1535 /* In case of one MSI vector, we handle irq enable/disable in a
1536 * uniform way since we only have one irq
1537 */
1538 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1539 return;
1540
1541 /* OpenBSD PCI stack does not yet implement MSI interrupt masking. */
1542 sc->msi_ce_irqmask |= (1U << ce_id);
1543 }
1544
1545 void
qwx_pcic_ce_irq_disable(struct qwx_softc * sc,uint16_t ce_id)1546 qwx_pcic_ce_irq_disable(struct qwx_softc *sc, uint16_t ce_id)
1547 {
1548 /* In case of one MSI vector, we handle irq enable/disable in a
1549 * uniform way since we only have one irq
1550 */
1551 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1552 return;
1553
1554 /* OpenBSD PCI stack does not yet implement MSI interrupt masking. */
1555 sc->msi_ce_irqmask &= ~(1U << ce_id);
1556 }
1557
1558 void
qwx_pcic_ext_grp_disable(struct qwx_ext_irq_grp * irq_grp)1559 qwx_pcic_ext_grp_disable(struct qwx_ext_irq_grp *irq_grp)
1560 {
1561 struct qwx_softc *sc = irq_grp->sc;
1562
1563 /* In case of one MSI vector, we handle irq enable/disable
1564 * in a uniform way since we only have one irq
1565 */
1566 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1567 return;
1568 }
1569
1570 int
qwx_pcic_ext_irq_config(struct qwx_softc * sc,struct pci_attach_args * pa)1571 qwx_pcic_ext_irq_config(struct qwx_softc *sc, struct pci_attach_args *pa)
1572 {
1573 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
1574 int i, ret, num_vectors = 0;
1575 uint32_t msi_data_start = 0;
1576 uint32_t base_vector = 0;
1577
1578 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1579 return 0;
1580
1581 ret = qwx_pcic_get_user_msi_vector(sc, "DP", &num_vectors,
1582 &msi_data_start, &base_vector);
1583 if (ret < 0)
1584 return ret;
1585
1586 for (i = 0; i < nitems(sc->ext_irq_grp); i++) {
1587 struct qwx_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i];
1588 uint32_t num_irq = 0;
1589
1590 irq_grp->sc = sc;
1591 irq_grp->grp_id = i;
1592 #if 0
1593 init_dummy_netdev(&irq_grp->napi_ndev);
1594 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
1595 ath11k_pcic_ext_grp_napi_poll);
1596 #endif
1597 if (sc->hw_params.ring_mask->tx[i] ||
1598 sc->hw_params.ring_mask->rx[i] ||
1599 sc->hw_params.ring_mask->rx_err[i] ||
1600 sc->hw_params.ring_mask->rx_wbm_rel[i] ||
1601 sc->hw_params.ring_mask->reo_status[i] ||
1602 sc->hw_params.ring_mask->rxdma2host[i] ||
1603 sc->hw_params.ring_mask->host2rxdma[i] ||
1604 sc->hw_params.ring_mask->rx_mon_status[i]) {
1605 num_irq = 1;
1606 }
1607
1608 irq_grp->num_irq = num_irq;
1609 irq_grp->irqs[0] = ATH11K_PCI_IRQ_DP_OFFSET + i;
1610
1611 if (num_irq) {
1612 int irq_idx = irq_grp->irqs[0];
1613 pci_intr_handle_t ih;
1614
1615 if (pci_intr_map_msivec(pa, irq_idx, &ih) != 0 &&
1616 pci_intr_map(pa, &ih) != 0) {
1617 printf("%s: can't map interrupt\n",
1618 sc->sc_dev.dv_xname);
1619 return EIO;
1620 }
1621
1622 snprintf(psc->sc_ivname[irq_idx], sizeof(psc->sc_ivname[0]),
1623 "%s:ex%d", sc->sc_dev.dv_xname, i);
1624 psc->sc_ih[irq_idx] = pci_intr_establish(psc->sc_pc, ih,
1625 IPL_NET, qwx_ext_intr, irq_grp, psc->sc_ivname[irq_idx]);
1626 if (psc->sc_ih[irq_idx] == NULL) {
1627 printf("%s: failed to request irq %d\n",
1628 sc->sc_dev.dv_xname, irq_idx);
1629 return EIO;
1630 }
1631 }
1632
1633 qwx_pcic_ext_grp_disable(irq_grp);
1634 }
1635
1636 return 0;
1637 }
1638
1639 int
qwx_pcic_config_irq(struct qwx_softc * sc,struct pci_attach_args * pa)1640 qwx_pcic_config_irq(struct qwx_softc *sc, struct pci_attach_args *pa)
1641 {
1642 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
1643 struct qwx_ce_pipe *ce_pipe;
1644 uint32_t msi_data_start;
1645 uint32_t msi_data_count, msi_data_idx;
1646 uint32_t msi_irq_start;
1647 int i, ret, irq_idx;
1648 pci_intr_handle_t ih;
1649
1650 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1651 return 0;
1652
1653 ret = qwx_pcic_get_user_msi_vector(sc, "CE", &msi_data_count,
1654 &msi_data_start, &msi_irq_start);
1655 if (ret)
1656 return ret;
1657
1658 /* Configure CE irqs */
1659 for (i = 0, msi_data_idx = 0; i < sc->hw_params.ce_count; i++) {
1660 if (qwx_ce_get_attr_flags(sc, i) & CE_ATTR_DIS_INTR)
1661 continue;
1662
1663 ce_pipe = &sc->ce.ce_pipe[i];
1664 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
1665
1666 if (pci_intr_map_msivec(pa, irq_idx, &ih) != 0 &&
1667 pci_intr_map(pa, &ih) != 0) {
1668 printf("%s: can't map interrupt\n",
1669 sc->sc_dev.dv_xname);
1670 return EIO;
1671 }
1672
1673 snprintf(psc->sc_ivname[irq_idx], sizeof(psc->sc_ivname[0]),
1674 "%s:ce%d", sc->sc_dev.dv_xname, ce_pipe->pipe_num);
1675 psc->sc_ih[irq_idx] = pci_intr_establish(psc->sc_pc, ih,
1676 IPL_NET, qwx_ce_intr, ce_pipe, psc->sc_ivname[irq_idx]);
1677 if (psc->sc_ih[irq_idx] == NULL) {
1678 printf("%s: failed to request irq %d\n",
1679 sc->sc_dev.dv_xname, irq_idx);
1680 return EIO;
1681 }
1682
1683 msi_data_idx++;
1684
1685 qwx_pcic_ce_irq_disable(sc, i);
1686 }
1687
1688 ret = qwx_pcic_ext_irq_config(sc, pa);
1689 if (ret)
1690 return ret;
1691
1692 return 0;
1693 }
1694
1695 void
qwx_pcic_ce_irqs_enable(struct qwx_softc * sc)1696 qwx_pcic_ce_irqs_enable(struct qwx_softc *sc)
1697 {
1698 int i;
1699
1700 set_bit(ATH11K_FLAG_CE_IRQ_ENABLED, sc->sc_flags);
1701
1702 for (i = 0; i < sc->hw_params.ce_count; i++) {
1703 if (qwx_ce_get_attr_flags(sc, i) & CE_ATTR_DIS_INTR)
1704 continue;
1705 qwx_pcic_ce_irq_enable(sc, i);
1706 }
1707 }
1708
1709 void
qwx_pcic_ce_irqs_disable(struct qwx_softc * sc)1710 qwx_pcic_ce_irqs_disable(struct qwx_softc *sc)
1711 {
1712 int i;
1713
1714 clear_bit(ATH11K_FLAG_CE_IRQ_ENABLED, sc->sc_flags);
1715
1716 for (i = 0; i < sc->hw_params.ce_count; i++) {
1717 if (qwx_ce_get_attr_flags(sc, i) & CE_ATTR_DIS_INTR)
1718 continue;
1719 qwx_pcic_ce_irq_disable(sc, i);
1720 }
1721 }
1722
1723 int
qwx_pci_start(struct qwx_softc * sc)1724 qwx_pci_start(struct qwx_softc *sc)
1725 {
1726 /* TODO: for now don't restore ASPM in case of single MSI
1727 * vector as MHI register reading in M2 causes system hang.
1728 */
1729 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
1730 qwx_pci_aspm_restore(sc);
1731 else
1732 DPRINTF("%s: leaving PCI ASPM disabled to avoid MHI M2 problems"
1733 "\n", sc->sc_dev.dv_xname);
1734
1735 set_bit(ATH11K_FLAG_DEVICE_INIT_DONE, sc->sc_flags);
1736
1737 qwx_ce_rx_post_buf(sc);
1738 qwx_pcic_ce_irqs_enable(sc);
1739
1740 return 0;
1741 }
1742
1743 void
qwx_pcic_ce_irq_disable_sync(struct qwx_softc * sc)1744 qwx_pcic_ce_irq_disable_sync(struct qwx_softc *sc)
1745 {
1746 qwx_pcic_ce_irqs_disable(sc);
1747 #if 0
1748 ath11k_pcic_sync_ce_irqs(ab);
1749 ath11k_pcic_kill_tasklets(ab);
1750 #endif
1751 }
1752
1753 void
qwx_pci_stop(struct qwx_softc * sc)1754 qwx_pci_stop(struct qwx_softc *sc)
1755 {
1756 qwx_pcic_ce_irq_disable_sync(sc);
1757 qwx_ce_cleanup_pipes(sc);
1758 }
1759
1760 int
qwx_pci_bus_wake_up(struct qwx_softc * sc)1761 qwx_pci_bus_wake_up(struct qwx_softc *sc)
1762 {
1763 if (qwx_mhi_wake_db_clear_valid(sc))
1764 qwx_mhi_device_wake(sc);
1765
1766 return 0;
1767 }
1768
1769 void
qwx_pci_bus_release(struct qwx_softc * sc)1770 qwx_pci_bus_release(struct qwx_softc *sc)
1771 {
1772 if (qwx_mhi_wake_db_clear_valid(sc))
1773 qwx_mhi_device_zzz(sc);
1774 }
1775
1776 uint32_t
qwx_pci_get_window_start(struct qwx_softc * sc,uint32_t offset)1777 qwx_pci_get_window_start(struct qwx_softc *sc, uint32_t offset)
1778 {
1779 if (!sc->hw_params.static_window_map)
1780 return ATH11K_PCI_WINDOW_START;
1781
1782 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
1783 /* if offset lies within DP register range, use 3rd window */
1784 return 3 * ATH11K_PCI_WINDOW_START;
1785 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc)) <
1786 ATH11K_PCI_WINDOW_RANGE_MASK)
1787 /* if offset lies within CE register range, use 2nd window */
1788 return 2 * ATH11K_PCI_WINDOW_START;
1789 else
1790 return ATH11K_PCI_WINDOW_START;
1791 }
1792
1793 void
qwx_pci_select_window(struct qwx_softc * sc,uint32_t offset)1794 qwx_pci_select_window(struct qwx_softc *sc, uint32_t offset)
1795 {
1796 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
1797 uint32_t window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
1798
1799 #if notyet
1800 lockdep_assert_held(&ab_pci->window_lock);
1801 #endif
1802
1803 if (window != psc->register_window) {
1804 qwx_pci_write(sc, ATH11K_PCI_WINDOW_REG_ADDRESS,
1805 ATH11K_PCI_WINDOW_ENABLE_BIT | window);
1806 (void) qwx_pci_read(sc, ATH11K_PCI_WINDOW_REG_ADDRESS);
1807 psc->register_window = window;
1808 }
1809 }
1810
1811 void
qwx_pci_window_write32(struct qwx_softc * sc,uint32_t offset,uint32_t value)1812 qwx_pci_window_write32(struct qwx_softc *sc, uint32_t offset, uint32_t value)
1813 {
1814 uint32_t window_start;
1815
1816 window_start = qwx_pci_get_window_start(sc, offset);
1817
1818 if (window_start == ATH11K_PCI_WINDOW_START) {
1819 #if notyet
1820 spin_lock_bh(&ab_pci->window_lock);
1821 #endif
1822 qwx_pci_select_window(sc, offset);
1823 qwx_pci_write(sc, window_start +
1824 (offset & ATH11K_PCI_WINDOW_RANGE_MASK), value);
1825 #if notyet
1826 spin_unlock_bh(&ab_pci->window_lock);
1827 #endif
1828 } else {
1829 qwx_pci_write(sc, window_start +
1830 (offset & ATH11K_PCI_WINDOW_RANGE_MASK), value);
1831 }
1832 }
1833
1834 uint32_t
qwx_pci_window_read32(struct qwx_softc * sc,uint32_t offset)1835 qwx_pci_window_read32(struct qwx_softc *sc, uint32_t offset)
1836 {
1837 uint32_t window_start, val;
1838
1839 window_start = qwx_pci_get_window_start(sc, offset);
1840
1841 if (window_start == ATH11K_PCI_WINDOW_START) {
1842 #if notyet
1843 spin_lock_bh(&ab_pci->window_lock);
1844 #endif
1845 qwx_pci_select_window(sc, offset);
1846 val = qwx_pci_read(sc, window_start +
1847 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
1848 #if notyet
1849 spin_unlock_bh(&ab_pci->window_lock);
1850 #endif
1851 } else {
1852 val = qwx_pci_read(sc, window_start +
1853 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
1854 }
1855
1856 return val;
1857 }
1858
1859 void
qwx_pci_select_static_window(struct qwx_softc * sc)1860 qwx_pci_select_static_window(struct qwx_softc *sc)
1861 {
1862 uint32_t umac_window;
1863 uint32_t ce_window;
1864 uint32_t window;
1865
1866 umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
1867 ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
1868 window = (umac_window << 12) | (ce_window << 6);
1869
1870 qwx_pci_write(sc, ATH11K_PCI_WINDOW_REG_ADDRESS,
1871 ATH11K_PCI_WINDOW_ENABLE_BIT | window);
1872 }
1873
1874 void
qwx_pci_soc_global_reset(struct qwx_softc * sc)1875 qwx_pci_soc_global_reset(struct qwx_softc *sc)
1876 {
1877 uint32_t val, msecs;
1878
1879 val = qwx_pcic_read32(sc, PCIE_SOC_GLOBAL_RESET);
1880
1881 val |= PCIE_SOC_GLOBAL_RESET_V;
1882
1883 qwx_pcic_write32(sc, PCIE_SOC_GLOBAL_RESET, val);
1884
1885 /* TODO: exact time to sleep is uncertain */
1886 msecs = 10;
1887 DELAY(msecs * 1000);
1888
1889 /* Need to toggle V bit back otherwise stuck in reset status */
1890 val &= ~PCIE_SOC_GLOBAL_RESET_V;
1891
1892 qwx_pcic_write32(sc, PCIE_SOC_GLOBAL_RESET, val);
1893
1894 DELAY(msecs * 1000);
1895
1896 val = qwx_pcic_read32(sc, PCIE_SOC_GLOBAL_RESET);
1897 if (val == 0xffffffff)
1898 printf("%s: link down error during global reset\n",
1899 sc->sc_dev.dv_xname);
1900 }
1901
1902 void
qwx_pci_clear_dbg_registers(struct qwx_softc * sc)1903 qwx_pci_clear_dbg_registers(struct qwx_softc *sc)
1904 {
1905 uint32_t val;
1906
1907 /* read cookie */
1908 val = qwx_pcic_read32(sc, PCIE_Q6_COOKIE_ADDR);
1909 DPRINTF("%s: cookie:0x%x\n", sc->sc_dev.dv_xname, val);
1910
1911 val = qwx_pcic_read32(sc, WLAON_WARM_SW_ENTRY);
1912 DPRINTF("%s: WLAON_WARM_SW_ENTRY 0x%x\n", sc->sc_dev.dv_xname, val);
1913
1914 /* TODO: exact time to sleep is uncertain */
1915 DELAY(10 * 1000);
1916
1917 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
1918 * continuing warm path and entering dead loop.
1919 */
1920 qwx_pcic_write32(sc, WLAON_WARM_SW_ENTRY, 0);
1921 DELAY(10 * 1000);
1922
1923 val = qwx_pcic_read32(sc, WLAON_WARM_SW_ENTRY);
1924 DPRINTF("%s: WLAON_WARM_SW_ENTRY 0x%x\n", sc->sc_dev.dv_xname, val);
1925
1926 /* A read clear register. clear the register to prevent
1927 * Q6 from entering wrong code path.
1928 */
1929 val = qwx_pcic_read32(sc, WLAON_SOC_RESET_CAUSE_REG);
1930 DPRINTF("%s: soc reset cause:%d\n", sc->sc_dev.dv_xname, val);
1931 }
1932
1933 int
qwx_pci_set_link_reg(struct qwx_softc * sc,uint32_t offset,uint32_t value,uint32_t mask)1934 qwx_pci_set_link_reg(struct qwx_softc *sc, uint32_t offset, uint32_t value,
1935 uint32_t mask)
1936 {
1937 uint32_t v;
1938 int i;
1939
1940 v = qwx_pcic_read32(sc, offset);
1941 if ((v & mask) == value)
1942 return 0;
1943
1944 for (i = 0; i < 10; i++) {
1945 qwx_pcic_write32(sc, offset, (v & ~mask) | value);
1946
1947 v = qwx_pcic_read32(sc, offset);
1948 if ((v & mask) == value)
1949 return 0;
1950
1951 delay((2 * 1000));
1952 }
1953
1954 DPRINTF("failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n",
1955 offset, v & mask, value);
1956
1957 return ETIMEDOUT;
1958 }
1959
1960 int
qwx_pci_fix_l1ss(struct qwx_softc * sc)1961 qwx_pci_fix_l1ss(struct qwx_softc *sc)
1962 {
1963 int ret;
1964
1965 ret = qwx_pci_set_link_reg(sc,
1966 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(sc),
1967 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL,
1968 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK);
1969 if (ret) {
1970 DPRINTF("failed to set sysclk: %d\n", ret);
1971 return ret;
1972 }
1973
1974 ret = qwx_pci_set_link_reg(sc,
1975 PCIE_PCS_OSC_DTCT_CONFIG1_REG(sc),
1976 PCIE_PCS_OSC_DTCT_CONFIG1_VAL,
1977 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
1978 if (ret) {
1979 DPRINTF("failed to set dtct config1 error: %d\n", ret);
1980 return ret;
1981 }
1982
1983 ret = qwx_pci_set_link_reg(sc,
1984 PCIE_PCS_OSC_DTCT_CONFIG2_REG(sc),
1985 PCIE_PCS_OSC_DTCT_CONFIG2_VAL,
1986 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
1987 if (ret) {
1988 DPRINTF("failed to set dtct config2: %d\n", ret);
1989 return ret;
1990 }
1991
1992 ret = qwx_pci_set_link_reg(sc,
1993 PCIE_PCS_OSC_DTCT_CONFIG4_REG(sc),
1994 PCIE_PCS_OSC_DTCT_CONFIG4_VAL,
1995 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
1996 if (ret) {
1997 DPRINTF("failed to set dtct config4: %d\n", ret);
1998 return ret;
1999 }
2000
2001 return 0;
2002 }
2003
2004 void
qwx_pci_enable_ltssm(struct qwx_softc * sc)2005 qwx_pci_enable_ltssm(struct qwx_softc *sc)
2006 {
2007 uint32_t val;
2008 int i;
2009
2010 val = qwx_pcic_read32(sc, PCIE_PCIE_PARF_LTSSM);
2011
2012 /* PCIE link seems very unstable after the Hot Reset*/
2013 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
2014 if (val == 0xffffffff)
2015 DELAY(5 * 1000);
2016
2017 qwx_pcic_write32(sc, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
2018 val = qwx_pcic_read32(sc, PCIE_PCIE_PARF_LTSSM);
2019 }
2020
2021 DPRINTF("%s: pci ltssm 0x%x\n", sc->sc_dev.dv_xname, val);
2022
2023 val = qwx_pcic_read32(sc, GCC_GCC_PCIE_HOT_RST);
2024 val |= GCC_GCC_PCIE_HOT_RST_VAL;
2025 qwx_pcic_write32(sc, GCC_GCC_PCIE_HOT_RST, val);
2026 val = qwx_pcic_read32(sc, GCC_GCC_PCIE_HOT_RST);
2027
2028 DPRINTF("%s: pci pcie_hot_rst 0x%x\n", sc->sc_dev.dv_xname, val);
2029
2030 DELAY(5 * 1000);
2031 }
2032
2033 void
qwx_pci_clear_all_intrs(struct qwx_softc * sc)2034 qwx_pci_clear_all_intrs(struct qwx_softc *sc)
2035 {
2036 /* This is a WAR for PCIE Hotreset.
2037 * When target receive Hotreset, but will set the interrupt.
2038 * So when download SBL again, SBL will open Interrupt and
2039 * receive it, and crash immediately.
2040 */
2041 qwx_pcic_write32(sc, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
2042 }
2043
2044 void
qwx_pci_set_wlaon_pwr_ctrl(struct qwx_softc * sc)2045 qwx_pci_set_wlaon_pwr_ctrl(struct qwx_softc *sc)
2046 {
2047 uint32_t val;
2048
2049 val = qwx_pcic_read32(sc, WLAON_QFPROM_PWR_CTRL_REG);
2050 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
2051 qwx_pcic_write32(sc, WLAON_QFPROM_PWR_CTRL_REG, val);
2052 }
2053
2054 void
qwx_pci_force_wake(struct qwx_softc * sc)2055 qwx_pci_force_wake(struct qwx_softc *sc)
2056 {
2057 qwx_pcic_write32(sc, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
2058 DELAY(5 * 1000);
2059 }
2060
2061 void
qwx_pci_sw_reset(struct qwx_softc * sc,bool power_on)2062 qwx_pci_sw_reset(struct qwx_softc *sc, bool power_on)
2063 {
2064 DELAY(100 * 1000); /* msecs */
2065
2066 if (power_on) {
2067 qwx_pci_enable_ltssm(sc);
2068 qwx_pci_clear_all_intrs(sc);
2069 qwx_pci_set_wlaon_pwr_ctrl(sc);
2070 if (sc->hw_params.fix_l1ss)
2071 qwx_pci_fix_l1ss(sc);
2072 }
2073
2074 qwx_mhi_clear_vector(sc);
2075 qwx_pci_clear_dbg_registers(sc);
2076 qwx_pci_soc_global_reset(sc);
2077 qwx_mhi_reset_device(sc, 0);
2078 }
2079
2080 void
qwx_pci_msi_config(struct qwx_softc * sc,bool enable)2081 qwx_pci_msi_config(struct qwx_softc *sc, bool enable)
2082 {
2083 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
2084 uint32_t val;
2085
2086 val = pci_conf_read(psc->sc_pc, psc->sc_tag,
2087 psc->sc_msi_off + PCI_MSI_MC);
2088
2089 if (enable)
2090 val |= PCI_MSI_MC_MSIE;
2091 else
2092 val &= ~PCI_MSI_MC_MSIE;
2093
2094 pci_conf_write(psc->sc_pc, psc->sc_tag, psc->sc_msi_off + PCI_MSI_MC,
2095 val);
2096 }
2097
2098 void
qwx_pci_msi_enable(struct qwx_softc * sc)2099 qwx_pci_msi_enable(struct qwx_softc *sc)
2100 {
2101 qwx_pci_msi_config(sc, true);
2102 }
2103
2104 void
qwx_pci_msi_disable(struct qwx_softc * sc)2105 qwx_pci_msi_disable(struct qwx_softc *sc)
2106 {
2107 qwx_pci_msi_config(sc, false);
2108 }
2109
2110 void
qwx_pci_aspm_disable(struct qwx_softc * sc)2111 qwx_pci_aspm_disable(struct qwx_softc *sc)
2112 {
2113 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
2114
2115 psc->sc_lcsr = pci_conf_read(psc->sc_pc, psc->sc_tag,
2116 psc->sc_cap_off + PCI_PCIE_LCSR);
2117
2118 DPRINTF("%s: pci link_ctl 0x%04x L0s %d L1 %d\n", sc->sc_dev.dv_xname,
2119 (uint16_t)psc->sc_lcsr, (psc->sc_lcsr & PCI_PCIE_LCSR_ASPM_L0S),
2120 (psc->sc_lcsr & PCI_PCIE_LCSR_ASPM_L1));
2121
2122 /* disable L0s and L1 */
2123 pci_conf_write(psc->sc_pc, psc->sc_tag, psc->sc_cap_off + PCI_PCIE_LCSR,
2124 psc->sc_lcsr & ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1));
2125
2126 psc->sc_flags |= ATH11K_PCI_ASPM_RESTORE;
2127 }
2128
2129 void
qwx_pci_aspm_restore(struct qwx_softc * sc)2130 qwx_pci_aspm_restore(struct qwx_softc *sc)
2131 {
2132 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
2133
2134 if (psc->sc_flags & ATH11K_PCI_ASPM_RESTORE) {
2135 pci_conf_write(psc->sc_pc, psc->sc_tag,
2136 psc->sc_cap_off + PCI_PCIE_LCSR, psc->sc_lcsr);
2137 psc->sc_flags &= ~ATH11K_PCI_ASPM_RESTORE;
2138 }
2139 }
2140
2141 int
qwx_pci_power_up(struct qwx_softc * sc)2142 qwx_pci_power_up(struct qwx_softc *sc)
2143 {
2144 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
2145 int error;
2146
2147 psc->register_window = 0;
2148 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, sc->sc_flags);
2149
2150 qwx_pci_sw_reset(sc, true);
2151
2152 /* Disable ASPM during firmware download due to problems switching
2153 * to AMSS state.
2154 */
2155 qwx_pci_aspm_disable(sc);
2156
2157 qwx_pci_msi_enable(sc);
2158
2159 error = qwx_mhi_start(psc);
2160 if (error)
2161 return error;
2162
2163 if (sc->hw_params.static_window_map)
2164 qwx_pci_select_static_window(sc);
2165
2166 return 0;
2167 }
2168
2169 void
qwx_pci_power_down(struct qwx_softc * sc)2170 qwx_pci_power_down(struct qwx_softc *sc)
2171 {
2172 /* restore aspm in case firmware bootup fails */
2173 qwx_pci_aspm_restore(sc);
2174
2175 qwx_pci_force_wake(sc);
2176
2177 qwx_pci_msi_disable(sc);
2178
2179 qwx_mhi_stop(sc);
2180 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, sc->sc_flags);
2181 qwx_pci_sw_reset(sc, false);
2182 }
2183
2184 /*
2185 * MHI
2186 */
2187 int
qwx_mhi_register(struct qwx_softc * sc)2188 qwx_mhi_register(struct qwx_softc *sc)
2189 {
2190 DNPRINTF(QWX_D_MHI, "%s: STUB %s()\n", sc->sc_dev.dv_xname, __func__);
2191 return 0;
2192 }
2193
2194 void
qwx_mhi_unregister(struct qwx_softc * sc)2195 qwx_mhi_unregister(struct qwx_softc *sc)
2196 {
2197 DNPRINTF(QWX_D_MHI, "%s: STUB %s()\n", sc->sc_dev.dv_xname, __func__);
2198 }
2199
2200 // XXX MHI is GPLd - we provide a compatible bare-bones implementation
2201 #define MHI_CFG 0x10
2202 #define MHI_CFG_NHWER_MASK GENMASK(31, 24)
2203 #define MHI_CFG_NHWER_SHFT 24
2204 #define MHI_CFG_NER_MASK GENMASK(23, 16)
2205 #define MHI_CFG_NER_SHFT 16
2206 #define MHI_CFG_NHWCH_MASK GENMASK(15, 8)
2207 #define MHI_CFG_NHWCH_SHFT 8
2208 #define MHI_CFG_NCH_MASK GENMASK(7, 0)
2209 #define MHI_CHDBOFF 0x18
2210 #define MHI_DEV_WAKE_DB 127
2211 #define MHI_ERDBOFF 0x20
2212 #define MHI_BHI_OFFSET 0x28
2213 #define MHI_BHI_IMGADDR_LOW 0x08
2214 #define MHI_BHI_IMGADDR_HIGH 0x0c
2215 #define MHI_BHI_IMGSIZE 0x10
2216 #define MHI_BHI_IMGTXDB 0x18
2217 #define MHI_BHI_INTVEC 0x20
2218 #define MHI_BHI_EXECENV 0x28
2219 #define MHI_BHI_STATUS 0x2c
2220 #define MHI_BHI_SERIALNU 0x40
2221 #define MHI_BHIE_OFFSET 0x2c
2222 #define MHI_BHIE_TXVECADDR_LOW_OFFS 0x2c
2223 #define MHI_BHIE_TXVECADDR_HIGH_OFFS 0x30
2224 #define MHI_BHIE_TXVECSIZE_OFFS 0x34
2225 #define MHI_BHIE_TXVECDB_OFFS 0x3c
2226 #define MHI_BHIE_TXVECSTATUS_OFFS 0x44
2227 #define MHI_BHIE_RXVECADDR_LOW_OFFS 0x60
2228 #define MHI_BHIE_RXVECSTATUS_OFFS 0x78
2229 #define MHI_CTRL 0x38
2230 #define MHI_CTRL_READY_MASK 0x1
2231 #define MHI_CTRL_RESET_MASK 0x2
2232 #define MHI_CTRL_MHISTATE_MASK GENMASK(15, 8)
2233 #define MHI_CTRL_MHISTATE_SHFT 8
2234 #define MHI_STATUS 0x48
2235 #define MHI_STATUS_MHISTATE_MASK GENMASK(15, 8)
2236 #define MHI_STATUS_MHISTATE_SHFT 8
2237 #define MHI_STATE_RESET 0x0
2238 #define MHI_STATE_READY 0x1
2239 #define MHI_STATE_M0 0x2
2240 #define MHI_STATE_M1 0x3
2241 #define MHI_STATE_M2 0x4
2242 #define MHI_STATE_M3 0x5
2243 #define MHI_STATE_M3_FAST 0x6
2244 #define MHI_STATE_BHI 0x7
2245 #define MHI_STATE_SYS_ERR 0xff
2246 #define MHI_STATUS_READY_MASK 0x1
2247 #define MHI_STATUS_SYSERR_MASK 0x4
2248 #define MHI_CCABAP_LOWER 0x58
2249 #define MHI_CCABAP_HIGHER 0x5c
2250 #define MHI_ECABAP_LOWER 0x60
2251 #define MHI_ECABAP_HIGHER 0x64
2252 #define MHI_CRCBAP_LOWER 0x68
2253 #define MHI_CRCBAP_HIGHER 0x6c
2254 #define MHI_CRDB_LOWER 0x70
2255 #define MHI_CRDB_HIGHER 0x74
2256 #define MHI_CTRLBASE_LOWER 0x80
2257 #define MHI_CTRLBASE_HIGHER 0x84
2258 #define MHI_CTRLLIMIT_LOWER 0x88
2259 #define MHI_CTRLLIMIT_HIGHER 0x8c
2260 #define MHI_DATABASE_LOWER 0x98
2261 #define MHI_DATABASE_HIGHER 0x9c
2262 #define MHI_DATALIMIT_LOWER 0xa0
2263 #define MHI_DATALIMIT_HIGHER 0xa4
2264
2265 #define MHI_EE_PBL 0x0 /* Primary Bootloader */
2266 #define MHI_EE_SBL 0x1 /* Secondary Bootloader */
2267 #define MHI_EE_AMSS 0x2 /* Modem, aka the primary runtime EE */
2268 #define MHI_EE_RDDM 0x3 /* Ram dump download mode */
2269 #define MHI_EE_WFW 0x4 /* WLAN firmware mode */
2270 #define MHI_EE_PTHRU 0x5 /* Passthrough */
2271 #define MHI_EE_EDL 0x6 /* Embedded downloader */
2272 #define MHI_EE_FP 0x7 /* Flash Programmer Environment */
2273
2274 #define MHI_IN_PBL(e) (e == MHI_EE_PBL || e == MHI_EE_PTHRU || e == MHI_EE_EDL)
2275 #define MHI_POWER_UP_CAPABLE(e) (MHI_IN_PBL(e) || e == MHI_EE_AMSS)
2276 #define MHI_IN_MISSION_MODE(e) \
2277 (e == MHI_EE_AMSS || e == MHI_EE_WFW || e == MHI_EE_FP)
2278
2279 /* BHI register bits */
2280 #define MHI_BHI_TXDB_SEQNUM_BMSK GENMASK(29, 0)
2281 #define MHI_BHI_TXDB_SEQNUM_SHFT 0
2282 #define MHI_BHI_STATUS_MASK GENMASK(31, 30)
2283 #define MHI_BHI_STATUS_SHFT 30
2284 #define MHI_BHI_STATUS_ERROR 0x03
2285 #define MHI_BHI_STATUS_SUCCESS 0x02
2286 #define MHI_BHI_STATUS_RESET 0x00
2287
2288 /* MHI BHIE registers */
2289 #define MHI_BHIE_MSMSOCID_OFFS 0x00
2290 #define MHI_BHIE_RXVECADDR_LOW_OFFS 0x60
2291 #define MHI_BHIE_RXVECADDR_HIGH_OFFS 0x64
2292 #define MHI_BHIE_RXVECSIZE_OFFS 0x68
2293 #define MHI_BHIE_RXVECDB_OFFS 0x70
2294 #define MHI_BHIE_RXVECSTATUS_OFFS 0x78
2295
2296 /* BHIE register bits */
2297 #define MHI_BHIE_TXVECDB_SEQNUM_BMSK GENMASK(29, 0)
2298 #define MHI_BHIE_TXVECDB_SEQNUM_SHFT 0
2299 #define MHI_BHIE_TXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
2300 #define MHI_BHIE_TXVECSTATUS_SEQNUM_SHFT 0
2301 #define MHI_BHIE_TXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
2302 #define MHI_BHIE_TXVECSTATUS_STATUS_SHFT 30
2303 #define MHI_BHIE_TXVECSTATUS_STATUS_RESET 0x00
2304 #define MHI_BHIE_TXVECSTATUS_STATUS_XFER_COMPL 0x02
2305 #define MHI_BHIE_TXVECSTATUS_STATUS_ERROR 0x03
2306 #define MHI_BHIE_RXVECDB_SEQNUM_BMSK GENMASK(29, 0)
2307 #define MHI_BHIE_RXVECDB_SEQNUM_SHFT 0
2308 #define MHI_BHIE_RXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
2309 #define MHI_BHIE_RXVECSTATUS_SEQNUM_SHFT 0
2310 #define MHI_BHIE_RXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
2311 #define MHI_BHIE_RXVECSTATUS_STATUS_SHFT 30
2312 #define MHI_BHIE_RXVECSTATUS_STATUS_RESET 0x00
2313 #define MHI_BHIE_RXVECSTATUS_STATUS_XFER_COMPL 0x02
2314 #define MHI_BHIE_RXVECSTATUS_STATUS_ERROR 0x03
2315
2316 #define MHI_EV_CC_INVALID 0x0
2317 #define MHI_EV_CC_SUCCESS 0x1
2318 #define MHI_EV_CC_EOT 0x2
2319 #define MHI_EV_CC_OVERFLOW 0x3
2320 #define MHI_EV_CC_EOB 0x4
2321 #define MHI_EV_CC_OOB 0x5
2322 #define MHI_EV_CC_DB_MODE 0x6
2323 #define MHI_EV_CC_UNDEFINED_ERR 0x10
2324 #define MHI_EV_CC_BAD_TRE 0x11
2325
2326 #define MHI_CMD_NOP 01
2327 #define MHI_CMD_RESET_CHAN 16
2328 #define MHI_CMD_STOP_CHAN 17
2329 #define MHI_CMD_START_CHAN 18
2330
2331 #define MHI_TRE_CMD_CHID_MASK GENMASK(31, 24)
2332 #define MHI_TRE_CMD_CHID_SHFT 24
2333 #define MHI_TRE_CMD_CMDID_MASK GENMASK(23, 16)
2334 #define MHI_TRE_CMD_CMDID_SHFT 16
2335
2336 #define MHI_TRE0_EV_LEN_MASK GENMASK(15, 0)
2337 #define MHI_TRE0_EV_LEN_SHFT 0
2338 #define MHI_TRE0_EV_CODE_MASK GENMASK(31, 24)
2339 #define MHI_TRE0_EV_CODE_SHFT 24
2340 #define MHI_TRE1_EV_TYPE_MASK GENMASK(23, 16)
2341 #define MHI_TRE1_EV_TYPE_SHFT 16
2342 #define MHI_TRE1_EV_CHID_MASK GENMASK(31, 24)
2343 #define MHI_TRE1_EV_CHID_SHFT 24
2344
2345 #define MHI_TRE0_DATA_LEN_MASK GENMASK(15, 0)
2346 #define MHI_TRE0_DATA_LEN_SHFT 0
2347 #define MHI_TRE1_DATA_CHAIN (1 << 0)
2348 #define MHI_TRE1_DATA_IEOB (1 << 8)
2349 #define MHI_TRE1_DATA_IEOT (1 << 9)
2350 #define MHI_TRE1_DATA_BEI (1 << 10)
2351 #define MHI_TRE1_DATA_TYPE_MASK GENMASK(23, 16)
2352 #define MHI_TRE1_DATA_TYPE_SHIFT 16
2353 #define MHI_TRE1_DATA_TYPE_TRANSFER 0x2
2354
2355 #define MHI_PKT_TYPE_INVALID 0x00
2356 #define MHI_PKT_TYPE_NOOP_CMD 0x01
2357 #define MHI_PKT_TYPE_TRANSFER 0x02
2358 #define MHI_PKT_TYPE_COALESCING 0x08
2359 #define MHI_PKT_TYPE_RESET_CHAN_CMD 0x10
2360 #define MHI_PKT_TYPE_STOP_CHAN_CMD 0x11
2361 #define MHI_PKT_TYPE_START_CHAN_CMD 0x12
2362 #define MHI_PKT_TYPE_STATE_CHANGE_EVENT 0x20
2363 #define MHI_PKT_TYPE_CMD_COMPLETION_EVENT 0x21
2364 #define MHI_PKT_TYPE_TX_EVENT 0x22
2365 #define MHI_PKT_TYPE_RSC_TX_EVENT 0x28
2366 #define MHI_PKT_TYPE_EE_EVENT 0x40
2367 #define MHI_PKT_TYPE_TSYNC_EVENT 0x48
2368 #define MHI_PKT_TYPE_BW_REQ_EVENT 0x50
2369
2370
2371 #define MHI_DMA_VEC_CHUNK_SIZE 524288 /* 512 KB */
2372 struct qwx_dma_vec_entry {
2373 uint64_t paddr;
2374 uint64_t size;
2375 };
2376
2377 void
qwx_mhi_ring_doorbell(struct qwx_softc * sc,uint64_t db_addr,uint64_t val)2378 qwx_mhi_ring_doorbell(struct qwx_softc *sc, uint64_t db_addr, uint64_t val)
2379 {
2380 qwx_pci_write(sc, db_addr + 4, val >> 32);
2381 qwx_pci_write(sc, db_addr, val & 0xffffffff);
2382 }
2383
2384 void
qwx_mhi_device_wake(struct qwx_softc * sc)2385 qwx_mhi_device_wake(struct qwx_softc *sc)
2386 {
2387 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
2388
2389 /*
2390 * Device wake is async only for now because we do not
2391 * keep track of PM state in software.
2392 */
2393 qwx_mhi_ring_doorbell(sc, psc->wake_db, 1);
2394 }
2395
2396 void
qwx_mhi_device_zzz(struct qwx_softc * sc)2397 qwx_mhi_device_zzz(struct qwx_softc *sc)
2398 {
2399 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
2400
2401 qwx_mhi_ring_doorbell(sc, psc->wake_db, 0);
2402 }
2403
2404 int
qwx_mhi_wake_db_clear_valid(struct qwx_softc * sc)2405 qwx_mhi_wake_db_clear_valid(struct qwx_softc *sc)
2406 {
2407 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
2408
2409 return (psc->mhi_state == MHI_STATE_M0); /* TODO other states? */
2410 }
2411
2412 void
qwx_mhi_init_xfer_rings(struct qwx_pci_softc * psc)2413 qwx_mhi_init_xfer_rings(struct qwx_pci_softc *psc)
2414 {
2415 struct qwx_softc *sc = &psc->sc_sc;
2416 int i;
2417 uint32_t chcfg;
2418 struct qwx_pci_xfer_ring *ring;
2419 struct qwx_mhi_chan_ctxt *cbase, *c;
2420
2421 cbase = (struct qwx_mhi_chan_ctxt *)QWX_DMA_KVA(psc->chan_ctxt);
2422 for (i = 0; i < psc->max_chan; i++) {
2423 c = &cbase[i];
2424 chcfg = le32toh(c->chcfg);
2425 chcfg &= ~(MHI_CHAN_CTX_CHSTATE_MASK |
2426 MHI_CHAN_CTX_BRSTMODE_MASK |
2427 MHI_CHAN_CTX_POLLCFG_MASK);
2428 chcfg |= (MHI_CHAN_CTX_CHSTATE_DISABLED |
2429 (MHI_CHAN_CTX_BRSTMODE_DISABLE <<
2430 MHI_CHAN_CTX_BRSTMODE_SHFT));
2431 c->chcfg = htole32(chcfg);
2432 c->chtype = htole32(MHI_CHAN_TYPE_INVALID);
2433 c->erindex = 0;
2434 }
2435
2436 for (i = 0; i < nitems(psc->xfer_rings); i++) {
2437 ring = &psc->xfer_rings[i];
2438 KASSERT(ring->mhi_chan_id < psc->max_chan);
2439 c = &cbase[ring->mhi_chan_id];
2440 c->chtype = htole32(ring->mhi_chan_direction);
2441 c->erindex = htole32(ring->mhi_chan_event_ring_index);
2442 ring->chan_ctxt = c;
2443 }
2444
2445 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(psc->chan_ctxt), 0,
2446 QWX_DMA_LEN(psc->chan_ctxt), BUS_DMASYNC_PREWRITE);
2447 }
2448
2449 void
qwx_mhi_init_event_rings(struct qwx_pci_softc * psc)2450 qwx_mhi_init_event_rings(struct qwx_pci_softc *psc)
2451 {
2452 struct qwx_softc *sc = &psc->sc_sc;
2453 int i;
2454 uint32_t intmod;
2455 uint64_t paddr, len;
2456 struct qwx_pci_event_ring *ring;
2457 struct qwx_mhi_event_ctxt *c;
2458
2459 c = (struct qwx_mhi_event_ctxt *)QWX_DMA_KVA(psc->event_ctxt);
2460 for (i = 0; i < nitems(psc->event_rings); i++, c++) {
2461 ring = &psc->event_rings[i];
2462
2463 ring->event_ctxt = c;
2464
2465 intmod = le32toh(c->intmod);
2466 intmod &= ~(MHI_EV_CTX_INTMODC_MASK | MHI_EV_CTX_INTMODT_MASK);
2467 intmod |= (ring->mhi_er_irq_moderation_ms <<
2468 MHI_EV_CTX_INTMODT_SHFT) & MHI_EV_CTX_INTMODT_MASK;
2469 c->intmod = htole32(intmod);
2470
2471 c->ertype = htole32(MHI_ER_TYPE_VALID);
2472 c->msivec = htole32(ring->mhi_er_irq);
2473
2474 paddr = QWX_DMA_DVA(ring->dmamem);
2475 ring->rp = paddr;
2476 ring->wp = paddr + ring->size -
2477 sizeof(struct qwx_mhi_ring_element);
2478 c->rbase = htole64(paddr);
2479 c->rp = htole64(ring->rp);
2480 c->wp = htole64(ring->wp);
2481
2482 len = sizeof(struct qwx_mhi_ring_element) * ring->num_elements;
2483 c->rlen = htole64(len);
2484 }
2485
2486 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(psc->event_ctxt), 0,
2487 QWX_DMA_LEN(psc->event_ctxt), BUS_DMASYNC_PREWRITE);
2488 }
2489
2490 void
qwx_mhi_init_cmd_ring(struct qwx_pci_softc * psc)2491 qwx_mhi_init_cmd_ring(struct qwx_pci_softc *psc)
2492 {
2493 struct qwx_softc *sc = &psc->sc_sc;
2494 struct qwx_pci_cmd_ring *ring = &psc->cmd_ring;
2495 struct qwx_mhi_cmd_ctxt *c;
2496 uint64_t paddr, len;
2497
2498 paddr = QWX_DMA_DVA(ring->dmamem);
2499 len = ring->size;
2500
2501 ring->rp = ring->wp = paddr;
2502
2503 c = (struct qwx_mhi_cmd_ctxt *)QWX_DMA_KVA(psc->cmd_ctxt);
2504 c->rbase = htole64(paddr);
2505 c->rp = htole64(paddr);
2506 c->wp = htole64(paddr);
2507 c->rlen = htole64(len);
2508
2509 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(psc->cmd_ctxt), 0,
2510 QWX_DMA_LEN(psc->cmd_ctxt), BUS_DMASYNC_PREWRITE);
2511 }
2512
2513 void
qwx_mhi_init_dev_ctxt(struct qwx_pci_softc * psc)2514 qwx_mhi_init_dev_ctxt(struct qwx_pci_softc *psc)
2515 {
2516 qwx_mhi_init_xfer_rings(psc);
2517 qwx_mhi_init_event_rings(psc);
2518 qwx_mhi_init_cmd_ring(psc);
2519 }
2520
2521 void *
qwx_pci_cmd_ring_get_elem(struct qwx_pci_cmd_ring * ring,uint64_t ptr)2522 qwx_pci_cmd_ring_get_elem(struct qwx_pci_cmd_ring *ring, uint64_t ptr)
2523 {
2524 uint64_t base = QWX_DMA_DVA(ring->dmamem), offset;
2525
2526 if (ptr < base || ptr >= base + ring->size)
2527 return NULL;
2528
2529 offset = ptr - base;
2530 if (offset >= ring->size)
2531 return NULL;
2532
2533 return QWX_DMA_KVA(ring->dmamem) + offset;
2534 }
2535
2536 int
qwx_mhi_cmd_ring_submit(struct qwx_pci_softc * psc,struct qwx_pci_cmd_ring * ring)2537 qwx_mhi_cmd_ring_submit(struct qwx_pci_softc *psc,
2538 struct qwx_pci_cmd_ring *ring)
2539 {
2540 struct qwx_softc *sc = &psc->sc_sc;
2541 uint64_t base = QWX_DMA_DVA(ring->dmamem);
2542 struct qwx_mhi_cmd_ctxt *c;
2543
2544 if (ring->queued >= ring->num_elements)
2545 return 1;
2546
2547 if (ring->wp + sizeof(struct qwx_mhi_ring_element) >= base + ring->size)
2548 ring->wp = base;
2549 else
2550 ring->wp += sizeof(struct qwx_mhi_ring_element);
2551
2552 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(psc->cmd_ctxt), 0,
2553 QWX_DMA_LEN(psc->cmd_ctxt), BUS_DMASYNC_POSTREAD);
2554
2555 c = (struct qwx_mhi_cmd_ctxt *)QWX_DMA_KVA(psc->cmd_ctxt);
2556 c->wp = htole64(ring->wp);
2557
2558 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(psc->cmd_ctxt), 0,
2559 QWX_DMA_LEN(psc->cmd_ctxt), BUS_DMASYNC_PREWRITE);
2560
2561 ring->queued++;
2562 qwx_mhi_ring_doorbell(sc, MHI_CRDB_LOWER, ring->wp);
2563 return 0;
2564 }
2565
2566 int
qwx_mhi_send_cmd(struct qwx_pci_softc * psc,uint32_t cmd,uint32_t chan)2567 qwx_mhi_send_cmd(struct qwx_pci_softc *psc, uint32_t cmd, uint32_t chan)
2568 {
2569 struct qwx_softc *sc = &psc->sc_sc;
2570 struct qwx_pci_cmd_ring *ring = &psc->cmd_ring;
2571 struct qwx_mhi_ring_element *e;
2572
2573 if (ring->queued >= ring->num_elements) {
2574 printf("%s: command ring overflow\n", sc->sc_dev.dv_xname);
2575 return 1;
2576 }
2577
2578 e = qwx_pci_cmd_ring_get_elem(ring, ring->wp);
2579 if (e == NULL)
2580 return 1;
2581
2582 e->ptr = 0ULL;
2583 e->dword[0] = 0;
2584 e->dword[1] = htole32(
2585 ((chan << MHI_TRE_CMD_CHID_SHFT) & MHI_TRE_CMD_CHID_MASK) |
2586 ((cmd << MHI_TRE_CMD_CMDID_SHFT) & MHI_TRE_CMD_CMDID_MASK));
2587
2588 return qwx_mhi_cmd_ring_submit(psc, ring);
2589 }
2590
2591 void *
qwx_pci_xfer_ring_get_elem(struct qwx_pci_xfer_ring * ring,uint64_t wp)2592 qwx_pci_xfer_ring_get_elem(struct qwx_pci_xfer_ring *ring, uint64_t wp)
2593 {
2594 uint64_t base = QWX_DMA_DVA(ring->dmamem), offset;
2595 void *addr = QWX_DMA_KVA(ring->dmamem);
2596
2597 if (wp < base)
2598 return NULL;
2599
2600 offset = wp - base;
2601 if (offset >= ring->size)
2602 return NULL;
2603
2604 return addr + offset;
2605 }
2606
2607 struct qwx_xfer_data *
qwx_pci_xfer_ring_get_data(struct qwx_pci_xfer_ring * ring,uint64_t wp)2608 qwx_pci_xfer_ring_get_data(struct qwx_pci_xfer_ring *ring, uint64_t wp)
2609 {
2610 uint64_t base = QWX_DMA_DVA(ring->dmamem), offset;
2611
2612 if (wp < base)
2613 return NULL;
2614
2615 offset = wp - base;
2616 if (offset >= ring->size)
2617 return NULL;
2618
2619 return &ring->data[offset / sizeof(ring->data[0])];
2620 }
2621
2622 int
qwx_mhi_submit_xfer(struct qwx_softc * sc,struct mbuf * m)2623 qwx_mhi_submit_xfer(struct qwx_softc *sc, struct mbuf *m)
2624 {
2625 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
2626 struct qwx_pci_xfer_ring *ring;
2627 struct qwx_mhi_ring_element *e;
2628 struct qwx_xfer_data *xfer;
2629 uint64_t paddr, base;
2630 int err;
2631
2632 ring = &psc->xfer_rings[QWX_PCI_XFER_RING_IPCR_OUTBOUND];
2633
2634 if (ring->queued >= ring->num_elements)
2635 return 1;
2636
2637 if (m->m_pkthdr.len > QWX_PCI_XFER_MAX_DATA_SIZE) {
2638 /* TODO: chunk xfers */
2639 printf("%s: xfer too large: %d bytes\n", __func__, m->m_pkthdr.len);
2640 return 1;
2641
2642 }
2643
2644 e = qwx_pci_xfer_ring_get_elem(ring, ring->wp);
2645 if (e == NULL)
2646 return 1;
2647
2648 xfer = qwx_pci_xfer_ring_get_data(ring, ring->wp);
2649 if (xfer == NULL || xfer->m != NULL)
2650 return 1;
2651
2652 err = bus_dmamap_load_mbuf(sc->sc_dmat, xfer->map, m,
2653 BUS_DMA_NOWAIT | BUS_DMA_WRITE);
2654 if (err && err != EFBIG) {
2655 printf("%s: can't map mbuf (error %d)\n",
2656 sc->sc_dev.dv_xname, err);
2657 return err;
2658 }
2659 if (err) {
2660 /* Too many DMA segments, linearize mbuf. */
2661 if (m_defrag(m, M_DONTWAIT))
2662 return ENOBUFS;
2663 err = bus_dmamap_load_mbuf(sc->sc_dmat, xfer->map, m,
2664 BUS_DMA_NOWAIT | BUS_DMA_WRITE);
2665 if (err) {
2666 printf("%s: can't map mbuf (error %d)\n",
2667 sc->sc_dev.dv_xname, err);
2668 return err;
2669 }
2670 }
2671
2672 bus_dmamap_sync(sc->sc_dmat, xfer->map, 0, m->m_pkthdr.len,
2673 BUS_DMASYNC_PREWRITE);
2674
2675 xfer->m = m;
2676 paddr = xfer->map->dm_segs[0].ds_addr;
2677
2678 e->ptr = htole64(paddr);
2679 e->dword[0] = htole32((m->m_pkthdr.len << MHI_TRE0_DATA_LEN_SHFT) &
2680 MHI_TRE0_DATA_LEN_MASK);
2681 e->dword[1] = htole32(MHI_TRE1_DATA_IEOT |
2682 MHI_TRE1_DATA_TYPE_TRANSFER << MHI_TRE1_DATA_TYPE_SHIFT);
2683
2684 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(ring->dmamem),
2685 0, QWX_DMA_LEN(ring->dmamem), BUS_DMASYNC_PREWRITE);
2686
2687 base = QWX_DMA_DVA(ring->dmamem);
2688 if (ring->wp + sizeof(struct qwx_mhi_ring_element) >= base + ring->size)
2689 ring->wp = base;
2690 else
2691 ring->wp += sizeof(struct qwx_mhi_ring_element);
2692 ring->queued++;
2693
2694 ring->chan_ctxt->wp = htole64(ring->wp);
2695
2696 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(psc->chan_ctxt), 0,
2697 QWX_DMA_LEN(psc->chan_ctxt), BUS_DMASYNC_PREWRITE);
2698
2699 qwx_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
2700 return 0;
2701 }
2702
2703 int
qwx_mhi_start_channel(struct qwx_pci_softc * psc,struct qwx_pci_xfer_ring * ring)2704 qwx_mhi_start_channel(struct qwx_pci_softc *psc,
2705 struct qwx_pci_xfer_ring *ring)
2706 {
2707 struct qwx_softc *sc = &psc->sc_sc;
2708 struct qwx_mhi_chan_ctxt *c;
2709 int ret = 0;
2710 uint32_t chcfg;
2711 uint64_t paddr, len;
2712
2713 DNPRINTF(QWX_D_MHI, "%s: start MHI channel %d in state %d\n", __func__,
2714 ring->mhi_chan_id, ring->mhi_chan_state);
2715
2716 c = ring->chan_ctxt;
2717
2718 chcfg = le32toh(c->chcfg);
2719 chcfg &= ~MHI_CHAN_CTX_CHSTATE_MASK;
2720 chcfg |= MHI_CHAN_CTX_CHSTATE_ENABLED;
2721 c->chcfg = htole32(chcfg);
2722
2723 paddr = QWX_DMA_DVA(ring->dmamem);
2724 ring->rp = ring->wp = paddr;
2725 c->rbase = htole64(paddr);
2726 c->rp = htole64(ring->rp);
2727 c->wp = htole64(ring->wp);
2728 len = sizeof(struct qwx_mhi_ring_element) * ring->num_elements;
2729 c->rlen = htole64(len);
2730
2731 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(psc->chan_ctxt), 0,
2732 QWX_DMA_LEN(psc->chan_ctxt), BUS_DMASYNC_PREWRITE);
2733
2734 ring->cmd_status = MHI_EV_CC_INVALID;
2735 if (qwx_mhi_send_cmd(psc, MHI_CMD_START_CHAN, ring->mhi_chan_id))
2736 return 1;
2737
2738 while (ring->cmd_status != MHI_EV_CC_SUCCESS) {
2739 ret = tsleep_nsec(&ring->cmd_status, 0, "qwxcmd",
2740 SEC_TO_NSEC(5));
2741 if (ret)
2742 break;
2743 }
2744
2745 if (ret) {
2746 printf("%s: could not start MHI channel %d in state %d: status 0x%x\n",
2747 sc->sc_dev.dv_xname, ring->mhi_chan_id,
2748 ring->mhi_chan_state, ring->cmd_status);
2749 return 1;
2750 }
2751
2752 if (ring->mhi_chan_direction == MHI_CHAN_TYPE_INBOUND) {
2753 uint64_t wp = QWX_DMA_DVA(ring->dmamem);
2754 int i;
2755
2756 for (i = 0; i < ring->num_elements; i++) {
2757 struct qwx_mhi_ring_element *e;
2758 struct qwx_xfer_data *xfer;
2759 uint64_t paddr;
2760
2761 e = qwx_pci_xfer_ring_get_elem(ring, wp);
2762 xfer = qwx_pci_xfer_ring_get_data(ring, wp);
2763 paddr = xfer->map->dm_segs[0].ds_addr;
2764
2765 e->ptr = htole64(paddr);
2766 e->dword[0] = htole32((QWX_PCI_XFER_MAX_DATA_SIZE <<
2767 MHI_TRE0_DATA_LEN_SHFT) &
2768 MHI_TRE0_DATA_LEN_MASK);
2769 e->dword[1] = htole32(MHI_TRE1_DATA_IEOT |
2770 MHI_TRE1_DATA_BEI |
2771 MHI_TRE1_DATA_TYPE_TRANSFER <<
2772 MHI_TRE1_DATA_TYPE_SHIFT);
2773
2774 ring->wp = wp;
2775 wp += sizeof(*e);
2776 }
2777
2778 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(ring->dmamem), 0,
2779 QWX_DMA_LEN(ring->dmamem), BUS_DMASYNC_PREWRITE);
2780
2781 qwx_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
2782 }
2783
2784 return 0;
2785 }
2786
2787 int
qwx_mhi_start_channels(struct qwx_pci_softc * psc)2788 qwx_mhi_start_channels(struct qwx_pci_softc *psc)
2789 {
2790 struct qwx_pci_xfer_ring *ring;
2791 int ret = 0;
2792
2793 qwx_mhi_device_wake(&psc->sc_sc);
2794
2795 ring = &psc->xfer_rings[QWX_PCI_XFER_RING_IPCR_OUTBOUND];
2796 if (qwx_mhi_start_channel(psc, ring)) {
2797 ret = 1;
2798 goto done;
2799 }
2800
2801 ring = &psc->xfer_rings[QWX_PCI_XFER_RING_IPCR_INBOUND];
2802 if (qwx_mhi_start_channel(psc, ring))
2803 ret = 1;
2804 done:
2805 qwx_mhi_device_zzz(&psc->sc_sc);
2806 return ret;
2807 }
2808
2809 int
qwx_mhi_start(struct qwx_pci_softc * psc)2810 qwx_mhi_start(struct qwx_pci_softc *psc)
2811 {
2812 struct qwx_softc *sc = &psc->sc_sc;
2813 uint32_t off;
2814 uint32_t ee, state;
2815 int ret;
2816
2817 qwx_mhi_init_dev_ctxt(psc);
2818
2819 psc->bhi_off = qwx_pci_read(sc, MHI_BHI_OFFSET);
2820 DNPRINTF(QWX_D_MHI, "%s: BHI offset 0x%x\n", __func__, psc->bhi_off);
2821
2822 psc->bhie_off = qwx_pci_read(sc, MHI_BHIE_OFFSET);
2823 DNPRINTF(QWX_D_MHI, "%s: BHIE offset 0x%x\n", __func__, psc->bhie_off);
2824
2825 /* Clean BHIE RX registers */
2826 for (off = MHI_BHIE_RXVECADDR_LOW_OFFS;
2827 off < (MHI_BHIE_RXVECSTATUS_OFFS - 4);
2828 off += 4)
2829 qwx_pci_write(sc, psc->bhie_off + off, 0x0);
2830
2831 qwx_rddm_prepare(psc);
2832
2833 /* Program BHI INTVEC */
2834 qwx_pci_write(sc, psc->bhi_off + MHI_BHI_INTVEC, 0x00);
2835
2836 /*
2837 * Get BHI execution environment and confirm that it is valid
2838 * for power on.
2839 */
2840 ee = qwx_pci_read(sc, psc->bhi_off + MHI_BHI_EXECENV);
2841 if (!MHI_POWER_UP_CAPABLE(ee)) {
2842 printf("%s: invalid EE for power on: 0x%x\n",
2843 sc->sc_dev.dv_xname, ee);
2844 return 1;
2845 }
2846
2847 /*
2848 * Get MHI state of the device and reset it if it is in system
2849 * error.
2850 */
2851 state = qwx_pci_read(sc, MHI_STATUS);
2852 DNPRINTF(QWX_D_MHI, "%s: MHI power on with EE: 0x%x, status: 0x%x\n",
2853 sc->sc_dev.dv_xname, ee, state);
2854 state = (state & MHI_STATUS_MHISTATE_MASK) >> MHI_STATUS_MHISTATE_SHFT;
2855 if (state == MHI_STATE_SYS_ERR) {
2856 if (qwx_mhi_reset_device(sc, 0))
2857 return 1;
2858 state = qwx_pci_read(sc, MHI_STATUS);
2859 DNPRINTF(QWX_D_MHI, "%s: MHI state after reset: 0x%x\n",
2860 sc->sc_dev.dv_xname, state);
2861 state = (state & MHI_STATUS_MHISTATE_MASK) >>
2862 MHI_STATUS_MHISTATE_SHFT;
2863 if (state == MHI_STATE_SYS_ERR) {
2864 printf("%s: MHI stuck in system error state\n",
2865 sc->sc_dev.dv_xname);
2866 return 1;
2867 }
2868 }
2869
2870 psc->bhi_ee = ee;
2871 psc->mhi_state = state;
2872
2873 #if notyet
2874 /* Enable IRQs */
2875 // XXX todo?
2876 #endif
2877
2878 /* Transition to primary runtime. */
2879 if (MHI_IN_PBL(ee)) {
2880 ret = qwx_mhi_fw_load_handler(psc);
2881 if (ret)
2882 return ret;
2883
2884 /* XXX without this delay starting the channels may fail */
2885 delay(1000);
2886 qwx_mhi_start_channels(psc);
2887 } else {
2888 /* XXX Handle partially initialized device...?!? */
2889 ee = qwx_pci_read(sc, psc->bhi_off + MHI_BHI_EXECENV);
2890 if (!MHI_IN_MISSION_MODE(ee)) {
2891 printf("%s: failed to power up MHI, ee=0x%x\n",
2892 sc->sc_dev.dv_xname, ee);
2893 return EIO;
2894 }
2895 }
2896
2897 return 0;
2898 }
2899
2900 void
qwx_mhi_stop(struct qwx_softc * sc)2901 qwx_mhi_stop(struct qwx_softc *sc)
2902 {
2903 qwx_mhi_reset_device(sc, 1);
2904 }
2905
2906 int
qwx_mhi_reset_device(struct qwx_softc * sc,int force)2907 qwx_mhi_reset_device(struct qwx_softc *sc, int force)
2908 {
2909 struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
2910 uint32_t reg;
2911 int ret = 0;
2912
2913 reg = qwx_pcic_read32(sc, MHI_STATUS);
2914
2915 DNPRINTF(QWX_D_MHI, "%s: MHISTATUS 0x%x\n", sc->sc_dev.dv_xname, reg);
2916 /*
2917 * Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS
2918 * has SYSERR bit set and thus need to set MHICTRL_RESET
2919 * to clear SYSERR.
2920 */
2921 if (force || (reg & MHI_STATUS_SYSERR_MASK)) {
2922 /* Trigger MHI Reset in device. */
2923 qwx_pcic_write32(sc, MHI_CTRL, MHI_CTRL_RESET_MASK);
2924
2925 /* Wait for the reset bit to be cleared by the device. */
2926 ret = qwx_mhi_await_device_reset(sc);
2927 if (ret)
2928 return ret;
2929
2930 if (psc->bhi_off == 0)
2931 psc->bhi_off = qwx_pci_read(sc, MHI_BHI_OFFSET);
2932
2933 /* Device clear BHI INTVEC so re-program it. */
2934 qwx_pci_write(sc, psc->bhi_off + MHI_BHI_INTVEC, 0x00);
2935 }
2936
2937 return 0;
2938 }
2939
2940 static inline void
qwx_mhi_reset_txvecdb(struct qwx_softc * sc)2941 qwx_mhi_reset_txvecdb(struct qwx_softc *sc)
2942 {
2943 qwx_pcic_write32(sc, PCIE_TXVECDB, 0);
2944 }
2945
2946 static inline void
qwx_mhi_reset_txvecstatus(struct qwx_softc * sc)2947 qwx_mhi_reset_txvecstatus(struct qwx_softc *sc)
2948 {
2949 qwx_pcic_write32(sc, PCIE_TXVECSTATUS, 0);
2950 }
2951
2952 static inline void
qwx_mhi_reset_rxvecdb(struct qwx_softc * sc)2953 qwx_mhi_reset_rxvecdb(struct qwx_softc *sc)
2954 {
2955 qwx_pcic_write32(sc, PCIE_RXVECDB, 0);
2956 }
2957
2958 static inline void
qwx_mhi_reset_rxvecstatus(struct qwx_softc * sc)2959 qwx_mhi_reset_rxvecstatus(struct qwx_softc *sc)
2960 {
2961 qwx_pcic_write32(sc, PCIE_RXVECSTATUS, 0);
2962 }
2963
2964 void
qwx_mhi_clear_vector(struct qwx_softc * sc)2965 qwx_mhi_clear_vector(struct qwx_softc *sc)
2966 {
2967 qwx_mhi_reset_txvecdb(sc);
2968 qwx_mhi_reset_txvecstatus(sc);
2969 qwx_mhi_reset_rxvecdb(sc);
2970 qwx_mhi_reset_rxvecstatus(sc);
2971 }
2972
2973 int
qwx_mhi_fw_load_handler(struct qwx_pci_softc * psc)2974 qwx_mhi_fw_load_handler(struct qwx_pci_softc *psc)
2975 {
2976 struct qwx_softc *sc = &psc->sc_sc;
2977 int ret;
2978 char amss_path[PATH_MAX];
2979 u_char *data;
2980 size_t len;
2981
2982 if (sc->fw_img[QWX_FW_AMSS].data) {
2983 data = sc->fw_img[QWX_FW_AMSS].data;
2984 len = sc->fw_img[QWX_FW_AMSS].size;
2985 } else {
2986 ret = snprintf(amss_path, sizeof(amss_path), "%s-%s-%s",
2987 ATH11K_FW_DIR, sc->hw_params.fw.dir, ATH11K_AMSS_FILE);
2988 if (ret < 0 || ret >= sizeof(amss_path))
2989 return ENOSPC;
2990
2991 ret = loadfirmware(amss_path, &data, &len);
2992 if (ret) {
2993 printf("%s: could not read %s (error %d)\n",
2994 sc->sc_dev.dv_xname, amss_path, ret);
2995 return ret;
2996 }
2997
2998 if (len < MHI_DMA_VEC_CHUNK_SIZE) {
2999 printf("%s: %s is too short, have only %zu bytes\n",
3000 sc->sc_dev.dv_xname, amss_path, len);
3001 free(data, M_DEVBUF, len);
3002 return EINVAL;
3003 }
3004
3005 sc->fw_img[QWX_FW_AMSS].data = data;
3006 sc->fw_img[QWX_FW_AMSS].size = len;
3007 }
3008
3009 /* Second-stage boot loader sits in the first 512 KB of image. */
3010 ret = qwx_mhi_fw_load_bhi(psc, data, MHI_DMA_VEC_CHUNK_SIZE);
3011 if (ret != 0) {
3012 printf("%s: could not load firmware %s\n",
3013 sc->sc_dev.dv_xname, amss_path);
3014 return ret;
3015 }
3016
3017 /* Now load the full image. */
3018 ret = qwx_mhi_fw_load_bhie(psc, data, len);
3019 if (ret != 0) {
3020 printf("%s: could not load firmware %s\n",
3021 sc->sc_dev.dv_xname, amss_path);
3022 return ret;
3023 }
3024
3025 while (psc->bhi_ee < MHI_EE_AMSS) {
3026 ret = tsleep_nsec(&psc->bhi_ee, 0, "qwxamss",
3027 SEC_TO_NSEC(5));
3028 if (ret)
3029 break;
3030 }
3031 if (ret != 0) {
3032 printf("%s: device failed to enter AMSS EE\n",
3033 sc->sc_dev.dv_xname);
3034 }
3035
3036 return ret;
3037 }
3038
3039 int
qwx_mhi_await_device_reset(struct qwx_softc * sc)3040 qwx_mhi_await_device_reset(struct qwx_softc *sc)
3041 {
3042 const uint32_t msecs = 24, retries = 2;
3043 uint32_t reg;
3044 int timeout;
3045
3046 /* Poll for CTRL RESET to clear. */
3047 timeout = retries;
3048 while (timeout > 0) {
3049 reg = qwx_pci_read(sc, MHI_CTRL);
3050 DNPRINTF(QWX_D_MHI, "%s: MHI_CTRL is 0x%x\n", __func__, reg);
3051 if ((reg & MHI_CTRL_RESET_MASK) == 0)
3052 break;
3053 DELAY((msecs / retries) * 1000);
3054 timeout--;
3055 }
3056 if (timeout == 0) {
3057 DNPRINTF(QWX_D_MHI, "%s: MHI reset failed\n", __func__);
3058 return ETIMEDOUT;
3059 }
3060
3061 return 0;
3062 }
3063
3064 int
qwx_mhi_await_device_ready(struct qwx_softc * sc)3065 qwx_mhi_await_device_ready(struct qwx_softc *sc)
3066 {
3067 uint32_t reg;
3068 int timeout;
3069 const uint32_t msecs = 2000, retries = 4;
3070
3071
3072 /* Poll for READY to be set. */
3073 timeout = retries;
3074 while (timeout > 0) {
3075 reg = qwx_pci_read(sc, MHI_STATUS);
3076 DNPRINTF(QWX_D_MHI, "%s: MHI_STATUS is 0x%x\n", __func__, reg);
3077 if (reg & MHI_STATUS_READY_MASK) {
3078 reg &= ~MHI_STATUS_READY_MASK;
3079 qwx_pci_write(sc, MHI_STATUS, reg);
3080 break;
3081 }
3082 DELAY((msecs / retries) * 1000);
3083 timeout--;
3084 }
3085 if (timeout == 0) {
3086 printf("%s: MHI not ready\n", sc->sc_dev.dv_xname);
3087 return ETIMEDOUT;
3088 }
3089
3090 return 0;
3091 }
3092
3093 void
qwx_mhi_ready_state_transition(struct qwx_pci_softc * psc)3094 qwx_mhi_ready_state_transition(struct qwx_pci_softc *psc)
3095 {
3096 struct qwx_softc *sc = &psc->sc_sc;
3097 int ret, i;
3098
3099 ret = qwx_mhi_await_device_reset(sc);
3100 if (ret)
3101 return;
3102
3103 ret = qwx_mhi_await_device_ready(sc);
3104 if (ret)
3105 return;
3106
3107 /* Set up memory-mapped IO for channels, events, etc. */
3108 qwx_mhi_init_mmio(psc);
3109
3110 /* Notify event rings. */
3111 for (i = 0; i < nitems(psc->event_rings); i++) {
3112 struct qwx_pci_event_ring *ring = &psc->event_rings[i];
3113 qwx_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
3114 }
3115
3116 /*
3117 * Set the device into M0 state. The device will transition
3118 * into M0 and the execution environment will switch to SBL.
3119 */
3120 qwx_mhi_set_state(sc, MHI_STATE_M0);
3121 }
3122
3123 void
qwx_mhi_mission_mode_state_transition(struct qwx_pci_softc * psc)3124 qwx_mhi_mission_mode_state_transition(struct qwx_pci_softc *psc)
3125 {
3126 struct qwx_softc *sc = &psc->sc_sc;
3127 int i;
3128
3129 qwx_mhi_device_wake(sc);
3130
3131 /* Notify event rings. */
3132 for (i = 0; i < nitems(psc->event_rings); i++) {
3133 struct qwx_pci_event_ring *ring = &psc->event_rings[i];
3134 qwx_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
3135 }
3136
3137 /* TODO: Notify transfer/command rings? */
3138
3139 qwx_mhi_device_zzz(sc);
3140 }
3141
3142 void
qwx_mhi_low_power_mode_state_transition(struct qwx_pci_softc * psc)3143 qwx_mhi_low_power_mode_state_transition(struct qwx_pci_softc *psc)
3144 {
3145 struct qwx_softc *sc = &psc->sc_sc;
3146
3147 qwx_mhi_set_state(sc, MHI_STATE_M2);
3148 }
3149
3150 void
qwx_mhi_set_state(struct qwx_softc * sc,uint32_t state)3151 qwx_mhi_set_state(struct qwx_softc *sc, uint32_t state)
3152 {
3153 uint32_t reg;
3154
3155 reg = qwx_pci_read(sc, MHI_CTRL);
3156
3157 if (state != MHI_STATE_RESET) {
3158 reg &= ~MHI_CTRL_MHISTATE_MASK;
3159 reg |= (state << MHI_CTRL_MHISTATE_SHFT) & MHI_CTRL_MHISTATE_MASK;
3160 } else
3161 reg |= MHI_CTRL_RESET_MASK;
3162
3163 qwx_pci_write(sc, MHI_CTRL, reg);
3164 }
3165
3166 void
qwx_mhi_init_mmio(struct qwx_pci_softc * psc)3167 qwx_mhi_init_mmio(struct qwx_pci_softc *psc)
3168 {
3169 struct qwx_softc *sc = &psc->sc_sc;
3170 uint64_t paddr;
3171 uint32_t reg;
3172 int i;
3173
3174 reg = qwx_pci_read(sc, MHI_CHDBOFF);
3175
3176 /* Set device wake doorbell address. */
3177 psc->wake_db = reg + 8 * MHI_DEV_WAKE_DB;
3178
3179 /* Set doorbell address for each transfer ring. */
3180 for (i = 0; i < nitems(psc->xfer_rings); i++) {
3181 struct qwx_pci_xfer_ring *ring = &psc->xfer_rings[i];
3182 ring->db_addr = reg + (8 * ring->mhi_chan_id);
3183 }
3184
3185 reg = qwx_pci_read(sc, MHI_ERDBOFF);
3186 /* Set doorbell address for each event ring. */
3187 for (i = 0; i < nitems(psc->event_rings); i++) {
3188 struct qwx_pci_event_ring *ring = &psc->event_rings[i];
3189 ring->db_addr = reg + (8 * i);
3190 }
3191
3192 paddr = QWX_DMA_DVA(psc->chan_ctxt);
3193 qwx_pci_write(sc, MHI_CCABAP_HIGHER, paddr >> 32);
3194 qwx_pci_write(sc, MHI_CCABAP_LOWER, paddr & 0xffffffff);
3195
3196 paddr = QWX_DMA_DVA(psc->event_ctxt);
3197 qwx_pci_write(sc, MHI_ECABAP_HIGHER, paddr >> 32);
3198 qwx_pci_write(sc, MHI_ECABAP_LOWER, paddr & 0xffffffff);
3199
3200 paddr = QWX_DMA_DVA(psc->cmd_ctxt);
3201 qwx_pci_write(sc, MHI_CRCBAP_HIGHER, paddr >> 32);
3202 qwx_pci_write(sc, MHI_CRCBAP_LOWER, paddr & 0xffffffff);
3203
3204 /* Not (yet?) using fixed memory space from a device-tree. */
3205 qwx_pci_write(sc, MHI_CTRLBASE_HIGHER, 0);
3206 qwx_pci_write(sc, MHI_CTRLBASE_LOWER, 0);
3207 qwx_pci_write(sc, MHI_DATABASE_HIGHER, 0);
3208 qwx_pci_write(sc, MHI_DATABASE_LOWER, 0);
3209 qwx_pci_write(sc, MHI_CTRLLIMIT_HIGHER, 0x0);
3210 qwx_pci_write(sc, MHI_CTRLLIMIT_LOWER, 0xffffffff);
3211 qwx_pci_write(sc, MHI_DATALIMIT_HIGHER, 0x0);
3212 qwx_pci_write(sc, MHI_DATALIMIT_LOWER, 0xffffffff);
3213
3214 reg = qwx_pci_read(sc, MHI_CFG);
3215 reg &= ~(MHI_CFG_NER_MASK | MHI_CFG_NHWER_MASK);
3216 reg |= QWX_NUM_EVENT_CTX << MHI_CFG_NER_SHFT;
3217 qwx_pci_write(sc, MHI_CFG, reg);
3218 }
3219
3220 int
qwx_mhi_fw_load_bhi(struct qwx_pci_softc * psc,uint8_t * data,size_t len)3221 qwx_mhi_fw_load_bhi(struct qwx_pci_softc *psc, uint8_t *data, size_t len)
3222 {
3223 struct qwx_softc *sc = &psc->sc_sc;
3224 struct qwx_dmamem *data_adm;
3225 uint32_t seq, reg, status = MHI_BHI_STATUS_RESET;
3226 uint64_t paddr;
3227 int ret;
3228
3229 data_adm = qwx_dmamem_alloc(sc->sc_dmat, len, 0);
3230 if (data_adm == NULL) {
3231 printf("%s: could not allocate BHI DMA data buffer\n",
3232 sc->sc_dev.dv_xname);
3233 return 1;
3234 }
3235
3236 /* Copy firmware image to DMA memory. */
3237 memcpy(QWX_DMA_KVA(data_adm), data, len);
3238
3239 qwx_pci_write(sc, psc->bhi_off + MHI_BHI_STATUS, 0);
3240
3241 /* Set data physical address and length. */
3242 paddr = QWX_DMA_DVA(data_adm);
3243 qwx_pci_write(sc, psc->bhi_off + MHI_BHI_IMGADDR_HIGH, paddr >> 32);
3244 qwx_pci_write(sc, psc->bhi_off + MHI_BHI_IMGADDR_LOW,
3245 paddr & 0xffffffff);
3246 qwx_pci_write(sc, psc->bhi_off + MHI_BHI_IMGSIZE, len);
3247
3248 /* Set a random transaction sequence number. */
3249 do {
3250 seq = arc4random_uniform(MHI_BHI_TXDB_SEQNUM_BMSK);
3251 } while (seq == 0);
3252 qwx_pci_write(sc, psc->bhi_off + MHI_BHI_IMGTXDB, seq);
3253
3254 /* Wait for completion. */
3255 ret = 0;
3256 while (status != MHI_BHI_STATUS_SUCCESS && psc->bhi_ee < MHI_EE_SBL) {
3257 ret = tsleep_nsec(&psc->bhi_ee, 0, "qwxbhi", SEC_TO_NSEC(5));
3258 if (ret)
3259 break;
3260 reg = qwx_pci_read(sc, psc->bhi_off + MHI_BHI_STATUS);
3261 status = (reg & MHI_BHI_STATUS_MASK) >> MHI_BHI_STATUS_SHFT;
3262 }
3263
3264 if (ret) {
3265 printf("%s: BHI load timeout\n", sc->sc_dev.dv_xname);
3266 reg = qwx_pci_read(sc, psc->bhi_off + MHI_BHI_STATUS);
3267 status = (reg & MHI_BHI_STATUS_MASK) >> MHI_BHI_STATUS_SHFT;
3268 DNPRINTF(QWX_D_MHI, "%s: BHI status is 0x%x EE is 0x%x\n",
3269 __func__, status, psc->bhi_ee);
3270 }
3271
3272 qwx_dmamem_free(sc->sc_dmat, data_adm);
3273 return ret;
3274 }
3275
3276 int
qwx_mhi_fw_load_bhie(struct qwx_pci_softc * psc,uint8_t * data,size_t len)3277 qwx_mhi_fw_load_bhie(struct qwx_pci_softc *psc, uint8_t *data, size_t len)
3278 {
3279 struct qwx_softc *sc = &psc->sc_sc;
3280 struct qwx_dma_vec_entry *vec;
3281 uint32_t seq, reg, state = MHI_BHIE_TXVECSTATUS_STATUS_RESET;
3282 uint64_t paddr;
3283 const size_t chunk_size = MHI_DMA_VEC_CHUNK_SIZE;
3284 size_t nseg, remain, vec_size;
3285 int i, ret;
3286
3287 nseg = howmany(len, chunk_size);
3288 if (nseg == 0) {
3289 printf("%s: BHIE data too short, have only %zu bytes\n",
3290 sc->sc_dev.dv_xname, len);
3291 return 1;
3292 }
3293
3294 if (psc->amss_data == NULL || QWX_DMA_LEN(psc->amss_data) < len) {
3295 if (psc->amss_data)
3296 qwx_dmamem_free(sc->sc_dmat, psc->amss_data);
3297 psc->amss_data = qwx_dmamem_alloc(sc->sc_dmat, len, 0);
3298 if (psc->amss_data == NULL) {
3299 printf("%s: could not allocate BHIE DMA data buffer\n",
3300 sc->sc_dev.dv_xname);
3301 return 1;
3302 }
3303 }
3304
3305 vec_size = nseg * sizeof(*vec);
3306 if (psc->amss_vec == NULL || QWX_DMA_LEN(psc->amss_vec) < vec_size) {
3307 if (psc->amss_vec)
3308 qwx_dmamem_free(sc->sc_dmat, psc->amss_vec);
3309 psc->amss_vec = qwx_dmamem_alloc(sc->sc_dmat, vec_size, 0);
3310 if (psc->amss_vec == NULL) {
3311 printf("%s: could not allocate BHIE DMA vec buffer\n",
3312 sc->sc_dev.dv_xname);
3313 qwx_dmamem_free(sc->sc_dmat, psc->amss_data);
3314 psc->amss_data = NULL;
3315 return 1;
3316 }
3317 }
3318
3319 /* Copy firmware image to DMA memory. */
3320 memcpy(QWX_DMA_KVA(psc->amss_data), data, len);
3321
3322 /* Create vector which controls chunk-wise DMA copy in hardware. */
3323 paddr = QWX_DMA_DVA(psc->amss_data);
3324 vec = QWX_DMA_KVA(psc->amss_vec);
3325 remain = len;
3326 for (i = 0; i < nseg; i++) {
3327 vec[i].paddr = paddr;
3328 if (remain >= chunk_size) {
3329 vec[i].size = chunk_size;
3330 remain -= chunk_size;
3331 paddr += chunk_size;
3332 } else
3333 vec[i].size = remain;
3334 }
3335
3336 /* Set vector physical address and length. */
3337 paddr = QWX_DMA_DVA(psc->amss_vec);
3338 qwx_pci_write(sc, psc->bhie_off + MHI_BHIE_TXVECADDR_HIGH_OFFS,
3339 paddr >> 32);
3340 qwx_pci_write(sc, psc->bhie_off + MHI_BHIE_TXVECADDR_LOW_OFFS,
3341 paddr & 0xffffffff);
3342 qwx_pci_write(sc, psc->bhie_off + MHI_BHIE_TXVECSIZE_OFFS, vec_size);
3343
3344 /* Set a random transaction sequence number. */
3345 do {
3346 seq = arc4random_uniform(MHI_BHIE_TXVECSTATUS_SEQNUM_BMSK);
3347 } while (seq == 0);
3348 reg = qwx_pci_read(sc, psc->bhie_off + MHI_BHIE_TXVECDB_OFFS);
3349 reg &= ~MHI_BHIE_TXVECDB_SEQNUM_BMSK;
3350 reg |= seq << MHI_BHIE_TXVECDB_SEQNUM_SHFT;
3351 qwx_pci_write(sc, psc->bhie_off + MHI_BHIE_TXVECDB_OFFS, reg);
3352
3353 /* Wait for completion. */
3354 ret = 0;
3355 while (state != MHI_BHIE_TXVECSTATUS_STATUS_XFER_COMPL) {
3356 ret = tsleep_nsec(&psc->bhie_off, 0, "qwxbhie",
3357 SEC_TO_NSEC(5));
3358 if (ret)
3359 break;
3360 reg = qwx_pci_read(sc,
3361 psc->bhie_off + MHI_BHIE_TXVECSTATUS_OFFS);
3362 state = (reg & MHI_BHIE_TXVECSTATUS_STATUS_BMSK) >>
3363 MHI_BHIE_TXVECSTATUS_STATUS_SHFT;
3364 DNPRINTF(QWX_D_MHI, "%s: txvec state is 0x%x\n", __func__,
3365 state);
3366 }
3367
3368 if (ret) {
3369 printf("%s: BHIE load timeout\n", sc->sc_dev.dv_xname);
3370 return ret;
3371 }
3372 return 0;
3373 }
3374
3375 void
qwx_rddm_prepare(struct qwx_pci_softc * psc)3376 qwx_rddm_prepare(struct qwx_pci_softc *psc)
3377 {
3378 struct qwx_softc *sc = &psc->sc_sc;
3379 struct qwx_dma_vec_entry *vec;
3380 struct qwx_dmamem *data_adm, *vec_adm;
3381 uint32_t seq, reg;
3382 uint64_t paddr;
3383 const size_t len = QWX_RDDM_DUMP_SIZE;
3384 const size_t chunk_size = MHI_DMA_VEC_CHUNK_SIZE;
3385 size_t nseg, remain, vec_size;
3386 int i;
3387
3388 nseg = howmany(len, chunk_size);
3389 if (nseg == 0) {
3390 printf("%s: RDDM data too short, have only %zu bytes\n",
3391 sc->sc_dev.dv_xname, len);
3392 return;
3393 }
3394
3395 data_adm = qwx_dmamem_alloc(sc->sc_dmat, len, 0);
3396 if (data_adm == NULL) {
3397 printf("%s: could not allocate BHIE DMA data buffer\n",
3398 sc->sc_dev.dv_xname);
3399 return;
3400 }
3401
3402 vec_size = nseg * sizeof(*vec);
3403 vec_adm = qwx_dmamem_alloc(sc->sc_dmat, vec_size, 0);
3404 if (vec_adm == NULL) {
3405 printf("%s: could not allocate BHIE DMA vector buffer\n",
3406 sc->sc_dev.dv_xname);
3407 qwx_dmamem_free(sc->sc_dmat, data_adm);
3408 return;
3409 }
3410
3411 /* Create vector which controls chunk-wise DMA copy from hardware. */
3412 paddr = QWX_DMA_DVA(data_adm);
3413 vec = QWX_DMA_KVA(vec_adm);
3414 remain = len;
3415 for (i = 0; i < nseg; i++) {
3416 vec[i].paddr = paddr;
3417 if (remain >= chunk_size) {
3418 vec[i].size = chunk_size;
3419 remain -= chunk_size;
3420 paddr += chunk_size;
3421 } else
3422 vec[i].size = remain;
3423 }
3424
3425 /* Set vector physical address and length. */
3426 paddr = QWX_DMA_DVA(vec_adm);
3427 qwx_pci_write(sc, psc->bhie_off + MHI_BHIE_RXVECADDR_HIGH_OFFS,
3428 paddr >> 32);
3429 qwx_pci_write(sc, psc->bhie_off + MHI_BHIE_RXVECADDR_LOW_OFFS,
3430 paddr & 0xffffffff);
3431 qwx_pci_write(sc, psc->bhie_off + MHI_BHIE_RXVECSIZE_OFFS, vec_size);
3432
3433 /* Set a random transaction sequence number. */
3434 do {
3435 seq = arc4random_uniform(MHI_BHIE_RXVECSTATUS_SEQNUM_BMSK);
3436 } while (seq == 0);
3437
3438 reg = qwx_pci_read(sc, psc->bhie_off + MHI_BHIE_RXVECDB_OFFS);
3439 reg &= ~MHI_BHIE_RXVECDB_SEQNUM_BMSK;
3440 reg |= seq << MHI_BHIE_RXVECDB_SEQNUM_SHFT;
3441 qwx_pci_write(sc, psc->bhie_off + MHI_BHIE_RXVECDB_OFFS, reg);
3442
3443 psc->rddm_data = data_adm;
3444 psc->rddm_vec = vec_adm;
3445 }
3446
3447 #ifdef QWX_DEBUG
3448 void
qwx_rddm_task(void * arg)3449 qwx_rddm_task(void *arg)
3450 {
3451 struct qwx_pci_softc *psc = arg;
3452 struct qwx_softc *sc = &psc->sc_sc;
3453 uint32_t reg, state = MHI_BHIE_RXVECSTATUS_STATUS_RESET;
3454 const size_t len = QWX_RDDM_DUMP_SIZE;
3455 int i, timeout;
3456 const uint32_t msecs = 100, retries = 20;
3457 uint8_t *rddm;
3458 struct nameidata nd;
3459 struct vnode *vp = NULL;
3460 struct iovec iov[3];
3461 struct uio uio;
3462 char path[PATH_MAX];
3463 int error = 0;
3464
3465 if (psc->rddm_data == NULL) {
3466 DPRINTF("%s: RDDM not prepared\n", __func__);
3467 return;
3468 }
3469
3470 /* Poll for completion */
3471 timeout = retries;
3472 while (timeout > 0 && state != MHI_BHIE_RXVECSTATUS_STATUS_XFER_COMPL) {
3473 reg = qwx_pci_read(sc,
3474 psc->bhie_off + MHI_BHIE_RXVECSTATUS_OFFS);
3475 state = (reg & MHI_BHIE_RXVECSTATUS_STATUS_BMSK) >>
3476 MHI_BHIE_RXVECSTATUS_STATUS_SHFT;
3477 DPRINTF("%s: txvec state is 0x%x\n", __func__, state);
3478 DELAY((msecs / retries) * 1000);
3479 timeout--;
3480 }
3481
3482 if (timeout == 0) {
3483 DPRINTF("%s: RDDM dump failed\n", sc->sc_dev.dv_xname);
3484 return;
3485 }
3486
3487 rddm = QWX_DMA_KVA(psc->rddm_data);
3488 DPRINTF("%s: RDDM snippet:\n", __func__);
3489 for (i = 0; i < MIN(64, len); i++) {
3490 DPRINTF("%s %.2x", i % 16 == 0 ? "\n" : "", rddm[i]);
3491 }
3492 DPRINTF("\n");
3493
3494 DPRINTF("%s: sleeping for 30 seconds to allow userland to boot\n", __func__);
3495 tsleep_nsec(&psc->rddm_data, 0, "qwxrddm", SEC_TO_NSEC(30));
3496
3497 snprintf(path, sizeof(path), "/root/%s-rddm.bin", sc->sc_dev.dv_xname);
3498 DPRINTF("%s: saving RDDM to %s\n", __func__, path);
3499 NDINIT(&nd, 0, 0, UIO_SYSSPACE, path, curproc);
3500 nd.ni_pledge = PLEDGE_CPATH | PLEDGE_WPATH;
3501 nd.ni_unveil = UNVEIL_CREATE | UNVEIL_WRITE;
3502 error = vn_open(&nd, FWRITE | O_CREAT | O_NOFOLLOW | O_TRUNC,
3503 S_IRUSR | S_IWUSR);
3504 if (error) {
3505 DPRINTF("%s: vn_open: error %d\n", __func__, error);
3506 goto done;
3507 }
3508 vp = nd.ni_vp;
3509 VOP_UNLOCK(vp);
3510
3511 iov[0].iov_base = (void *)rddm;
3512 iov[0].iov_len = len;
3513 iov[1].iov_len = 0;
3514 uio.uio_iov = &iov[0];
3515 uio.uio_offset = 0;
3516 uio.uio_segflg = UIO_SYSSPACE;
3517 uio.uio_rw = UIO_WRITE;
3518 uio.uio_resid = len;
3519 uio.uio_iovcnt = 1;
3520 uio.uio_procp = curproc;
3521 error = vget(vp, LK_EXCLUSIVE | LK_RETRY);
3522 if (error) {
3523 DPRINTF("%s: vget: error %d\n", __func__, error);
3524 goto done;
3525 }
3526 error = VOP_WRITE(vp, &uio, IO_UNIT|IO_APPEND, curproc->p_ucred);
3527 vput(vp);
3528 if (error)
3529 DPRINTF("%s: VOP_WRITE: error %d\n", __func__, error);
3530 #if 0
3531 error = vn_close(vp, FWRITE, curproc->p_ucred, curproc);
3532 if (error)
3533 DPRINTF("%s: vn_close: error %d\n", __func__, error);
3534 #endif
3535 done:
3536 qwx_dmamem_free(sc->sc_dmat, psc->rddm_data);
3537 qwx_dmamem_free(sc->sc_dmat, psc->rddm_vec);
3538 psc->rddm_data = NULL;
3539 psc->rddm_vec = NULL;
3540 DPRINTF("%s: done, error %d\n", __func__, error);
3541 }
3542 #endif
3543
3544 void *
qwx_pci_event_ring_get_elem(struct qwx_pci_event_ring * ring,uint64_t rp)3545 qwx_pci_event_ring_get_elem(struct qwx_pci_event_ring *ring, uint64_t rp)
3546 {
3547 uint64_t base = QWX_DMA_DVA(ring->dmamem), offset;
3548 void *addr = QWX_DMA_KVA(ring->dmamem);
3549
3550 if (rp < base)
3551 return NULL;
3552
3553 offset = rp - base;
3554 if (offset >= ring->size)
3555 return NULL;
3556
3557 return addr + offset;
3558 }
3559
3560 void
qwx_mhi_state_change(struct qwx_pci_softc * psc,int ee,int mhi_state)3561 qwx_mhi_state_change(struct qwx_pci_softc *psc, int ee, int mhi_state)
3562 {
3563 struct qwx_softc *sc = &psc->sc_sc;
3564 uint32_t old_ee = psc->bhi_ee;
3565 uint32_t old_mhi_state = psc->mhi_state;
3566
3567 if (ee != -1 && psc->bhi_ee != ee) {
3568 switch (ee) {
3569 case MHI_EE_PBL:
3570 DNPRINTF(QWX_D_MHI, "%s: new EE PBL\n",
3571 sc->sc_dev.dv_xname);
3572 psc->bhi_ee = ee;
3573 break;
3574 case MHI_EE_SBL:
3575 psc->bhi_ee = ee;
3576 DNPRINTF(QWX_D_MHI, "%s: new EE SBL\n",
3577 sc->sc_dev.dv_xname);
3578 break;
3579 case MHI_EE_AMSS:
3580 DNPRINTF(QWX_D_MHI, "%s: new EE AMSS\n",
3581 sc->sc_dev.dv_xname);
3582 psc->bhi_ee = ee;
3583 /* Wake thread loading the full AMSS image. */
3584 wakeup(&psc->bhie_off);
3585 break;
3586 case MHI_EE_WFW:
3587 DNPRINTF(QWX_D_MHI, "%s: new EE WFW\n",
3588 sc->sc_dev.dv_xname);
3589 psc->bhi_ee = ee;
3590 break;
3591 default:
3592 printf("%s: unhandled EE change to %x\n",
3593 sc->sc_dev.dv_xname, ee);
3594 break;
3595 }
3596 }
3597
3598 if (mhi_state != -1 && psc->mhi_state != mhi_state) {
3599 switch (mhi_state) {
3600 case -1:
3601 break;
3602 case MHI_STATE_RESET:
3603 DNPRINTF(QWX_D_MHI, "%s: new MHI state RESET\n",
3604 sc->sc_dev.dv_xname);
3605 psc->mhi_state = mhi_state;
3606 break;
3607 case MHI_STATE_READY:
3608 DNPRINTF(QWX_D_MHI, "%s: new MHI state READY\n",
3609 sc->sc_dev.dv_xname);
3610 psc->mhi_state = mhi_state;
3611 qwx_mhi_ready_state_transition(psc);
3612 break;
3613 case MHI_STATE_M0:
3614 DNPRINTF(QWX_D_MHI, "%s: new MHI state M0\n",
3615 sc->sc_dev.dv_xname);
3616 psc->mhi_state = mhi_state;
3617 qwx_mhi_mission_mode_state_transition(psc);
3618 break;
3619 case MHI_STATE_M1:
3620 DNPRINTF(QWX_D_MHI, "%s: new MHI state M1\n",
3621 sc->sc_dev.dv_xname);
3622 psc->mhi_state = mhi_state;
3623 qwx_mhi_low_power_mode_state_transition(psc);
3624 break;
3625 case MHI_STATE_SYS_ERR:
3626 DNPRINTF(QWX_D_MHI,
3627 "%s: new MHI state SYS ERR\n",
3628 sc->sc_dev.dv_xname);
3629 psc->mhi_state = mhi_state;
3630 break;
3631 default:
3632 printf("%s: unhandled MHI state change to %x\n",
3633 sc->sc_dev.dv_xname, mhi_state);
3634 break;
3635 }
3636 }
3637
3638 if (old_ee != psc->bhi_ee)
3639 wakeup(&psc->bhi_ee);
3640 if (old_mhi_state != psc->mhi_state)
3641 wakeup(&psc->mhi_state);
3642 }
3643
3644 void
qwx_pci_intr_ctrl_event_mhi(struct qwx_pci_softc * psc,uint32_t mhi_state)3645 qwx_pci_intr_ctrl_event_mhi(struct qwx_pci_softc *psc, uint32_t mhi_state)
3646 {
3647 DNPRINTF(QWX_D_MHI, "%s: MHI state change 0x%x -> 0x%x\n", __func__,
3648 psc->mhi_state, mhi_state);
3649
3650 if (psc->mhi_state != mhi_state)
3651 qwx_mhi_state_change(psc, -1, mhi_state);
3652 }
3653
3654 void
qwx_pci_intr_ctrl_event_ee(struct qwx_pci_softc * psc,uint32_t ee)3655 qwx_pci_intr_ctrl_event_ee(struct qwx_pci_softc *psc, uint32_t ee)
3656 {
3657 DNPRINTF(QWX_D_MHI, "%s: EE change 0x%x to 0x%x\n", __func__,
3658 psc->bhi_ee, ee);
3659
3660 if (psc->bhi_ee != ee)
3661 qwx_mhi_state_change(psc, ee, -1);
3662 }
3663
3664 void
qwx_pci_intr_ctrl_event_cmd_complete(struct qwx_pci_softc * psc,uint64_t ptr,uint32_t cmd_status)3665 qwx_pci_intr_ctrl_event_cmd_complete(struct qwx_pci_softc *psc,
3666 uint64_t ptr, uint32_t cmd_status)
3667 {
3668 struct qwx_pci_cmd_ring *cmd_ring = &psc->cmd_ring;
3669 uint64_t base = QWX_DMA_DVA(cmd_ring->dmamem);
3670 struct qwx_pci_xfer_ring *xfer_ring = NULL;
3671 struct qwx_mhi_ring_element *e;
3672 uint32_t tre1, chid;
3673 size_t i;
3674
3675 e = qwx_pci_cmd_ring_get_elem(cmd_ring, ptr);
3676 if (e == NULL)
3677 return;
3678
3679 tre1 = le32toh(e->dword[1]);
3680 chid = (tre1 & MHI_TRE1_EV_CHID_MASK) >> MHI_TRE1_EV_CHID_SHFT;
3681
3682 for (i = 0; i < nitems(psc->xfer_rings); i++) {
3683 if (psc->xfer_rings[i].mhi_chan_id == chid) {
3684 xfer_ring = &psc->xfer_rings[i];
3685 break;
3686 }
3687 }
3688 if (xfer_ring == NULL) {
3689 printf("%s: no transfer ring found for command completion "
3690 "on channel %u\n", __func__, chid);
3691 return;
3692 }
3693
3694 xfer_ring->cmd_status = cmd_status;
3695 wakeup(&xfer_ring->cmd_status);
3696
3697 if (cmd_ring->rp + sizeof(*e) >= base + cmd_ring->size)
3698 cmd_ring->rp = base;
3699 else
3700 cmd_ring->rp += sizeof(*e);
3701 }
3702
3703 int
qwx_pci_intr_ctrl_event(struct qwx_pci_softc * psc,struct qwx_pci_event_ring * ring)3704 qwx_pci_intr_ctrl_event(struct qwx_pci_softc *psc, struct qwx_pci_event_ring *ring)
3705 {
3706 struct qwx_softc *sc = &psc->sc_sc;
3707 struct qwx_mhi_event_ctxt *c;
3708 uint64_t rp, wp, base;
3709 struct qwx_mhi_ring_element *e;
3710 uint32_t tre0, tre1, type, code, chid, len;
3711
3712 c = ring->event_ctxt;
3713 if (c == NULL) {
3714 /*
3715 * Interrupts can trigger before mhi_init_event_rings()
3716 * if the device is still active after a warm reboot.
3717 */
3718 return 0;
3719 }
3720
3721 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(psc->event_ctxt), 0,
3722 QWX_DMA_LEN(psc->event_ctxt), BUS_DMASYNC_POSTREAD);
3723
3724 rp = le64toh(c->rp);
3725 wp = le64toh(c->wp);
3726
3727 DNPRINTF(QWX_D_MHI, "%s: kernel rp=0x%llx\n", __func__, ring->rp);
3728 DNPRINTF(QWX_D_MHI, "%s: device rp=0x%llx\n", __func__, rp);
3729 DNPRINTF(QWX_D_MHI, "%s: kernel wp=0x%llx\n", __func__, ring->wp);
3730 DNPRINTF(QWX_D_MHI, "%s: device wp=0x%llx\n", __func__, wp);
3731
3732 base = QWX_DMA_DVA(ring->dmamem);
3733 if (ring->rp == rp || rp < base || rp >= base + ring->size)
3734 return 0;
3735 if (wp < base || wp >= base + ring->size)
3736 return 0;
3737
3738 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(ring->dmamem),
3739 0, QWX_DMA_LEN(ring->dmamem), BUS_DMASYNC_POSTREAD);
3740
3741 while (ring->rp != rp) {
3742 e = qwx_pci_event_ring_get_elem(ring, ring->rp);
3743 if (e == NULL)
3744 return 0;
3745
3746 tre0 = le32toh(e->dword[0]);
3747 tre1 = le32toh(e->dword[1]);
3748
3749 len = (tre0 & MHI_TRE0_EV_LEN_MASK) >> MHI_TRE0_EV_LEN_SHFT;
3750 code = (tre0 & MHI_TRE0_EV_CODE_MASK) >> MHI_TRE0_EV_CODE_SHFT;
3751 type = (tre1 & MHI_TRE1_EV_TYPE_MASK) >> MHI_TRE1_EV_TYPE_SHFT;
3752 chid = (tre1 & MHI_TRE1_EV_CHID_MASK) >> MHI_TRE1_EV_CHID_SHFT;
3753 DNPRINTF(QWX_D_MHI, "%s: len=%u code=0x%x type=0x%x chid=%d\n",
3754 __func__, len, code, type, chid);
3755
3756 switch (type) {
3757 case MHI_PKT_TYPE_STATE_CHANGE_EVENT:
3758 qwx_pci_intr_ctrl_event_mhi(psc, code);
3759 break;
3760 case MHI_PKT_TYPE_EE_EVENT:
3761 qwx_pci_intr_ctrl_event_ee(psc, code);
3762 break;
3763 case MHI_PKT_TYPE_CMD_COMPLETION_EVENT:
3764 qwx_pci_intr_ctrl_event_cmd_complete(psc,
3765 le64toh(e->ptr), code);
3766 break;
3767 default:
3768 printf("%s: unhandled event type 0x%x\n",
3769 __func__, type);
3770 break;
3771 }
3772
3773 if (ring->rp + sizeof(*e) >= base + ring->size)
3774 ring->rp = base;
3775 else
3776 ring->rp += sizeof(*e);
3777
3778 if (ring->wp + sizeof(*e) >= base + ring->size)
3779 ring->wp = base;
3780 else
3781 ring->wp += sizeof(*e);
3782 }
3783
3784 c->wp = htole64(ring->wp);
3785
3786 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(psc->event_ctxt), 0,
3787 QWX_DMA_LEN(psc->event_ctxt), BUS_DMASYNC_PREWRITE);
3788
3789 qwx_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
3790 return 1;
3791 }
3792
3793 void
qwx_pci_intr_data_event_tx(struct qwx_pci_softc * psc,struct qwx_mhi_ring_element * e)3794 qwx_pci_intr_data_event_tx(struct qwx_pci_softc *psc, struct qwx_mhi_ring_element *e)
3795 {
3796 struct qwx_softc *sc = &psc->sc_sc;
3797 struct qwx_pci_xfer_ring *ring;
3798 struct qwx_xfer_data *xfer;
3799 uint64_t rp, evrp, base, paddr;
3800 uint32_t tre0, tre1, code, chid, evlen, len;
3801 int i;
3802
3803 tre0 = le32toh(e->dword[0]);
3804 tre1 = le32toh(e->dword[1]);
3805
3806 evlen = (tre0 & MHI_TRE0_EV_LEN_MASK) >> MHI_TRE0_EV_LEN_SHFT;
3807 code = (tre0 & MHI_TRE0_EV_CODE_MASK) >> MHI_TRE0_EV_CODE_SHFT;
3808 chid = (tre1 & MHI_TRE1_EV_CHID_MASK) >> MHI_TRE1_EV_CHID_SHFT;
3809
3810 switch (code) {
3811 case MHI_EV_CC_EOT:
3812 for (i = 0; i < nitems(psc->xfer_rings); i++) {
3813 ring = &psc->xfer_rings[i];
3814 if (ring->mhi_chan_id == chid)
3815 break;
3816 }
3817 if (i == nitems(psc->xfer_rings)) {
3818 printf("%s: unhandled channel 0x%x\n",
3819 __func__, chid);
3820 break;
3821 }
3822 base = QWX_DMA_DVA(ring->dmamem);
3823 /* PTR contains the entry that was last written */
3824 evrp = letoh64(e->ptr);
3825 rp = evrp;
3826 if (rp < base || rp >= base + ring->size) {
3827 printf("%s: invalid ptr 0x%llx\n",
3828 __func__, rp);
3829 break;
3830 }
3831 /* Point rp to next empty slot */
3832 if (rp + sizeof(*e) >= base + ring->size)
3833 rp = base;
3834 else
3835 rp += sizeof(*e);
3836 /* Parse until next empty slot */
3837 while (ring->rp != rp) {
3838 DNPRINTF(QWX_D_MHI, "%s:%d: ring->rp 0x%llx "
3839 "ring->wp 0x%llx rp 0x%llx\n", __func__,
3840 __LINE__, ring->rp, ring->wp, rp);
3841 e = qwx_pci_xfer_ring_get_elem(ring, ring->rp);
3842 xfer = qwx_pci_xfer_ring_get_data(ring, ring->rp);
3843
3844 if (ring->rp == evrp)
3845 len = evlen;
3846 else
3847 len = xfer->m->m_pkthdr.len;
3848
3849 bus_dmamap_sync(sc->sc_dmat, xfer->map, 0,
3850 xfer->m->m_pkthdr.len, BUS_DMASYNC_POSTREAD);
3851 #ifdef QWX_DEBUG
3852 {
3853 int i;
3854 DNPRINTF(QWX_D_MHI, "%s: chan %u data (len %u): ",
3855 __func__,
3856 ring->mhi_chan_id, len);
3857 for (i = 0; i < MIN(32, len); i++) {
3858 DNPRINTF(QWX_D_MHI, "%02x ",
3859 (unsigned char)mtod(xfer->m, caddr_t)[i]);
3860 }
3861 if (i < len)
3862 DNPRINTF(QWX_D_MHI, "...");
3863 DNPRINTF(QWX_D_MHI, "\n");
3864 }
3865 #endif
3866 if (ring->mhi_chan_direction == MHI_CHAN_TYPE_INBOUND) {
3867 /* Save m_data as upper layers use m_adj(9) */
3868 void *o_data = xfer->m->m_data;
3869
3870 /* Pass mbuf to upper layers */
3871 qwx_qrtr_recv_msg(sc, xfer->m);
3872
3873 /* Reset RX mbuf instead of free/alloc */
3874 KASSERT(xfer->m->m_next == NULL);
3875 xfer->m->m_data = o_data;
3876 xfer->m->m_len = xfer->m->m_pkthdr.len =
3877 QWX_PCI_XFER_MAX_DATA_SIZE;
3878
3879 paddr = xfer->map->dm_segs[0].ds_addr;
3880
3881 e->ptr = htole64(paddr);
3882 e->dword[0] = htole32((
3883 QWX_PCI_XFER_MAX_DATA_SIZE <<
3884 MHI_TRE0_DATA_LEN_SHFT) &
3885 MHI_TRE0_DATA_LEN_MASK);
3886 e->dword[1] = htole32(MHI_TRE1_DATA_IEOT |
3887 MHI_TRE1_DATA_BEI |
3888 MHI_TRE1_DATA_TYPE_TRANSFER <<
3889 MHI_TRE1_DATA_TYPE_SHIFT);
3890
3891 if (ring->wp + sizeof(*e) >= base + ring->size)
3892 ring->wp = base;
3893 else
3894 ring->wp += sizeof(*e);
3895 } else {
3896 /* Unload and free TX mbuf */
3897 bus_dmamap_unload(sc->sc_dmat, xfer->map);
3898 m_freem(xfer->m);
3899 xfer->m = NULL;
3900 ring->queued--;
3901 }
3902
3903 if (ring->rp + sizeof(*e) >= base + ring->size)
3904 ring->rp = base;
3905 else
3906 ring->rp += sizeof(*e);
3907 }
3908
3909 if (ring->mhi_chan_direction == MHI_CHAN_TYPE_INBOUND) {
3910 ring->chan_ctxt->wp = htole64(ring->wp);
3911
3912 bus_dmamap_sync(sc->sc_dmat,
3913 QWX_DMA_MAP(psc->chan_ctxt), 0,
3914 QWX_DMA_LEN(psc->chan_ctxt),
3915 BUS_DMASYNC_PREWRITE);
3916
3917 qwx_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
3918 }
3919 break;
3920 default:
3921 printf("%s: unhandled event code 0x%x\n",
3922 __func__, code);
3923 }
3924 }
3925
3926 int
qwx_pci_intr_data_event(struct qwx_pci_softc * psc,struct qwx_pci_event_ring * ring)3927 qwx_pci_intr_data_event(struct qwx_pci_softc *psc, struct qwx_pci_event_ring *ring)
3928 {
3929 struct qwx_softc *sc = &psc->sc_sc;
3930 struct qwx_mhi_event_ctxt *c;
3931 uint64_t rp, wp, base;
3932 struct qwx_mhi_ring_element *e;
3933 uint32_t tre0, tre1, type, code, chid, len;
3934
3935 c = ring->event_ctxt;
3936 if (c == NULL) {
3937 /*
3938 * Interrupts can trigger before mhi_init_event_rings()
3939 * if the device is still active after a warm reboot.
3940 */
3941 return 0;
3942 }
3943
3944 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(psc->event_ctxt), 0,
3945 QWX_DMA_LEN(psc->event_ctxt), BUS_DMASYNC_POSTREAD);
3946
3947 rp = le64toh(c->rp);
3948 wp = le64toh(c->wp);
3949
3950 DNPRINTF(QWX_D_MHI, "%s: kernel rp=0x%llx\n", __func__, ring->rp);
3951 DNPRINTF(QWX_D_MHI, "%s: device rp=0x%llx\n", __func__, rp);
3952 DNPRINTF(QWX_D_MHI, "%s: kernel wp=0x%llx\n", __func__, ring->wp);
3953 DNPRINTF(QWX_D_MHI, "%s: device wp=0x%llx\n", __func__, wp);
3954
3955 base = QWX_DMA_DVA(ring->dmamem);
3956 if (ring->rp == rp || rp < base || rp >= base + ring->size)
3957 return 0;
3958
3959 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(ring->dmamem),
3960 0, QWX_DMA_LEN(ring->dmamem), BUS_DMASYNC_POSTREAD);
3961
3962 while (ring->rp != rp) {
3963 e = qwx_pci_event_ring_get_elem(ring, ring->rp);
3964 if (e == NULL)
3965 return 0;
3966
3967 tre0 = le32toh(e->dword[0]);
3968 tre1 = le32toh(e->dword[1]);
3969
3970 len = (tre0 & MHI_TRE0_EV_LEN_MASK) >> MHI_TRE0_EV_LEN_SHFT;
3971 code = (tre0 & MHI_TRE0_EV_CODE_MASK) >> MHI_TRE0_EV_CODE_SHFT;
3972 type = (tre1 & MHI_TRE1_EV_TYPE_MASK) >> MHI_TRE1_EV_TYPE_SHFT;
3973 chid = (tre1 & MHI_TRE1_EV_CHID_MASK) >> MHI_TRE1_EV_CHID_SHFT;
3974 DNPRINTF(QWX_D_MHI, "%s: len=%u code=0x%x type=0x%x chid=%d\n",
3975 __func__, len, code, type, chid);
3976
3977 switch (type) {
3978 case MHI_PKT_TYPE_TX_EVENT:
3979 qwx_pci_intr_data_event_tx(psc, e);
3980 break;
3981 default:
3982 printf("%s: unhandled event type 0x%x\n",
3983 __func__, type);
3984 break;
3985 }
3986
3987 if (ring->rp + sizeof(*e) >= base + ring->size)
3988 ring->rp = base;
3989 else
3990 ring->rp += sizeof(*e);
3991
3992 if (ring->wp + sizeof(*e) >= base + ring->size)
3993 ring->wp = base;
3994 else
3995 ring->wp += sizeof(*e);
3996 }
3997
3998 c->wp = htole64(ring->wp);
3999
4000 bus_dmamap_sync(sc->sc_dmat, QWX_DMA_MAP(psc->event_ctxt), 0,
4001 QWX_DMA_LEN(psc->event_ctxt), BUS_DMASYNC_PREWRITE);
4002
4003 qwx_mhi_ring_doorbell(sc, ring->db_addr, ring->wp);
4004 return 1;
4005 }
4006
4007 int
qwx_pci_intr_mhi_ctrl(void * arg)4008 qwx_pci_intr_mhi_ctrl(void *arg)
4009 {
4010 struct qwx_pci_softc *psc = arg;
4011
4012 if (qwx_pci_intr_ctrl_event(psc, &psc->event_rings[0]))
4013 return 1;
4014
4015 return 0;
4016 }
4017
4018 int
qwx_pci_intr_mhi_data(void * arg)4019 qwx_pci_intr_mhi_data(void *arg)
4020 {
4021 struct qwx_pci_softc *psc = arg;
4022
4023 if (qwx_pci_intr_data_event(psc, &psc->event_rings[1]))
4024 return 1;
4025
4026 return 0;
4027 }
4028
4029 int
qwx_pci_intr(void * arg)4030 qwx_pci_intr(void *arg)
4031 {
4032 struct qwx_pci_softc *psc = arg;
4033 struct qwx_softc *sc = (void *)psc;
4034 uint32_t ee, state;
4035 int ret = 0;
4036
4037 /*
4038 * Interrupts can trigger before mhi_start() during boot if the device
4039 * is still active after a warm reboot.
4040 */
4041 if (psc->bhi_off == 0)
4042 psc->bhi_off = qwx_pci_read(sc, MHI_BHI_OFFSET);
4043
4044 ee = qwx_pci_read(sc, psc->bhi_off + MHI_BHI_EXECENV);
4045 state = qwx_pci_read(sc, MHI_STATUS);
4046 state = (state & MHI_STATUS_MHISTATE_MASK) >>
4047 MHI_STATUS_MHISTATE_SHFT;
4048
4049 DNPRINTF(QWX_D_MHI,
4050 "%s: BHI interrupt with EE: 0x%x -> 0x%x state: 0x%x -> 0x%x\n",
4051 sc->sc_dev.dv_xname, psc->bhi_ee, ee, psc->mhi_state, state);
4052
4053 if (ee == MHI_EE_RDDM) {
4054 /* Firmware crash, e.g. due to invalid DMA memory access. */
4055 psc->bhi_ee = ee;
4056 #ifdef QWX_DEBUG
4057 if (!psc->rddm_triggered) {
4058 /* Write fw memory dump to root's home directory. */
4059 task_add(systq, &psc->rddm_task);
4060 psc->rddm_triggered = 1;
4061 }
4062 #else
4063 printf("%s: fatal firmware error\n",
4064 sc->sc_dev.dv_xname);
4065 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, sc->sc_flags) &&
4066 (sc->sc_ic.ic_if.if_flags & (IFF_UP | IFF_RUNNING)) ==
4067 (IFF_UP | IFF_RUNNING)) {
4068 /* Try to reset the device. */
4069 set_bit(ATH11K_FLAG_CRASH_FLUSH, sc->sc_flags);
4070 task_add(systq, &sc->init_task);
4071 }
4072 #endif
4073 return 1;
4074 } else if (psc->bhi_ee == MHI_EE_PBL || psc->bhi_ee == MHI_EE_SBL) {
4075 int new_ee = -1, new_mhi_state = -1;
4076
4077 if (psc->bhi_ee != ee)
4078 new_ee = ee;
4079
4080 if (psc->mhi_state != state)
4081 new_mhi_state = state;
4082
4083 if (new_ee != -1 || new_mhi_state != -1)
4084 qwx_mhi_state_change(psc, new_ee, new_mhi_state);
4085
4086 ret = 1;
4087 }
4088
4089 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags)) {
4090 int i;
4091
4092 if (qwx_pci_intr_ctrl_event(psc, &psc->event_rings[0]))
4093 ret = 1;
4094 if (qwx_pci_intr_data_event(psc, &psc->event_rings[1]))
4095 ret = 1;
4096
4097 for (i = 0; i < sc->hw_params.ce_count; i++) {
4098 struct qwx_ce_pipe *ce_pipe = &sc->ce.ce_pipe[i];
4099
4100 if (qwx_ce_intr(ce_pipe))
4101 ret = 1;
4102 }
4103
4104 if (test_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, sc->sc_flags)) {
4105 for (i = 0; i < nitems(sc->ext_irq_grp); i++) {
4106 if (qwx_dp_service_srng(sc, i))
4107 ret = 1;
4108 }
4109 }
4110 }
4111
4112 return ret;
4113 }
4114