| /openbsd/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 37 class MCInstrDesc; variable
358 const MCInstrDesc &MCID) { in BuildMI()
428 const MCInstrDesc &MCID) { in BuildMI()
438 const MCInstrDesc &MCID) { in BuildMI()
447 const MCInstrDesc &MCID) { in BuildMI()
457 const MCInstrDesc &MCID) { in BuildMI()
465 const MCInstrDesc &MCID) { in BuildMI()
483 const MCInstrDesc &MCID, bool IsIndirect,
490 const MCInstrDesc &MCID, bool IsIndirect,
499 const MCInstrDesc &MCID, bool IsIndirect,
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| H A D | DFAPacketizer.h | 44 class MCInstrDesc; variable
78 bool canReserveResources(const MCInstrDesc *MID);
82 void reserveResources(const MCInstrDesc *MID);
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.h | 25 class MCInstrDesc; variable
52 const MCInstrDesc &II,
67 const MCInstrDesc *II,
78 const MCInstrDesc *II,
111 const MCInstrDesc &DbgValDesc,
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| H A D | InstrEmitter.cpp | 188 const MCInstrDesc &II, in CreateVirtualRegisters()
296 const MCInstrDesc *II, in AddRegisterOperand()
305 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
374 const MCInstrDesc *II, in AddOperand()
635 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
729 MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, in AddDbgValueLocationOps()
898 const MCInstrDesc &Desc = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgNoLocation()
924 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgValueFromSingleOp()
960 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL); in EmitDbgLabel()
999 const MCInstrDesc &II = TII->get(Opc); in EmitMachineNode()
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| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCHazardRecognizers.cpp | 29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore()
39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
55 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet()
65 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isBCTRAfterSet()
85 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, in mustComeFirst()
147 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in ShouldPreferAnother()
175 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode); in GetInstrType()
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| H A D | PPCExpandAtomicPseudoInsts.cpp | 55 const MCInstrDesc &OR = TII->get(PPC::OR8); in PairedCopy()
56 const MCInstrDesc &XOR = TII->get(PPC::XOR8); in PairedCopy()
122 const MCInstrDesc &LL = TII->get(PPC::LQARX); in expandAtomicRMW128()
123 const MCInstrDesc &SC = TII->get(PPC::STQCX); in expandAtomicRMW128()
221 const MCInstrDesc &LL = TII->get(PPC::LQARX); in expandAtomicCmpSwap128()
222 const MCInstrDesc &SC = TII->get(PPC::STQCX); in expandAtomicCmpSwap128()
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| H A D | PPCFrameLowering.cpp | 659 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 in emitPrologue()
661 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD in emitPrologue()
663 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU in emitPrologue()
667 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 in emitPrologue()
676 const MCInstrDesc &HashST = in emitPrologue()
1578 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 in emitEpilogue()
1580 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD in emitEpilogue()
1584 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 in emitEpilogue()
1586 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 in emitEpilogue()
1590 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 in emitEpilogue()
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| /openbsd/gnu/llvm/llvm/include/llvm/MC/ |
| H A D | MCInstrInfo.h | 33 const MCInstrDesc *LastDesc; // Raw array to allow static init'n
48 void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, in InitMCInstrInfo()
63 const MCInstrDesc &get(unsigned Opcode) const { in get()
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| /openbsd/gnu/llvm/llvm/lib/MC/ |
| H A D | MCInstrDesc.cpp | 20 bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI, in mayAffectControlFlow()
32 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg, in hasImplicitDefOfPhysReg()
40 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg, in hasDefOfPhysReg()
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| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 563 ComponentProps(const MCInstrDesc &OpDesc);
707 ComponentInfo(const MCInstrDesc &OpDesc,
712 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps) in ComponentInfo()
728 InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY) in InstInfo()
767 VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
1148 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
1151 bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
1154 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1157 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
1166 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 171 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); in isPredicated()
177 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); in isCPSRDefined()
187 uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc, in evaluateBranchTarget()
420 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); in evaluateBranch()
443 evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode_i12()
461 evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode3()
481 evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode5()
500 evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode5FP16()
541 evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrModeT2_pc()
557 evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrModeT1_s()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 57 bool DFAPacketizer::canReserveResources(const MCInstrDesc *MID) { in canReserveResources()
66 void DFAPacketizer::reserveResources(const MCInstrDesc *MID) { in reserveResources()
76 const MCInstrDesc &MID = MI.getDesc(); in canReserveResources()
83 const MCInstrDesc &MID = MI.getDesc(); in reserveResources()
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| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 160 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
161 SmallVectorImpl<const MCInstrDesc*> &ReplInstrMCID);
218 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc, in shouldReplaceInst()
219 SmallVectorImpl<const MCInstrDesc*> &InstDescRepl) { in shouldReplaceInst()
275 const MCInstrDesc* OriginalMCID; in shouldExitEarly()
276 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID; in shouldExitEarly()
354 const MCInstrDesc *MulMCID, *DupMCID; in optimizeVectElement()
420 SmallVector<const MCInstrDesc*, 2> ReplInstrMCID; in optimizeVectElement()
513 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID; in optimizeLdStInterleave()
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| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ReturnThunks.cpp | 81 const MCInstrDesc &CS = ST.getInstrInfo()->get(X86::CS_PREFIX); in runOnMachineFunction()
82 const MCInstrDesc &JMP = ST.getInstrInfo()->get(X86::TAILJMPd); in runOnMachineFunction()
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| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.h | 179 static inline unsigned getMergeOpNum(const MCInstrDesc &Desc) { in getMergeOpNum()
185 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) { in getVLOpNum()
196 static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) { in getSEWOpNum()
205 static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) { in getVecPolicyOpNum()
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| /openbsd/gnu/llvm/llvm/lib/Target/M68k/ |
| H A D | M68kInstrBuilder.h | 63 const MCInstrDesc &MCID = MI->getDesc();
80 const MCInstrDesc &MCID = MI->getDesc();
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| H A D | M68kInstrInfo.h | 314 const MCInstrDesc &Desc, MVT MVTDst, MVT MVTSrc) const;
317 bool ExpandPUSH_POP(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
324 bool ExpandMOVEM(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 425 const MCInstrDesc &DefMCID,
429 const MCInstrDesc &DefMCID,
433 const MCInstrDesc &UseMCID,
437 const MCInstrDesc &UseMCID,
441 const MCInstrDesc &DefMCID,
443 const MCInstrDesc &UseMCID,
448 const MCInstrDesc &DefMCID, unsigned DefAdj,
451 const MCInstrDesc &UseMCID, unsigned UseAdj) const;
898 const MCInstrDesc &Desc = TII->get(Opcode); in isLegalAddressImm()
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| H A D | MLxExpansionPass.cpp | 184 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
284 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
339 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions()
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| H A D | ARMHazardRecognizer.cpp | 31 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
52 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
55 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
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| /openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | Mips16InstrInfo.h | 24 class MCInstrDesc; variable
100 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
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| /openbsd/gnu/llvm/llvm/tools/llvm-exegesis/lib/ |
| H A D | MCInstrDescView.h | 155 const MCInstrDesc &Description;
164 Instruction(const MCInstrDesc *Description, StringRef Name,
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 129 const MCInstrDesc &MID = MI.getDesc(); in INITIALIZE_PASS_DEPENDENCY()
196 const MCInstrDesc &UseMID = UseMI.getDesc(); in canRemoveAddasl()
376 const MCInstrDesc &MID = MI->getDesc(); in getBaseOpPosition()
398 const MCInstrDesc &MID = MI->getDesc(); in getOffsetOpPosition()
425 const MCInstrDesc &MID = MI->getDesc(); in processAddUses()
520 const MCInstrDesc &MID = MI.getDesc(); in analyzeUses()
702 const MCInstrDesc &UseMID = UseMI->getDesc(); in changeAddAsl()
749 const MCInstrDesc &MID = UseMI->getDesc(); in xformUseMI()
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| /openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | SIMCCodeEmitter.cpp | 314 static bool isVCMPX64(const MCInstrDesc &Desc) { in isVCMPX64()
325 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
458 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getSDWASrcEncoding()
573 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getMachineOpValueCommon()
580 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getMachineOpValueCommon()
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| /openbsd/gnu/llvm/llvm/lib/Target/SPIRV/MCTargetDesc/ |
| H A D | SPIRVInstPrinter.cpp | 83 const MCInstrDesc &MCDesc = MII.get(OpCode); in printInst()
188 const MCInstrDesc &MCDesc = MII.get(MI->getOpcode()); in printOpExtInst()
203 const MCInstrDesc &MCDesc = MII.get(MI->getOpcode()); in printOpDecorate()
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