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Searched refs:RW (Results 1 – 25 of 98) sorted by relevance

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/openbsd/sys/arch/luna88k/luna88k/
H A Dpmap_table.c38 #define RW (PROT_READ | PROT_WRITE) macro
54 { OBIO_SIO, PAGE_SIZE, RW, CI },
55 { OBIO_TAS, PAGE_SIZE, RW, CI },
58 { SOFT_INT0, PAGE_SIZE, RW, CI },
66 { PC_BASE, PC_SPACE, RW, CI },
81 { BMAP_FN, PAGE_SIZE, RW, CI },
83 { BMAP_FN0, PAGE_SIZE, RW, CI },
84 { BMAP_FN1, PAGE_SIZE, RW, CI },
85 { BMAP_FN2, PAGE_SIZE, RW, CI },
86 { BMAP_FN3, PAGE_SIZE, RW, CI },
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/openbsd/sys/dev/ic/
H A Dar9285.c216 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, in ar9285_init_from_rom()
220 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, in ar9285_init_from_rom()
228 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, in ar9285_init_from_rom()
232 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, in ar9285_init_from_rom()
255 reg = RW(reg, AR9285_PHY_ANT_DIV_CTL, in ar9285_init_from_rom()
261 reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_GAINTB, in ar9285_init_from_rom()
393 reg = RW(reg, AR_PHY_TX_END_PA_ON, in ar9285_init_from_rom()
395 reg = RW(reg, AR_PHY_TX_END_DATA_START, in ar9285_init_from_rom()
460 reg = RW(reg, AR9285_AN_RF2G6_CCOMP, 0xf); in ar9285_pa_calib()
556 reg = RW(reg, AR9271_AN_RF2G3_CCOMP, 0xfff); in ar9271_pa_calib()
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H A Dar9380.c363 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_0, 5); in ar9380_init_from_rom()
364 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_1, 5); in ar9380_init_from_rom()
365 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_2, 5); in ar9380_init_from_rom()
366 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_3, 5); in ar9380_init_from_rom()
367 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_4, 5); in ar9380_init_from_rom()
368 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_5, 5); in ar9380_init_from_rom()
372 reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_0, 5); in ar9380_init_from_rom()
373 reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_1, 5); in ar9380_init_from_rom()
374 reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_2, 5); in ar9380_init_from_rom()
375 reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_3, 5); in ar9380_init_from_rom()
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H A Dar9287.c185 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, in ar9287_init_from_rom()
187 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, in ar9287_init_from_rom()
192 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, in ar9287_init_from_rom()
194 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, in ar9287_init_from_rom()
199 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, in ar9287_init_from_rom()
201 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, in ar9287_init_from_rom()
236 reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1); in ar9287_init_from_rom()
237 reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2); in ar9287_init_from_rom()
247 reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1); in ar9287_init_from_rom()
248 reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2); in ar9287_init_from_rom()
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H A Dar9280.c228 reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1); in ar9280_set_synth()
274 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, in ar9280_init_from_rom()
278 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, in ar9280_init_from_rom()
287 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, in ar9280_init_from_rom()
289 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, in ar9280_init_from_rom()
295 reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob); in ar9280_init_from_rom()
329 reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, 0); in ar9280_init_from_rom()
375 reg = RW(reg, AR_PHY_TX_END_DATA_START, in ar9280_init_from_rom()
406 reg = RW(reg, AR_PHY_FRAME_CTL_TX_CLIP, in ar9280_init_from_rom()
411 reg = RW(reg, AR_PHY_TX_DESIRED_SCALE_CCK, in ar9280_init_from_rom()
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H A Dar5416.c262 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, in ar5416_init_from_rom()
264 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, in ar5416_init_from_rom()
273 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_MARGIN, in ar5416_init_from_rom()
275 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_ATTEN, in ar5416_init_from_rom()
284 reg = RW(reg, AR_PHY_RXGAIN_TXRX_ATTEN, txRxAtten); in ar5416_init_from_rom()
288 reg = RW(reg, AR_PHY_GAIN_2GHZ_RXTX_MARGIN, in ar5416_init_from_rom()
312 reg = RW(reg, AR_PHY_CCA_THRESH62, modal->thresh62); in ar5416_init_from_rom()
321 reg = RW(reg, AR_PHY_TX_END_DATA_START, in ar5416_init_from_rom()
464 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]); in ar5416_set_power_calib()
484 reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); in ar5416_set_power_calib()
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H A Dar9003.c564 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); in ar9003_rfsilent_init()
820 reg = RW(reg, AR_RXBP_THRESH_HP, 1); in ar9003_rx_enable()
821 reg = RW(reg, AR_RXBP_THRESH_LP, 1); in ar9003_rx_enable()
1864 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); in ar9003_set_delta_slope()
1865 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); in ar9003_set_delta_slope()
1874 reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp); in ar9003_set_delta_slope()
1875 reg = RW(reg, AR_PHY_SGI_DSC_MAN, man); in ar9003_set_delta_slope()
1966 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); in ar9003_write_noisefloor()
3294 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77); in ar9003_enable_ofdm_weak_signal()
3295 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64); in ar9003_enable_ofdm_weak_signal()
[all …]
H A Dar5008.c462 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); in ar5008_rfsilent_init()
1926 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); in ar5008_set_delta_slope()
1927 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); in ar5008_set_delta_slope()
1936 reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp); in ar5008_set_delta_slope()
1937 reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man); in ar5008_set_delta_slope()
2032 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); in ar5008_write_noisefloor()
2341 reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QDC, in ar5008_calib_adc_dc_off()
2343 reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IDC, in ar5008_calib_adc_dc_off()
2877 reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77); in ar5008_enable_ofdm_weak_signal()
2878 reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64); in ar5008_enable_ofdm_weak_signal()
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/openbsd/sys/dev/microcode/aic7xxx/
H A Daic79xx.reg91 access_mode RW
105 access_mode RW
122 access_mode RW
248 access_mode RW
264 access_mode RW
273 access_mode RW
281 access_mode RW
317 access_mode RW
326 access_mode RW
336 access_mode RW
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H A Daic7xxx.reg60 access_mode RW
77 access_mode RW
93 access_mode RW
170 access_mode RW
186 access_mode RW
208 access_mode RW
213 access_mode RW
226 access_mode RW
232 access_mode RW
241 access_mode RW
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/openbsd/gnu/llvm/libcxx/lib/abi/
H A Dpowerpc-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist580 {'import_export': 'EXP', 'is_defined': True, 'name': '_ZNSt3__13cinE', 'storage_mapping_class': 'RW…
648 …P', 'is_defined': True, 'name': '_ZNSt3__14cerrE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
649 …P', 'is_defined': True, 'name': '_ZNSt3__14clogE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
650 …P', 'is_defined': True, 'name': '_ZNSt3__14coutE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
659 …P', 'is_defined': True, 'name': '_ZNSt3__14wcinE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
684 …', 'is_defined': True, 'name': '_ZNSt3__15wcerrE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
685 …', 'is_defined': True, 'name': '_ZNSt3__15wclogE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
686 …', 'is_defined': True, 'name': '_ZNSt3__15wcoutE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
1098 …', 'is_defined': False, 'name': '_ZTISt8bad_cast', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
1099 …, 'is_defined': False, 'name': '_ZTISt9bad_alloc', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
[all …]
H A Dpowerpc64-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist580 {'import_export': 'EXP', 'is_defined': True, 'name': '_ZNSt3__13cinE', 'storage_mapping_class': 'RW…
648 …P', 'is_defined': True, 'name': '_ZNSt3__14cerrE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
649 …P', 'is_defined': True, 'name': '_ZNSt3__14clogE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
650 …P', 'is_defined': True, 'name': '_ZNSt3__14coutE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
659 …P', 'is_defined': True, 'name': '_ZNSt3__14wcinE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
684 …', 'is_defined': True, 'name': '_ZNSt3__15wcerrE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
685 …', 'is_defined': True, 'name': '_ZNSt3__15wclogE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
686 …', 'is_defined': True, 'name': '_ZNSt3__15wcoutE', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
1098 …', 'is_defined': False, 'name': '_ZTISt8bad_cast', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
1099 …, 'is_defined': False, 'name': '_ZTISt9bad_alloc', 'storage_mapping_class': 'RW', 'type': 'OBJECT'}
[all …]
/openbsd/gnu/llvm/compiler-rt/lib/tsan/tests/rtl/
H A Dtsan_test_util_posix.cpp107 else if (type_ == RW) in Init()
130 else if (type_ == RW) in Destroy()
142 else if (type_ == RW) in Lock()
154 else if (type_ == RW) in TryLock()
167 else if (type_ == RW) in Unlock()
173 CHECK(type_ == RW); in ReadLock()
179 CHECK(type_ == RW); in TryReadLock()
185 CHECK(type_ == RW); in ReadUnlock()
H A Dtsan_mop.cpp68 UserMutex m(UserMutex::RW); in TEST_F()
87 UserMutex m(UserMutex::RW); in TEST_F()
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp101 return IsSubLo ? BT::BitMask(0, RW-1) in mask()
102 : BT::BitMask(RW, 2*RW-1); in mask()
277 assert(RW <= RC.width()); in evaluate()
278 return eXTR(RC, 0, RW); in evaluate()
284 assert(RW <= W); in evaluate()
285 return eXTR(RC, W-RW, W); in evaluate()
345 uint16_t RW = W0; in evaluate() local
347 assert(PW <= RW); in evaluate()
350 RC.fill(PW, RW, BT::BitValue::Zero); in evaluate()
354 uint16_t RW = W0; in evaluate() local
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/openbsd/usr.bin/uuencode/
H A Duuencode.c114 #define RW (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) in main() macro
115 mode = RW & ~umask(RW); in main()
/openbsd/gnu/llvm/clang/utils/ABITest/
H A DEnumeration.py152 LW,RW = W//2, W - (W//2)
153 L,R = getNthPairBounded(N, H**LW, H**RW)
155 getNthNTuple(R,RW,H=H,useLeftToRight=useLeftToRight))
/openbsd/gnu/usr.bin/perl/cpan/Encode/t/
H A Dat-cn.t65 '!6RW>-!75ZR;XT',
78 '!6RW>-!75ZR;XT',
/openbsd/regress/lib/libcrypto/x509/bettertls/certificates/
H A D671.crt13 46KrreoF/RW+PYlIrlhnbm2G5+pf94Dj7lMtRlBLqqX08/MtYJJP+z7ASgur5ADO
H A D2556.crt17 YWyHBH8AAAEwDQYJKoZIhvcNAQELBQADggEBAH+cXvN/REbgfSvP+RW/HeuVeyeO
H A D2836.key16 RW/z+LBrCE8j1rzH8kwFMCoWiXUzHyTgp+YTI6sEhINt/pD97arPl4jeeu/Y2+O6
H A D1301.key18 RW+NwkrptrddQB5Yk54STOzLKJKraSIsExFL1e0CgYBNUERXsG0AvyzZ2NfLi2df
H A D1222.key8 ZmjBBnX89+RW+KjemkBn0UuSa5/DSeQZog2E1aQgluA/ltmlq2oP6WRhG0GNuqRb
H A D2812.key8 Fmj4DldUp0qT6f9zA5W+RW/uXnwOzAAYLKvy2vxSG0sJD2oLsntD+Nuy2QjQkb56
/openbsd/gnu/llvm/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp609 for (Record *RW : RWs) { in collectSchedRW()
610 if (RW->isSubClassOf("SchedWrite")) in collectSchedRW()
611 scanSchedRW(RW, SWDefs, RWSet); in collectSchedRW()
614 scanSchedRW(RW, SRDefs, RWSet); in collectSchedRW()
689 CodeGenSchedRW &RW = getSchedRW(MatchDef); in collectSchedRW() local
690 if (RW.IsAlias) in collectSchedRW()
692 RW.Aliases.push_back(ADef); in collectSchedRW()
732 RWVec, [Def](const CodeGenSchedRW &RW) { return RW.TheDef == Def; }); in getSchedRWIdx() argument
840 auto I = find_if(RWVec, [Seq](CodeGenSchedRW &RW) { in findRWForSequence() argument
841 return ArrayRef(RW.Sequence) == Seq; in findRWForSequence()
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