Home
last modified time | relevance | path

Searched refs:cacheline_size (Results 1 – 9 of 9) sorted by relevance

/openbsd/sys/arch/powerpc64/powerpc64/
H A Dsyncicache.c48 by = cacheline_size; in __syncicache()
H A Dpmap.c1475 for (offset = 0; offset < PAGE_SIZE; offset += cacheline_size) in pmap_zero_page()
1488 for (offset = 0; offset < PAGE_SIZE; offset += cacheline_size) in pmap_flush_page()
H A Dmachdep.c53 int cacheline_size = 128; variable
/openbsd/sys/arch/powerpc64/include/
H A Dcpufunc.h218 extern int cacheline_size;
/openbsd/sys/dev/pci/drm/amd/amdkfd/
H A Dkfd_topology.h99 uint32_t cacheline_size; member
H A Dkfd_crat.c1107 props->cacheline_size = cache->cache_line_size; in kfd_parse_subtype_cache()
H A Dkfd_topology.c357 cache->cacheline_size); in kfd_cache_show()
/openbsd/sys/dev/pci/drm/i915/display/
H A Di9xx_wm.c355 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
363 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
371 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
379 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
387 .cacheline_size = I915_FIFO_LINE_SIZE,
395 .cacheline_size = I915_FIFO_LINE_SIZE,
403 .cacheline_size = I915_FIFO_LINE_SIZE,
411 .cacheline_size = I830_FIFO_LINE_SIZE,
419 .cacheline_size = I830_FIFO_LINE_SIZE,
427 .cacheline_size = I830_FIFO_LINE_SIZE,
[all …]
H A Dintel_display_types.h1574 u8 cacheline_size; member