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Searched refs:sdma_cntl (Results 1 – 9 of 9) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_si_dma.c590 u32 sdma_cntl; in si_dma_set_trap_irq_state() local
596 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
597 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
598 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
601 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
602 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
603 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
613 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
614 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
618 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
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H A Dsdma_v2_4.c1000 u32 sdma_cntl; in sdma_v2_4_set_trap_irq_state() local
1006 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1007 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1008 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1011 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1012 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
1013 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1023 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1024 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1028 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
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H A Dsdma_v3_0.c1334 u32 sdma_cntl; in sdma_v3_0_set_trap_irq_state() local
1340 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1341 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1342 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1345 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1346 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
1347 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1357 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1358 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1362 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
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H A Damdgpu_cik_sdma.c1107 u32 sdma_cntl; in cik_sdma_set_trap_irq_state() local
1113 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1114 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1115 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1118 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1119 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1120 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1130 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1131 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1135 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
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H A Dsdma_v4_4_2.c1517 u32 sdma_cntl; in sdma_v4_4_2_set_trap_irq_state() local
1519 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); in sdma_v4_4_2_set_trap_irq_state()
1520 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, in sdma_v4_4_2_set_trap_irq_state()
1522 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); in sdma_v4_4_2_set_trap_irq_state()
1613 u32 sdma_cntl; in sdma_v4_4_2_set_ecc_irq_state() local
1615 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); in sdma_v4_4_2_set_ecc_irq_state()
1616 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE, in sdma_v4_4_2_set_ecc_irq_state()
1618 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); in sdma_v4_4_2_set_ecc_irq_state()
H A Dsdma_v6_0.c1454 u32 sdma_cntl; in sdma_v6_0_set_trap_irq_state() local
1459 sdma_cntl = RREG32(reg_offset); in sdma_v6_0_set_trap_irq_state()
1460 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v6_0_set_trap_irq_state()
1462 WREG32(reg_offset, sdma_cntl); in sdma_v6_0_set_trap_irq_state()
H A Dsdma_v5_2.c1410 u32 sdma_cntl; in sdma_v5_2_set_trap_irq_state() local
1414 sdma_cntl = RREG32(reg_offset); in sdma_v5_2_set_trap_irq_state()
1415 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_2_set_trap_irq_state()
1417 WREG32(reg_offset, sdma_cntl); in sdma_v5_2_set_trap_irq_state()
H A Dsdma_v5_0.c1547 u32 sdma_cntl; in sdma_v5_0_set_trap_irq_state() local
1554 sdma_cntl = RREG32(reg_offset); in sdma_v5_0_set_trap_irq_state()
1555 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_0_set_trap_irq_state()
1557 WREG32(reg_offset, sdma_cntl); in sdma_v5_0_set_trap_irq_state()
H A Dsdma_v4_0.c2016 u32 sdma_cntl; in sdma_v4_0_set_trap_irq_state() local
2018 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); in sdma_v4_0_set_trap_irq_state()
2019 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v4_0_set_trap_irq_state()
2021 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); in sdma_v4_0_set_trap_irq_state()