Searched refs:sdma_v5_0_get_reg_offset (Results 1 – 1 of 1) sorted by relevance
| /openbsd/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | sdma_v5_0.c | 389 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
392 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
639 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_0_ctx_switch_enable()
748 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), in sdma_v5_0_gfx_resume()
750 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), in sdma_v5_0_gfx_resume()
780 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_0_gfx_resume()
785 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); in sdma_v5_0_gfx_resume()
879 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); in sdma_v5_0_load_microcode()
960 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0, in sdma_v5_0_mqd_init()
1551 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : in sdma_v5_0_set_trap_irq_state()
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