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Searched refs:v2i32 (Results 1 – 25 of 77) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonCallingConv.td17 CCIfType<[i64,v2i32,v4i16,v8i8],
43 CCIfType<[i64,v2i32,v4i16,v8i8],
45 CCIfType<[i64,v2i32,v4i16,v8i8],
73 CCIfType<[i64,v2i32,v4i16,v8i8],
75 CCIfType<[i64,v2i32,v4i16,v8i8],
99 CCIfType<[i64,v2i32,v4i16,v8i8],
H A DHexagonPatterns.td88 def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>;
481 defm: NopCast_pat<i64, v2i32, DoubleRegs>;
484 defm: NopCast_pat<v2i32, v4i16, DoubleRegs>;
485 defm: NopCast_pat<v2i32, v8i8, DoubleRegs>;
529 def: Pat<(v2i32 (azext V2I1:$Pu)),
543 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)),
546 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
904 def: Pat<(select I1:$Pu, v2i32:$Rs, v2i32:$Rt),
1007 def: OpR_RR_pat<A2_vminw, Smin, v2i32, V2I32>;
1008 def: OpR_RR_pat<A2_vmaxw, Smax, v2i32, V2I32>;
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td600 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVTZ(S|U)v2i32(_shift)?$")>;
658 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^ADD(v1i64|v2i32|v4i16|v8i8)$")>;
661 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(BIC|ORR)(v2i32|v4i16)$")>;
662 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^NEG(v1i64|v2i32|v4i16|v8i8)$")>;
663 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^SUB(v1i64|v2i32|v4i16|v8i8)$")>;
672 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CMTST(v1i64|v2i32|v4i16|v8i8)$")>;
674 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^SHL(v2i32|v4i16|v8i8)_shift$")>;
677 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v2i32|v4i16|v8i8)$")>;
686 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)RHADD(v2i32|v4i16|v8i8)$")>;
689 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^R?SHRN(v2i32|v4i16|v8i8)_shift$")>;
[all …]
H A DAArch64CallingConvention.td28 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
33 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8],
106 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
123 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
131 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8],
143 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
220 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
257 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
282 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
304 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
[all …]
H A DAArch64SchedKryoDetails.td33 (instregex "(S|U)ABA(v8i8|v4i16|v2i32)")>;
57 (instregex "(S|U)(ABD|RHADD)(v8i8|v4i16|v2i32)")>;
69 (instregex "(S|U)ADALP(v8i8|v4i16|v2i32)_v.*")>;
201 (instregex "^(S|U)QADD(v8i8|v4i16|v2i32)")>;
435 …(instregex "((AND|ORN|EOR|EON)S?(Wr[rsi]|v8i8|v4i16|v2i32)|(ORR|BIC)S?(Wr[rs]|v8i8|v4i16|v2i32))")…
507 (instregex "(CLS|CLZ|CNT)(v2i32|v4i16|v8i8)")>;
573 (instregex "DUP(v8i8|v4i16|v2i32)(gpr|lane)")>;
753 (instregex "FCVTL(v2i32|v4i16|v4i32|v8i16)$")>;
1668 (instregex "NEG(v8i8|v4i16|v2i32|v1i64)")>;
1830 (instregex "SQ(ABS|NEG)(v8i8|v4i16|v2i32)")>;
[all …]
H A DAArch64SchedA57.td350 // D form - v8i8, v4i16, v2i32
362 def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)…
369 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
442 // D form - v2i32
451 def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>;
487 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
494 def : InstRW<[A57Write_5cyc_1V_FP_Forward], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
508 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
521 // D form - v8i8, v4i16, v2i32
537 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
[all …]
H A DAArch64InstrInfo.td4502 def : Pat<(v2i32 (AArch64vashr (v2i32 V64:$Rn), (i32 31))),
5900 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
6156 def : Pat<(v2i32 (AArch64uaddv (v2i32 (addlp (v4i16 V64:$op))))),
6279 def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))),
6284 def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),
6288 def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))),
6292 def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))),
6296 def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))),
6300 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
7627 // v0 = load v2i32
[all …]
H A DAArch64ISelDAGToDAG.cpp880 case MVT::v2i32: in tryMLAV64LaneV128()
5090 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
5118 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
5146 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
5174 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
5202 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
5230 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
5258 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
5286 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
5314 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
[all …]
H A DAArch64TargetTransformInfo.cpp389 {Intrinsic::bitreverse, MVT::v2i32, 2}, in getIntrinsicInstrCost()
419 {ISD::CTPOP, MVT::v2i32, 3}, in getIntrinsicInstrCost()
1883 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
3024 {ISD::OR, MVT::v2i32, 3}, in getArithmeticReductionCost()
3031 {ISD::XOR, MVT::v2i32, 3}, in getArithmeticReductionCost()
3038 {ISD::AND, MVT::v2i32, 3}, in getArithmeticReductionCost()
3231 {TTI::SK_Broadcast, MVT::v2i32, 1}, in getShuffleCost()
3243 {TTI::SK_Transpose, MVT::v2i32, 1}, in getShuffleCost()
3251 {TTI::SK_Select, MVT::v2i32, 1}, // mov. in getShuffleCost()
3273 {TTI::SK_Reverse, MVT::v2i32, 1}, // REV64 in getShuffleCost()
[all …]
H A DAArch64InstrGISel.td267 def : Pat<(v2f64 (sint_to_fp v2i32:$src)),
269 def : Pat<(v2f64 (uint_to_fp v2i32:$src)),
280 def : Pat<(v2i32 (fp_to_sint v2f64:$src)),
282 def : Pat<(v2i32 (fp_to_uint v2f64:$src)),
H A DAArch64InstrFormats.td5611 def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS),
5651 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5695 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
5722 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5826 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5873 def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS),
6122 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
6729 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>;
6772 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
10805 (v2i32 (op (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstrNEON.td3411 v2i32, v2i32, fc, Commutable>;
3515 v2i32, v2i32, OpNode, Commutable>;
3588 v2i32, v2i32, IntOp>;
4532 def : Pat<(v2i32 (int_arm_neon_vqrdmlah (v2i32 DPR:$src1), (v2i32 DPR:$Vn),
4586 def : Pat<(v2i32 (int_arm_neon_vqrdmlsh (v2i32 DPR:$src1), (v2i32 DPR:$Vn),
5304 v2i32, v2i32, and, 1>;
5310 v2i32, v2i32, xor, 1>;
5316 v2i32, v2i32, or, 1>;
5525 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 DPR:$src1),
5934 def : Pat<(v2i32 (ARMvshls (v2i32 DPR:$Dn), (v2i32 DPR:$Dm))),
[all …]
H A DARMCallingConv.td33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
186 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
213 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
236 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
H A DARMTargetTransformInfo.cpp649 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
650 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
686 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
687 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
711 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
712 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
718 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
719 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
1219 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
1240 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
[all …]
H A DARMScheduleA57.td977 (instregex "VABA(s|u)(v8i8|v4i16|v2i32)")>;
1020 "VMUL(v8i8|v4i16|v2i32|pd)", "VMULsl(v4i16|v2i32)",
1021 "VQDMULH(sl)?(v4i16|v2i32)", "VQRDMULH(sl)?(v4i16|v2i32)")>;
1042 (instregex "VMLA(sl)?(v8i8|v4i16|v2i32)", "VMLS(sl)?(v8i8|v4i16|v2i32)")>;
1119 "VSLI(v8i8|v4i16|v2i32|v1i64)", "VSRI(v8i8|v4i16|v2i32|v1i64)")>;
1127 "VSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;
1136 "VQRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)", "VQSHL(s|u)(v8i8|v4i16|v2i32|v1i64)",
1137 "VRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;
1212 "VMOV(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v1i64|v2i64|v2f32|v4f32)",
/openbsd/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterInfo.td29 def vID : RegisterClass<"SPIRV", [v2i32], 32, (add vID0)>;
33 …def ANYID : RegisterClass<"SPIRV", [i32, f32, p0, v2i32, v2f32], 32, (add ID, fID, pID, vID, vfID)…
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DCaymanInstructions.td83 def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>;
187 def : R600Pat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
201 def : R600Pat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
215 def : R600Pat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
H A DAMDGPUISelLowering.cpp67 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
106 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32); in AMDGPUTargetLowering()
112 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32); in AMDGPUTargetLowering()
193 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
232 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32); in AMDGPUTargetLowering()
238 AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32); in AMDGPUTargetLowering()
275 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand); in AMDGPUTargetLowering()
462 AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
1487 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in split64BitValue()
1501 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getLoHalf64()
[all …]
H A DR600ISelLowering.cpp36 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
46 setOperationAction(ISD::LOAD, {MVT::i32, MVT::v2i32, MVT::v4i32}, Custom); in R600TargetLowering()
58 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v2i32, in R600TargetLowering()
64 setOperationAction(ISD::STORE, {MVT::i8, MVT::i32, MVT::v2i32, MVT::v4i32}, in R600TargetLowering()
71 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom); in R600TargetLowering()
76 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom); in R600TargetLowering()
83 setTruncStoreAction(MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
97 setOperationAction(ISD::SETCC, {MVT::v4i32, MVT::v2i32}, Expand); in R600TargetLowering()
113 setOperationAction(ISD::SELECT, {MVT::i32, MVT::f32, MVT::v2i32, MVT::v4i32}, in R600TargetLowering()
139 setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::v2i32, MVT::v4i32}, Expand); in R600TargetLowering()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcCallingConv.td24 // As are v2i32 arguments (this would be the default behavior for
25 // v2i32 if it wasn't allocated to the IntPair register-class)
26 CCIfType<[v2i32], CCCustom<"CC_Sparc_Assign_Split_64">>,
37 CCIfType<[v2i32], CCCustom<"CC_Sparc_Assign_Ret_Split_64">>
H A DSparcISelDAGToDAG.cpp241 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32); in tryInlineAsm()
245 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::v2i32, in tryInlineAsm()
274 TargetOpcode::REG_SEQUENCE, dl, MVT::v2i32, in tryInlineAsm()
288 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32); in tryInlineAsm()
H A DSparcISelLowering.cpp286 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
1085 if (RVLocs[i].getLocVT() == MVT::v2i32) { in LowerCall_32()
1086 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32); in LowerCall_32()
1566 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass); in SparcTargetLowering()
1571 setOperationAction(Op, MVT::v2i32, Expand); in SparcTargetLowering()
1583 setTruncStoreAction(VT, MVT::v2i32, Expand); in SparcTargetLowering()
1584 setTruncStoreAction(MVT::v2i32, VT, Expand); in SparcTargetLowering()
1587 setOperationAction(ISD::LOAD, MVT::v2i32, Legal); in SparcTargetLowering()
1588 setOperationAction(ISD::STORE, MVT::v2i32, Legal); in SparcTargetLowering()
3262 return DAG.getBuildVector(MVT::v2i32, DL, {Hi, Lo}); in bitcastConstantFPToInt()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp465 {Intrinsic::bswap, MVT::v2i32, 12},
491 {Intrinsic::vp_bswap, MVT::v2i32, 12},
529 {Intrinsic::vp_fshl, MVT::v2i32, 7},
567 {Intrinsic::vp_fshr, MVT::v2i32, 7},
602 {Intrinsic::bitreverse, MVT::v2i32, 33},
637 {Intrinsic::vp_bitreverse, MVT::v2i32, 33},
672 {Intrinsic::ctpop, MVT::v2i32, 20},
707 {Intrinsic::vp_ctpop, MVT::v2i32, 20},
745 {Intrinsic::vp_ctlz, MVT::v2i32, 31},
783 {Intrinsic::vp_cttz, MVT::v2i32, 24},
/openbsd/gnu/llvm/llvm/include/llvm/Support/
H A DMachineValueType.h110 v2i32 = 56, // 2 x i32 enumerator
420 SimpleTy == MVT::v4i16 || SimpleTy == MVT::v2i32 || in is64BitVector()
606 case v2i32: in getVectorElementType()
865 case v2i32: in getVectorMinNumElements()
989 case v2i32: in getSizeInBits()
1318 if (NumElements == 2) return MVT::v2i32; in getVectorVT()
/openbsd/gnu/llvm/llvm/include/llvm/IR/
H A DIntrinsicsNVVM.td2566 "llvm.nvvm.suld.1d.v2i32.clamp">;
2656 "llvm.nvvm.suld.2d.v2i32.clamp">;
2746 "llvm.nvvm.suld.3d.v2i32.clamp">;
2792 "llvm.nvvm.suld.1d.v2i32.trap">;
2882 "llvm.nvvm.suld.2d.v2i32.trap">;
2972 "llvm.nvvm.suld.3d.v2i32.trap">;
3018 "llvm.nvvm.suld.1d.v2i32.zero">;
3108 "llvm.nvvm.suld.2d.v2i32.zero">;
3198 "llvm.nvvm.suld.3d.v2i32.zero">;
3596 "llvm.nvvm.sust.b.1d.v2i32.trap">,
[all …]

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