1//===- HexagonPatterns.td - Selection Patterns for Hexagon -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// Table of contents: 10// (0) Definitions 11// (1) Immediates 12// (2) Type casts 13// (3) Extend/truncate/saturate 14// (4) Logical 15// (5) Compare 16// (6) Select 17// (7) Insert/extract 18// (8) Shift/permute 19// (9) Arithmetic/bitwise 20// (10) Bit 21// (11) PIC 22// (12) Load 23// (13) Store 24// (14) Memop 25// (15) Call 26// (16) Branch 27// (17) Misc 28 29// Guidelines (in no particular order): 30// 1. Avoid relying on pattern ordering to give preference to one pattern 31// over another, prefer using AddedComplexity instead. The reason for 32// this is to avoid unintended conseqeuences (caused by altering the 33// order) when making changes. The current order of patterns in this 34// file obviously does play some role, but none of the ordering was 35// deliberately chosen (other than to create a logical structure of 36// this file). When making changes, adding AddedComplexity to existing 37// patterns may be needed. 38// 2. Maintain the logical structure of the file, try to put new patterns 39// in designated sections. 40// 3. Do not use A2_combinew instruction directly, use Combinew fragment 41// instead. It uses REG_SEQUENCE, which is more amenable to optimizations. 42// 4. Most selection macros are based on PatFrags. For DAGs that involve 43// SDNodes, use pf1/pf2 to convert them to PatFrags. Use common frags 44// whenever possible (see the Definitions section). When adding new 45// macro, try to make is general to enable reuse across sections. 46// 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition 47// that the nested operation has only one use. Having it separated in case 48// of multiple uses avoids duplication of (processor) work. 49// 6. The v4 vector instructions (64-bit) are treated as core instructions, 50// for example, A2_vaddh is in the "arithmetic" section with A2_add. 51// 7. When adding a pattern for an instruction with a constant-extendable 52// operand, allow all possible kinds of inputs for the immediate value 53// (see AnyImm/anyimm and their variants in the Definitions section). 54 55 56// --(0) Definitions ----------------------------------------------------- 57// 58 59// This complex pattern exists only to create a machine instruction operand 60// of type "frame index". There doesn't seem to be a way to do that directly 61// in the patterns. 62def AddrFI: ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>; 63 64// These complex patterns are not strictly necessary, since global address 65// folding will happen during DAG combining. For distinguishing between GA 66// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used. 67def AddrGA: ComplexPattern<i32, 1, "SelectAddrGA", [], []>; 68def AddrGP: ComplexPattern<i32, 1, "SelectAddrGP", [], []>; 69def AnyImm: ComplexPattern<i32, 1, "SelectAnyImm", [], []>; 70def AnyInt: ComplexPattern<i32, 1, "SelectAnyInt", [], []>; 71 72// Global address or a constant being a multiple of 2^n. 73def AnyImm0: ComplexPattern<i32, 1, "SelectAnyImm0", [], []>; 74def AnyImm1: ComplexPattern<i32, 1, "SelectAnyImm1", [], []>; 75def AnyImm2: ComplexPattern<i32, 1, "SelectAnyImm2", [], []>; 76def AnyImm3: ComplexPattern<i32, 1, "SelectAnyImm3", [], []>; 77 78 79// Type helper frags. 80def V2I1: PatLeaf<(v2i1 PredRegs:$R)>; 81def V4I1: PatLeaf<(v4i1 PredRegs:$R)>; 82def V8I1: PatLeaf<(v8i1 PredRegs:$R)>; 83def V4I8: PatLeaf<(v4i8 IntRegs:$R)>; 84def V2I16: PatLeaf<(v2i16 IntRegs:$R)>; 85 86def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>; 87def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>; 88def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>; 89 90def SDTVecLeaf: 91 SDTypeProfile<1, 0, [SDTCisVec<0>]>; 92def SDTVecVecIntOp: 93 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>, 94 SDTCisVT<3,i32>]>; 95 96def HexagonPTRUE: SDNode<"HexagonISD::PTRUE", SDTVecLeaf>; 97def HexagonPFALSE: SDNode<"HexagonISD::PFALSE", SDTVecLeaf>; 98def HexagonVALIGN: SDNode<"HexagonISD::VALIGN", SDTVecVecIntOp>; 99def HexagonVALIGNADDR: SDNode<"HexagonISD::VALIGNADDR", SDTIntUnaryOp>; 100def HexagonMULHUS: SDNode<"HexagonISD::MULHUS", SDTIntBinOp>; 101 102def SDTSaturate: 103 SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, SDTCisVT<2, OtherVT>]>; 104def HexagonSSAT: SDNode<"HexagonISD::SSAT", SDTSaturate>; 105def HexagonUSAT: SDNode<"HexagonISD::USAT", SDTSaturate>; 106 107def ptrue: PatFrag<(ops), (HexagonPTRUE)>; 108def pfalse: PatFrag<(ops), (HexagonPFALSE)>; 109def pnot: PatFrag<(ops node:$Pu), (xor node:$Pu, ptrue)>; 110 111def valign: PatFrag<(ops node:$Vt, node:$Vs, node:$Ru), 112 (HexagonVALIGN node:$Vt, node:$Vs, node:$Ru)>; 113def valignaddr: PatFrag<(ops node:$Addr), (HexagonVALIGNADDR node:$Addr)>; 114 115def ssat: PatFrag<(ops node:$V, node:$Ty), (HexagonSSAT node:$V, node:$Ty)>; 116def usat: PatFrag<(ops node:$V, node:$Ty), (HexagonUSAT node:$V, node:$Ty)>; 117 118// Pattern fragments to extract the low and high subregisters from a 119// 64-bit value. 120def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_lo)>; 121def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_hi)>; 122 123def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{ 124 return isOrEquivalentToAdd(N); 125}]>; 126 127def IsPow2_32: PatLeaf<(i32 imm), [{ 128 uint32_t V = N->getZExtValue(); 129 return isPowerOf2_32(V); 130}]>; 131 132def IsPow2_64: PatLeaf<(i64 imm), [{ 133 uint64_t V = N->getZExtValue(); 134 return isPowerOf2_64(V); 135}]>; 136 137def IsNPow2_32: PatLeaf<(i32 imm), [{ 138 uint32_t NV = ~N->getZExtValue(); 139 return isPowerOf2_32(NV); 140}]>; 141 142def IsPow2_64L: PatLeaf<(i64 imm), [{ 143 uint64_t V = N->getZExtValue(); 144 return isPowerOf2_64(V) && Log2_64(V) < 32; 145}]>; 146 147def IsPow2_64H: PatLeaf<(i64 imm), [{ 148 uint64_t V = N->getZExtValue(); 149 return isPowerOf2_64(V) && Log2_64(V) >= 32; 150}]>; 151 152def IsNPow2_64L: PatLeaf<(i64 imm), [{ 153 uint64_t NV = ~N->getZExtValue(); 154 return isPowerOf2_64(NV) && Log2_64(NV) < 32; 155}]>; 156 157def IsNPow2_64H: PatLeaf<(i64 imm), [{ 158 uint64_t NV = ~N->getZExtValue(); 159 return isPowerOf2_64(NV) && Log2_64(NV) >= 32; 160}]>; 161 162class IsULE<int Width, int Arg>: PatLeaf<(i32 imm), 163 "uint64_t V = N->getZExtValue();" # 164 "return isUInt<" # Width # ">(V) && V <= " # Arg # ";" 165>; 166 167class IsUGT<int Width, int Arg>: PatLeaf<(i32 imm), 168 "uint64_t V = N->getZExtValue();" # 169 "return isUInt<" # Width # ">(V) && V > " # Arg # ";" 170>; 171 172def SDEC1: SDNodeXForm<imm, [{ 173 int32_t V = N->getSExtValue(); 174 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 175}]>; 176 177def UDEC1: SDNodeXForm<imm, [{ 178 uint32_t V = N->getZExtValue(); 179 assert(V >= 1); 180 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32); 181}]>; 182 183def UDEC32: SDNodeXForm<imm, [{ 184 uint32_t V = N->getZExtValue(); 185 assert(V >= 32); 186 return CurDAG->getTargetConstant(V-32, SDLoc(N), MVT::i32); 187}]>; 188 189class Subi<int From>: SDNodeXForm<imm, 190 "int32_t V = " # From # " - N->getSExtValue();" # 191 "return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);" 192>; 193 194def Log2_32: SDNodeXForm<imm, [{ 195 uint32_t V = N->getZExtValue(); 196 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 197}]>; 198 199def Log2_64: SDNodeXForm<imm, [{ 200 uint64_t V = N->getZExtValue(); 201 return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32); 202}]>; 203 204def LogN2_32: SDNodeXForm<imm, [{ 205 uint32_t NV = ~N->getZExtValue(); 206 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 207}]>; 208 209def LogN2_64: SDNodeXForm<imm, [{ 210 uint64_t NV = ~N->getZExtValue(); 211 return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32); 212}]>; 213 214def NegImm8: SDNodeXForm<imm, [{ 215 int8_t NV = -N->getSExtValue(); 216 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 217}]>; 218 219def NegImm16: SDNodeXForm<imm, [{ 220 int16_t NV = -N->getSExtValue(); 221 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 222}]>; 223 224def NegImm32: SDNodeXForm<imm, [{ 225 int32_t NV = -N->getSExtValue(); 226 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32); 227}]>; 228 229def SplatB: SDNodeXForm<imm, [{ 230 uint32_t V = N->getZExtValue(); 231 assert(isUInt<8>(V) || V >> 8 == 0xFFFFFF); 232 V &= 0xFF; 233 uint32_t S = V << 24 | V << 16 | V << 8 | V; 234 return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32); 235}]>; 236 237def SplatH: SDNodeXForm<imm, [{ 238 uint32_t V = N->getZExtValue(); 239 assert(isUInt<16>(V) || V >> 16 == 0xFFFF); 240 V &= 0xFFFF; 241 return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32); 242}]>; 243 244 245// Helpers for type promotions/contractions. 246def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>; 247def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>; 248def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>; 249def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>; 250def ToAext64: OutPatFrag<(ops node:$Rs), 251 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>; 252 253def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt), 254 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>; 255 256def addrga: PatLeaf<(i32 AddrGA:$Addr)>; 257def addrgp: PatLeaf<(i32 AddrGP:$Addr)>; 258def anyimm: PatLeaf<(i32 AnyImm:$Imm)>; 259def anyint: PatLeaf<(i32 AnyInt:$Imm)>; 260 261// Global address or an aligned constant. 262def anyimm0: PatLeaf<(i32 AnyImm0:$Addr)>; 263def anyimm1: PatLeaf<(i32 AnyImm1:$Addr)>; 264def anyimm2: PatLeaf<(i32 AnyImm2:$Addr)>; 265def anyimm3: PatLeaf<(i32 AnyImm3:$Addr)>; 266 267def f32ImmPred : PatLeaf<(f32 fpimm:$F)>; 268def f64ImmPred : PatLeaf<(f64 fpimm:$F)>; 269def f32zero: PatLeaf<(f32 fpimm:$F), [{ 270 return N->isExactlyValue(APFloat::getZero(APFloat::IEEEsingle(), false)); 271}]>; 272 273// This complex pattern is really only to detect various forms of 274// sign-extension i32->i64. The selected value will be of type i64 275// whose low word is the value being extended. The high word is 276// unspecified. 277def Usxtw: ComplexPattern<i64, 1, "DetectUseSxtw", [], []>; 278 279def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>; 280def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>; 281def Sext64: PatLeaf<(i64 Usxtw:$Rs)>; 282 283def azext: PatFrags<(ops node:$Rs), [(zext node:$Rs), (anyext node:$Rs)]>; 284def asext: PatFrags<(ops node:$Rs), [(sext node:$Rs), (anyext node:$Rs)]>; 285 286def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off), 287 (PS_fi (i32 AddrFI:$Rs), imm:$off)>; 288 289 290// Converters from unary/binary SDNode to PatFrag. 291class pf1<SDNode Op> : PatFrag<(ops node:$a), (Op node:$a)>; 292class pf2<SDNode Op> : PatFrag<(ops node:$a, node:$b), (Op node:$a, node:$b)>; 293 294class Not2<PatFrag P> 295 : PatFrag<(ops node:$A, node:$B), (P node:$A, (not node:$B))>; 296class VNot2<PatFrag P, PatFrag Not> 297 : PatFrag<(ops node:$A, node:$B), (P node:$A, (Not node:$B))>; 298 299// If there is a constant operand that feeds the and/or instruction, 300// do not generate the compound instructions. 301// It is not always profitable, as some times we end up with a transfer. 302// Check the below example. 303// ra = #65820; rb = lsr(rb, #8); rc ^= and (rb, ra) 304// Instead this is preferable. 305// ra = and (#65820, lsr(ra, #8)); rb = xor(rb, ra) 306class Su_ni1<PatFrag Op> 307 : PatFrag<Op.Operands, !head(Op.Fragments), [{ 308 if (hasOneUse(N)){ 309 // Check if Op1 is an immediate operand. 310 SDValue Op1 = N->getOperand(1); 311 return !isa<ConstantSDNode>(Op1); 312 } 313 return false;}], 314 Op.OperandTransform>; 315 316class Su<PatFrag Op> 317 : PatFrag<Op.Operands, !head(Op.Fragments), [{ return hasOneUse(N); }], 318 Op.OperandTransform>; 319 320// Main selection macros. 321 322class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred> 323 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>; 324 325class OpR_RI_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 326 PatFrag RegPred, PatFrag ImmPred> 327 : Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)), 328 (MI RegPred:$Rs, imm:$I)>; 329 330class OpR_RR_pat<InstHexagon MI, PatFrag Op, ValueType ResType, 331 PatFrag RsPred, PatFrag RtPred = RsPred> 332 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 333 (MI RsPred:$Rs, RtPred:$Rt)>; 334 335class AccRRI_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 336 PatFrag RegPred, PatFrag ImmPred> 337 : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)), 338 (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>; 339 340class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op, 341 PatFrag RxPred, PatFrag RsPred, PatFrag RtPred> 342 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)), 343 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>; 344 345multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val, 346 InstHexagon InstA, InstHexagon InstB> { 347 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B), 348 (InstA Val:$A, Val:$B)>; 349 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A), 350 (InstB Val:$A, Val:$B)>; 351} 352 353multiclass MinMax_pats<InstHexagon PickT, InstHexagon PickS, 354 SDPatternOperator Sel, SDPatternOperator CmpOp, 355 ValueType CmpType, PatFrag CmpPred> { 356 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 357 CmpPred:$Vt, CmpPred:$Vs), 358 (PickT CmpPred:$Vs, CmpPred:$Vt)>; 359 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)), 360 CmpPred:$Vs, CmpPred:$Vt), 361 (PickS CmpPred:$Vs, CmpPred:$Vt)>; 362} 363 364// Bitcasts between same-size vector types are no-ops, except for the 365// actual type change. 366multiclass NopCast_pat<ValueType Ty1, ValueType Ty2, RegisterClass RC> { 367 def: Pat<(Ty1 (bitconvert (Ty2 RC:$Val))), (Ty1 RC:$Val)>; 368 def: Pat<(Ty2 (bitconvert (Ty1 RC:$Val))), (Ty2 RC:$Val)>; 369} 370 371// Frags for commonly used SDNodes. 372def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>; 373def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>; 374def Mul: pf2<mul>; def Xor: pf2<xor>; def Shl: pf2<shl>; 375 376def Smin: pf2<smin>; def Smax: pf2<smax>; 377def Umin: pf2<umin>; def Umax: pf2<umax>; 378 379def Rol: pf2<rotl>; 380 381def Fptosi: pf1<fp_to_sint>; 382def Fptoui: pf1<fp_to_uint>; 383def Sitofp: pf1<sint_to_fp>; 384def Uitofp: pf1<uint_to_fp>; 385 386 387// --(1) Immediate ------------------------------------------------------- 388// 389 390def Imm64Lo: SDNodeXForm<imm, [{ 391 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()), 392 SDLoc(N), MVT::i32); 393}]>; 394def Imm64Hi: SDNodeXForm<imm, [{ 395 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()>>32), 396 SDLoc(N), MVT::i32); 397}]>; 398 399 400def SDTHexagonCONST32 401 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>; 402 403def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>; 404def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>; 405def HexagonCONST32: SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; 406def HexagonCONST32_GP: SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>; 407 408def TruncI64ToI32: SDNodeXForm<imm, [{ 409 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); 410}]>; 411 412def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>; 413def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>; 414 415def: Pat<(HexagonCONST32 tglobaltlsaddr:$A), (A2_tfrsi imm:$A)>; 416def: Pat<(HexagonCONST32 bbl:$A), (A2_tfrsi imm:$A)>; 417def: Pat<(HexagonCONST32 tglobaladdr:$A), (A2_tfrsi imm:$A)>; 418def: Pat<(HexagonCONST32_GP tblockaddress:$A), (A2_tfrsi imm:$A)>; 419def: Pat<(HexagonCONST32_GP tglobaladdr:$A), (A2_tfrsi imm:$A)>; 420def: Pat<(HexagonJT tjumptable:$A), (A2_tfrsi imm:$A)>; 421def: Pat<(HexagonCP tconstpool:$A), (A2_tfrsi imm:$A)>; 422// The HVX load patterns also match CP directly. Make sure that if 423// the selection of this opcode changes, it's updated in all places. 424 425def: Pat<(i1 0), (PS_false)>; 426def: Pat<(i1 1), (PS_true)>; 427def: Pat<(i64 imm:$v), (CONST64 imm:$v)>, 428 Requires<[UseSmallData,NotOptTinyCore]>; 429def: Pat<(i64 imm:$v), 430 (Combinew (A2_tfrsi (Imm64Hi $v)), (A2_tfrsi (Imm64Lo $v)))>; 431 432def ftoi : SDNodeXForm<fpimm, [{ 433 APInt I = N->getValueAPF().bitcastToAPInt(); 434 return CurDAG->getTargetConstant(I.getZExtValue(), SDLoc(N), 435 MVT::getIntegerVT(I.getBitWidth())); 436}]>; 437 438def: Pat<(f32ImmPred:$f), (A2_tfrsi (ftoi $f))>; 439def: Pat<(f64ImmPred:$f), (CONST64 (ftoi $f))>; 440 441def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>; 442 443// --(2) Type cast ------------------------------------------------------- 444// 445 446def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>; 447def: OpR_R_pat<F2_conv_df2sf, pf1<fpround>, f32, F64>; 448 449def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>; 450def: OpR_R_pat<F2_conv_d2sf, pf1<sint_to_fp>, f32, I64>; 451def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>; 452def: OpR_R_pat<F2_conv_d2df, pf1<sint_to_fp>, f64, I64>; 453 454def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>; 455def: OpR_R_pat<F2_conv_ud2sf, pf1<uint_to_fp>, f32, I64>; 456def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>; 457def: OpR_R_pat<F2_conv_ud2df, pf1<uint_to_fp>, f64, I64>; 458 459def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>; 460def: OpR_R_pat<F2_conv_df2w_chop, pf1<fp_to_sint>, i32, F64>; 461def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>; 462def: OpR_R_pat<F2_conv_df2d_chop, pf1<fp_to_sint>, i64, F64>; 463 464def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>; 465def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>; 466def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>; 467def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>; 468 469// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp]. 470def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; 471def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; 472def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>; 473def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>; 474 475// Bit convert 32- and 64-bit types. 476// All of these are bitcastable to one another: i32, v2i16, v4i8. 477defm: NopCast_pat<i32, v2i16, IntRegs>; 478defm: NopCast_pat<i32, v4i8, IntRegs>; 479defm: NopCast_pat<v2i16, v4i8, IntRegs>; 480// All of these are bitcastable to one another: i64, v2i32, v4i16, v8i8. 481defm: NopCast_pat<i64, v2i32, DoubleRegs>; 482defm: NopCast_pat<i64, v4i16, DoubleRegs>; 483defm: NopCast_pat<i64, v8i8, DoubleRegs>; 484defm: NopCast_pat<v2i32, v4i16, DoubleRegs>; 485defm: NopCast_pat<v2i32, v8i8, DoubleRegs>; 486defm: NopCast_pat<v4i16, v8i8, DoubleRegs>; 487 488 489// --(3) Extend/truncate/saturate ---------------------------------------- 490// 491 492def: Pat<(sext_inreg I32:$Rs, i8), (A2_sxtb I32:$Rs)>; 493def: Pat<(sext_inreg I32:$Rs, i16), (A2_sxth I32:$Rs)>; 494def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>; 495def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>; 496def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>; 497 498def: Pat<(i64 (sext I32:$Rs)), (A2_sxtw I32:$Rs)>; 499def: Pat<(Zext64 I32:$Rs), (ToZext64 $Rs)>; 500def: Pat<(Aext64 I32:$Rs), (ToZext64 $Rs)>; 501 502def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>; 503def: Pat<(i1 (trunc I32:$Rs)), (S2_tstbit_i I32:$Rs, 0)>; 504def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg $Rs), 0)>; 505 506let AddedComplexity = 20 in { 507 def: Pat<(and I32:$Rs, 255), (A2_zxtb I32:$Rs)>; 508 def: Pat<(and I32:$Rs, 65535), (A2_zxth I32:$Rs)>; 509} 510 511// Extensions from i1 or vectors of i1. 512def: Pat<(i32 (azext I1:$Pu)), (C2_muxii I1:$Pu, 1, 0)>; 513def: Pat<(i64 (azext I1:$Pu)), (ToZext64 (C2_muxii I1:$Pu, 1, 0))>; 514def: Pat<(i32 (sext I1:$Pu)), (C2_muxii I1:$Pu, -1, 0)>; 515def: Pat<(i64 (sext I1:$Pu)), (Combinew (C2_muxii PredRegs:$Pu, -1, 0), 516 (C2_muxii PredRegs:$Pu, -1, 0))>; 517 518def: Pat<(v2i16 (sext V2I1:$Pu)), (S2_vtrunehb (C2_mask V2I1:$Pu))>; 519def: Pat<(v2i32 (sext V2I1:$Pu)), (C2_mask V2I1:$Pu)>; 520def: Pat<(v4i8 (sext V4I1:$Pu)), (S2_vtrunehb (C2_mask V4I1:$Pu))>; 521def: Pat<(v4i16 (sext V4I1:$Pu)), (C2_mask V4I1:$Pu)>; 522def: Pat<(v8i8 (sext V8I1:$Pu)), (C2_mask V8I1:$Pu)>; 523 524def Vsplatpi: OutPatFrag<(ops node:$V), 525 (Combinew (A2_tfrsi $V), (A2_tfrsi $V))>; 526 527def: Pat<(v2i16 (azext V2I1:$Pu)), 528 (A2_andir (LoReg (C2_mask V2I1:$Pu)), (i32 0x00010001))>; 529def: Pat<(v2i32 (azext V2I1:$Pu)), 530 (A2_andp (C2_mask V2I1:$Pu), (A2_combineii (i32 1), (i32 1)))>; 531def: Pat<(v4i8 (azext V4I1:$Pu)), 532 (A2_andir (LoReg (C2_mask V4I1:$Pu)), (i32 0x01010101))>; 533def: Pat<(v4i16 (azext V4I1:$Pu)), 534 (A2_andp (C2_mask V4I1:$Pu), (Vsplatpi (i32 0x00010001)))>; 535def: Pat<(v8i8 (azext V8I1:$Pu)), 536 (A2_andp (C2_mask V8I1:$Pu), (Vsplatpi (i32 0x01010101)))>; 537 538def: Pat<(v4i16 (azext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>; 539def: Pat<(v2i32 (azext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>; 540def: Pat<(v4i16 (sext V4I8:$Rs)), (S2_vsxtbh V4I8:$Rs)>; 541def: Pat<(v2i32 (sext V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>; 542 543def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)), 544 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>; 545 546def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)), 547 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>; 548 549// Truncate: from vector B copy all 'E'ven 'B'yte elements: 550// A[0] = B[0]; A[1] = B[2]; A[2] = B[4]; A[3] = B[6]; 551def: Pat<(v4i8 (trunc V4I16:$Rs)), 552 (S2_vtrunehb V4I16:$Rs)>; 553 554// Truncate: from vector B copy all 'O'dd 'B'yte elements: 555// A[0] = B[1]; A[1] = B[3]; A[2] = B[5]; A[3] = B[7]; 556// S2_vtrunohb 557 558// Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements: 559// A[0] = B[0]; A[1] = B[2]; A[2] = C[0]; A[3] = C[2]; 560// S2_vtruneh 561 562def: Pat<(v2i16 (trunc V2I32:$Rs)), 563 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>; 564 565// Saturation: 566// Note: saturation assumes the same signed-ness for the input and the 567// output. 568def: Pat<(i32 (ssat I32:$Rs, i8)), (A2_satb I32:$Rs)>; 569def: Pat<(i32 (ssat I32:$Rs, i16)), (A2_sath I32:$Rs)>; 570def: Pat<(i32 (ssat I64:$Rs, i32)), (A2_sat I64:$Rs)>; 571def: Pat<(i32 (usat I32:$Rs, i8)), (A2_satub I32:$Rs)>; 572def: Pat<(i32 (usat I32:$Rs, i16)), (A2_satuh I32:$Rs)>; 573def: Pat<(i32 (usat I64:$Rs, i32)), 574 (C2_mux (C2_cmpeqi (HiReg $Rs), (i32 0)), (LoReg $Rs), (i32 -1))>; 575 576def: Pat<(v4i8 (ssat V4I16:$Rs, v4i8)), (S2_vsathb V4I16:$Rs)>; 577def: Pat<(v2i16 (ssat V2I32:$Rs, v2i16)), (S2_vsatwh V2I32:$Rs)>; 578def: Pat<(v4i8 (usat V4I16:$Rs, v4i8)), (S2_vsathub V4I16:$Rs)>; 579def: Pat<(v2i16 (usat V2I32:$Rs, v2i16)), (S2_vsatwuh V2I32:$Rs)>; 580 581 582// --(4) Logical --------------------------------------------------------- 583// 584 585def: Pat<(not I1:$Ps), (C2_not I1:$Ps)>; 586def: Pat<(pnot V2I1:$Ps), (C2_not V2I1:$Ps)>; 587def: Pat<(pnot V4I1:$Ps), (C2_not V4I1:$Ps)>; 588def: Pat<(pnot V8I1:$Ps), (C2_not V8I1:$Ps)>; 589def: Pat<(add I1:$Ps, -1), (C2_not I1:$Ps)>; 590 591def: OpR_RR_pat<C2_and, And, i1, I1>; 592def: OpR_RR_pat<C2_or, Or, i1, I1>; 593def: OpR_RR_pat<C2_xor, Xor, i1, I1>; 594def: OpR_RR_pat<C2_andn, Not2<And>, i1, I1>; 595def: OpR_RR_pat<C2_orn, Not2<Or>, i1, I1>; 596 597def: AccRRR_pat<C4_and_and, And, Su<And>, I1, I1, I1>; 598def: AccRRR_pat<C4_and_or, And, Su< Or>, I1, I1, I1>; 599def: AccRRR_pat<C4_or_and, Or, Su<And>, I1, I1, I1>; 600def: AccRRR_pat<C4_or_or, Or, Su< Or>, I1, I1, I1>; 601def: AccRRR_pat<C4_and_andn, And, Su<Not2<And>>, I1, I1, I1>; 602def: AccRRR_pat<C4_and_orn, And, Su<Not2< Or>>, I1, I1, I1>; 603def: AccRRR_pat<C4_or_andn, Or, Su<Not2<And>>, I1, I1, I1>; 604def: AccRRR_pat<C4_or_orn, Or, Su<Not2< Or>>, I1, I1, I1>; 605 606multiclass BoolvOpR_RR_pat<InstHexagon MI, PatFrag VOp> { 607 def: OpR_RR_pat<MI, VOp, v2i1, V2I1>; 608 def: OpR_RR_pat<MI, VOp, v4i1, V4I1>; 609 def: OpR_RR_pat<MI, VOp, v8i1, V8I1>; 610} 611 612multiclass BoolvAccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag VOp> { 613 def: AccRRR_pat<MI, AccOp, VOp, V2I1, V2I1, V2I1>; 614 def: AccRRR_pat<MI, AccOp, VOp, V4I1, V4I1, V4I1>; 615 def: AccRRR_pat<MI, AccOp, VOp, V8I1, V8I1, V8I1>; 616} 617 618defm: BoolvOpR_RR_pat<C2_and, And>; 619defm: BoolvOpR_RR_pat<C2_or, Or>; 620defm: BoolvOpR_RR_pat<C2_xor, Xor>; 621defm: BoolvOpR_RR_pat<C2_andn, VNot2<And, pnot>>; 622defm: BoolvOpR_RR_pat<C2_orn, VNot2< Or, pnot>>; 623 624// op(Ps, op(Pt, Pu)) 625defm: BoolvAccRRR_pat<C4_and_and, And, Su<And>>; 626defm: BoolvAccRRR_pat<C4_and_or, And, Su<Or>>; 627defm: BoolvAccRRR_pat<C4_or_and, Or, Su<And>>; 628defm: BoolvAccRRR_pat<C4_or_or, Or, Su<Or>>; 629 630// op(Ps, op(Pt, !Pu)) 631defm: BoolvAccRRR_pat<C4_and_andn, And, Su<VNot2<And, pnot>>>; 632defm: BoolvAccRRR_pat<C4_and_orn, And, Su<VNot2< Or, pnot>>>; 633defm: BoolvAccRRR_pat<C4_or_andn, Or, Su<VNot2<And, pnot>>>; 634defm: BoolvAccRRR_pat<C4_or_orn, Or, Su<VNot2< Or, pnot>>>; 635 636 637// --(5) Compare --------------------------------------------------------- 638// 639 640// Avoid negated comparisons, i.e. those of form "Pd = !cmp(...)". 641// These cannot form compounds (e.g. J4_cmpeqi_tp0_jump_nt). 642 643def: OpR_RI_pat<C2_cmpeqi, seteq, i1, I32, anyimm>; 644def: OpR_RI_pat<C2_cmpgti, setgt, i1, I32, anyimm>; 645def: OpR_RI_pat<C2_cmpgtui, setugt, i1, I32, anyimm>; 646 647def: Pat<(i1 (setge I32:$Rs, s32_0ImmPred:$s10)), 648 (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10))>; 649def: Pat<(i1 (setuge I32:$Rs, u32_0ImmPred:$u9)), 650 (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9))>; 651 652def: Pat<(i1 (setlt I32:$Rs, s32_0ImmPred:$s10)), 653 (C2_not (C2_cmpgti I32:$Rs, (SDEC1 imm:$s10)))>; 654def: Pat<(i1 (setult I32:$Rs, u32_0ImmPred:$u9)), 655 (C2_not (C2_cmpgtui I32:$Rs, (UDEC1 imm:$u9)))>; 656 657// Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones 658// that reverse the order of the operands. 659class RevCmp<PatFrag F> 660 : PatFrag<(ops node:$rhs, node:$lhs), !head(F.Fragments), F.PredicateCode, 661 F.OperandTransform>; 662 663def: OpR_RR_pat<C2_cmpeq, seteq, i1, I32>; 664def: OpR_RR_pat<C2_cmpgt, setgt, i1, I32>; 665def: OpR_RR_pat<C2_cmpgtu, setugt, i1, I32>; 666def: OpR_RR_pat<C2_cmpgt, RevCmp<setlt>, i1, I32>; 667def: OpR_RR_pat<C2_cmpgtu, RevCmp<setult>, i1, I32>; 668def: OpR_RR_pat<C2_cmpeqp, seteq, i1, I64>; 669def: OpR_RR_pat<C2_cmpgtp, setgt, i1, I64>; 670def: OpR_RR_pat<C2_cmpgtup, setugt, i1, I64>; 671def: OpR_RR_pat<C2_cmpgtp, RevCmp<setlt>, i1, I64>; 672def: OpR_RR_pat<C2_cmpgtup, RevCmp<setult>, i1, I64>; 673def: OpR_RR_pat<A2_vcmpbeq, seteq, i1, V8I8>; 674def: OpR_RR_pat<A2_vcmpbeq, seteq, v8i1, V8I8>; 675def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, i1, V8I8>; 676def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, v8i1, V8I8>; 677def: OpR_RR_pat<A4_vcmpbgt, setgt, i1, V8I8>; 678def: OpR_RR_pat<A4_vcmpbgt, setgt, v8i1, V8I8>; 679def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, i1, V8I8>; 680def: OpR_RR_pat<A2_vcmpbgtu, RevCmp<setult>, v8i1, V8I8>; 681def: OpR_RR_pat<A2_vcmpbgtu, setugt, i1, V8I8>; 682def: OpR_RR_pat<A2_vcmpbgtu, setugt, v8i1, V8I8>; 683def: OpR_RR_pat<A2_vcmpheq, seteq, i1, V4I16>; 684def: OpR_RR_pat<A2_vcmpheq, seteq, v4i1, V4I16>; 685def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, i1, V4I16>; 686def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, v4i1, V4I16>; 687def: OpR_RR_pat<A2_vcmphgt, setgt, i1, V4I16>; 688def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>; 689def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, i1, V4I16>; 690def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, v4i1, V4I16>; 691def: OpR_RR_pat<A2_vcmphgtu, setugt, i1, V4I16>; 692def: OpR_RR_pat<A2_vcmphgtu, setugt, v4i1, V4I16>; 693def: OpR_RR_pat<A2_vcmpweq, seteq, i1, V2I32>; 694def: OpR_RR_pat<A2_vcmpweq, seteq, v2i1, V2I32>; 695def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, i1, V2I32>; 696def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, v2i1, V2I32>; 697def: OpR_RR_pat<A2_vcmpwgt, setgt, i1, V2I32>; 698def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>; 699def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, i1, V2I32>; 700def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, v2i1, V2I32>; 701def: OpR_RR_pat<A2_vcmpwgtu, setugt, i1, V2I32>; 702def: OpR_RR_pat<A2_vcmpwgtu, setugt, v2i1, V2I32>; 703 704def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>; 705def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>; 706def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>; 707def: OpR_RR_pat<F2_sfcmpeq, setoeq, i1, F32>; 708def: OpR_RR_pat<F2_sfcmpgt, setogt, i1, F32>; 709def: OpR_RR_pat<F2_sfcmpge, setoge, i1, F32>; 710def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setolt>, i1, F32>; 711def: OpR_RR_pat<F2_sfcmpge, RevCmp<setole>, i1, F32>; 712def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setlt>, i1, F32>; 713def: OpR_RR_pat<F2_sfcmpge, RevCmp<setle>, i1, F32>; 714def: OpR_RR_pat<F2_sfcmpuo, setuo, i1, F32>; 715 716def: OpR_RR_pat<F2_dfcmpeq, seteq, i1, F64>; 717def: OpR_RR_pat<F2_dfcmpgt, setgt, i1, F64>; 718def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>; 719def: OpR_RR_pat<F2_dfcmpeq, setoeq, i1, F64>; 720def: OpR_RR_pat<F2_dfcmpgt, setogt, i1, F64>; 721def: OpR_RR_pat<F2_dfcmpge, setoge, i1, F64>; 722def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setolt>, i1, F64>; 723def: OpR_RR_pat<F2_dfcmpge, RevCmp<setole>, i1, F64>; 724def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setlt>, i1, F64>; 725def: OpR_RR_pat<F2_dfcmpge, RevCmp<setle>, i1, F64>; 726def: OpR_RR_pat<F2_dfcmpuo, setuo, i1, F64>; 727 728// Avoid C4_cmpneqi, C4_cmpltei, C4_cmplteui, since they cannot form compounds. 729 730def: Pat<(i1 (setne I32:$Rs, anyimm:$u5)), 731 (C2_not (C2_cmpeqi I32:$Rs, imm:$u5))>; 732def: Pat<(i1 (setle I32:$Rs, anyimm:$u5)), 733 (C2_not (C2_cmpgti I32:$Rs, imm:$u5))>; 734def: Pat<(i1 (setule I32:$Rs, anyimm:$u5)), 735 (C2_not (C2_cmpgtui I32:$Rs, imm:$u5))>; 736 737class OpmR_RR_pat<PatFrag Output, PatFrag Op, ValueType ResType, 738 PatFrag RsPred, PatFrag RtPred = RsPred> 739 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)), 740 (Output RsPred:$Rs, RtPred:$Rt)>; 741 742class Outn<InstHexagon MI> 743 : OutPatFrag<(ops node:$Rs, node:$Rt), 744 (C2_not (MI $Rs, $Rt))>; 745 746def: OpmR_RR_pat<Outn<C2_cmpeq>, setne, i1, I32>; 747def: OpmR_RR_pat<Outn<C2_cmpgt>, setle, i1, I32>; 748def: OpmR_RR_pat<Outn<C2_cmpgtu>, setule, i1, I32>; 749def: OpmR_RR_pat<Outn<C2_cmpgt>, RevCmp<setge>, i1, I32>; 750def: OpmR_RR_pat<Outn<C2_cmpgtu>, RevCmp<setuge>, i1, I32>; 751def: OpmR_RR_pat<Outn<C2_cmpeqp>, setne, i1, I64>; 752def: OpmR_RR_pat<Outn<C2_cmpgtp>, setle, i1, I64>; 753def: OpmR_RR_pat<Outn<C2_cmpgtup>, setule, i1, I64>; 754def: OpmR_RR_pat<Outn<C2_cmpgtp>, RevCmp<setge>, i1, I64>; 755def: OpmR_RR_pat<Outn<C2_cmpgtup>, RevCmp<setuge>, i1, I64>; 756def: OpmR_RR_pat<Outn<A2_vcmpbeq>, setne, v8i1, V8I8>; 757def: OpmR_RR_pat<Outn<A4_vcmpbgt>, setle, v8i1, V8I8>; 758def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, setule, v8i1, V8I8>; 759def: OpmR_RR_pat<Outn<A4_vcmpbgt>, RevCmp<setge>, v8i1, V8I8>; 760def: OpmR_RR_pat<Outn<A2_vcmpbgtu>, RevCmp<setuge>, v8i1, V8I8>; 761def: OpmR_RR_pat<Outn<A2_vcmpheq>, setne, v4i1, V4I16>; 762def: OpmR_RR_pat<Outn<A2_vcmphgt>, setle, v4i1, V4I16>; 763def: OpmR_RR_pat<Outn<A2_vcmphgtu>, setule, v4i1, V4I16>; 764def: OpmR_RR_pat<Outn<A2_vcmphgt>, RevCmp<setge>, v4i1, V4I16>; 765def: OpmR_RR_pat<Outn<A2_vcmphgtu>, RevCmp<setuge>, v4i1, V4I16>; 766def: OpmR_RR_pat<Outn<A2_vcmpweq>, setne, v2i1, V2I32>; 767def: OpmR_RR_pat<Outn<A2_vcmpwgt>, setle, v2i1, V2I32>; 768def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, setule, v2i1, V2I32>; 769def: OpmR_RR_pat<Outn<A2_vcmpwgt>, RevCmp<setge>, v2i1, V2I32>; 770def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, RevCmp<setuge>, v2i1, V2I32>; 771 772let AddedComplexity = 100 in { 773 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 255), 0)), 774 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>; 775 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 255), 0)), 776 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>; 777 def: Pat<(i1 (seteq (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 778 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>; 779 def: Pat<(i1 (setne (and (xor I32:$Rs, I32:$Rt), 65535), 0)), 780 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>; 781} 782 783// PatFrag for AsserZext which takes the original type as a parameter. 784def SDTAssertZext: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,1>]>; 785def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>; 786class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>; 787 788multiclass Cmpb_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 789 PatLeaf ImmPred, int Mask> { 790 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 791 (MI I32:$Rs, imm:$I)>; 792 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 793 (MI I32:$Rs, imm:$I)>; 794} 795 796multiclass CmpbN_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 797 PatLeaf ImmPred, int Mask> { 798 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 799 (C2_not (MI I32:$Rs, imm:$I))>; 800 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 801 (C2_not (MI I32:$Rs, imm:$I))>; 802} 803 804multiclass CmpbND_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt, 805 PatLeaf ImmPred, int Mask> { 806 def: Pat<(i1 (Op (and I32:$Rs, Mask), ImmPred:$I)), 807 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 808 def: Pat<(i1 (Op (AssertExt I32:$Rs), ImmPred:$I)), 809 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>; 810} 811 812let AddedComplexity = 200 in { 813 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>; 814 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>; 815 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>; 816 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>; 817 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>; 818 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>; 819 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>; 820 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>; 821} 822 823def: Pat<(i32 (zext (i1 (seteq I32:$Rs, I32:$Rt)))), 824 (A4_rcmpeq I32:$Rs, I32:$Rt)>; 825def: Pat<(i32 (zext (i1 (setne I32:$Rs, I32:$Rt)))), 826 (A4_rcmpneq I32:$Rs, I32:$Rt)>; 827def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))), 828 (A4_rcmpeqi I32:$Rs, imm:$s8)>; 829def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))), 830 (A4_rcmpneqi I32:$Rs, imm:$s8)>; 831 832def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>; 833def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>; 834def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, (C2_not I1:$Pt))>; 835def: Pat<(i1 (setne I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>; 836 837// Floating-point comparisons with checks for ordered/unordered status. 838 839class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3> 840 : OutPatFrag<(ops node:$Rs, node:$Rt), 841 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>; 842 843class Cmpuf<InstHexagon MI>: T3<C2_or, F2_sfcmpuo, MI>; 844class Cmpud<InstHexagon MI>: T3<C2_or, F2_dfcmpuo, MI>; 845 846class Cmpufn<InstHexagon MI>: T3<C2_orn, F2_sfcmpuo, MI>; 847class Cmpudn<InstHexagon MI>: T3<C2_orn, F2_dfcmpuo, MI>; 848 849def: OpmR_RR_pat<Cmpuf<F2_sfcmpeq>, setueq, i1, F32>; 850def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, setuge, i1, F32>; 851def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, setugt, i1, F32>; 852def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, RevCmp<setule>, i1, F32>; 853def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, RevCmp<setult>, i1, F32>; 854def: OpmR_RR_pat<Cmpufn<F2_sfcmpeq>, setune, i1, F32>; 855 856def: OpmR_RR_pat<Cmpud<F2_dfcmpeq>, setueq, i1, F64>; 857def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, setuge, i1, F64>; 858def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, setugt, i1, F64>; 859def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, RevCmp<setule>, i1, F64>; 860def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, RevCmp<setult>, i1, F64>; 861def: OpmR_RR_pat<Cmpudn<F2_dfcmpeq>, setune, i1, F64>; 862 863def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setone, i1, F32>; 864def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setne, i1, F32>; 865 866def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setone, i1, F64>; 867def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setne, i1, F64>; 868 869def: OpmR_RR_pat<Outn<F2_sfcmpuo>, seto, i1, F32>; 870def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto, i1, F64>; 871 872 873// --(6) Select ---------------------------------------------------------- 874// 875 876def: Pat<(select I1:$Pu, I32:$Rs, I32:$Rt), 877 (C2_mux I1:$Pu, I32:$Rs, I32:$Rt)>; 878def: Pat<(select I1:$Pu, v4i8:$Rs, v4i8:$Rt), 879 (C2_mux I1:$Pu, v4i8:$Rs, v4i8:$Rt)>; 880def: Pat<(select I1:$Pu, v2i16:$Rs, v2i16:$Rt), 881 (C2_mux I1:$Pu, v2i16:$Rs, v2i16:$Rt)>; 882def: Pat<(select I1:$Pu, anyimm:$s8, I32:$Rs), 883 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 884def: Pat<(select I1:$Pu, I32:$Rs, anyimm:$s8), 885 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 886def: Pat<(select I1:$Pu, anyimm:$s8, s8_0ImmPred:$S8), 887 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 888 889def: Pat<(select (not I1:$Pu), I32:$Rs, I32:$Rt), 890 (C2_mux I1:$Pu, I32:$Rt, I32:$Rs)>; 891def: Pat<(select (not I1:$Pu), s8_0ImmPred:$S8, anyimm:$s8), 892 (C2_muxii I1:$Pu, imm:$s8, imm:$S8)>; 893def: Pat<(select (not I1:$Pu), anyimm:$s8, I32:$Rs), 894 (C2_muxir I1:$Pu, I32:$Rs, imm:$s8)>; 895def: Pat<(select (not I1:$Pu), I32:$Rs, anyimm:$s8), 896 (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; 897 898// Map from a 64-bit select to an emulated 64-bit mux. 899// Hexagon does not support 64-bit MUXes; so emulate with combines. 900def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt), 901 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 902 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 903 904def: Pat<(select I1:$Pu, v2i32:$Rs, v2i32:$Rt), 905 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 906 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 907 908def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I), 909 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 910def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt), 911 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 912def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt), 913 (C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>; 914def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt), 915 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), 916 (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; 917 918def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt), 919 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>; 920def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt), 921 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>; 922 923def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs), 924 (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; 925def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I), 926 (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; 927 928def: Pat<(vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt), 929 (C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>; 930def: Pat<(vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt), 931 (C2_vmux V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)>; 932def: Pat<(vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt), 933 (C2_vmux V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)>; 934 935def: Pat<(vselect (pnot V8I1:$Pu), V8I8:$Rs, V8I8:$Rt), 936 (C2_vmux V8I1:$Pu, V8I8:$Rt, V8I8:$Rs)>; 937def: Pat<(vselect (pnot V4I1:$Pu), V4I16:$Rs, V4I16:$Rt), 938 (C2_vmux V4I1:$Pu, V4I16:$Rt, V4I16:$Rs)>; 939def: Pat<(vselect (pnot V2I1:$Pu), V2I32:$Rs, V2I32:$Rt), 940 (C2_vmux V2I1:$Pu, V2I32:$Rt, V2I32:$Rs)>; 941 942 943// From LegalizeDAG.cpp: (Pu ? Pv : Pw) <=> (Pu & Pv) | (!Pu & Pw). 944def: Pat<(select I1:$Pu, I1:$Pv, I1:$Pw), 945 (C2_or (C2_and I1:$Pu, I1:$Pv), 946 (C2_andn I1:$Pw, I1:$Pu))>; 947 948 949def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{ 950 return isPositiveHalfWord(N); 951}]>; 952 953multiclass SelMinMax16_pats<PatFrag CmpOp, InstHexagon InstA, 954 InstHexagon InstB> { 955 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 956 IsPosHalf:$Rs, IsPosHalf:$Rt), i16), 957 (InstA IntRegs:$Rs, IntRegs:$Rt)>; 958 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)), 959 IsPosHalf:$Rt, IsPosHalf:$Rs), i16), 960 (InstB IntRegs:$Rs, IntRegs:$Rt)>; 961} 962 963let AddedComplexity = 200 in { 964 defm: SelMinMax16_pats<setge, A2_max, A2_min>; 965 defm: SelMinMax16_pats<setgt, A2_max, A2_min>; 966 defm: SelMinMax16_pats<setle, A2_min, A2_max>; 967 defm: SelMinMax16_pats<setlt, A2_min, A2_max>; 968 defm: SelMinMax16_pats<setuge, A2_maxu, A2_minu>; 969 defm: SelMinMax16_pats<setugt, A2_maxu, A2_minu>; 970 defm: SelMinMax16_pats<setule, A2_minu, A2_maxu>; 971 defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>; 972} 973 974def: OpR_RR_pat<A2_min, Smin, i32, I32, I32>; 975def: OpR_RR_pat<A2_max, Smax, i32, I32, I32>; 976def: OpR_RR_pat<A2_minu, Umin, i32, I32, I32>; 977def: OpR_RR_pat<A2_maxu, Umax, i32, I32, I32>; 978def: OpR_RR_pat<A2_minp, Smin, i64, I64, I64>; 979def: OpR_RR_pat<A2_maxp, Smax, i64, I64, I64>; 980def: OpR_RR_pat<A2_minup, Umin, i64, I64, I64>; 981def: OpR_RR_pat<A2_maxup, Umax, i64, I64, I64>; 982 983let AddedComplexity = 100 in { 984 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setogt, i1, F32>; 985 defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setoge, i1, F32>; 986 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setolt, i1, F32>; 987 defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setole, i1, F32>; 988} 989 990let AddedComplexity = 100, Predicates = [HasV67] in { 991 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setogt, i1, F64>; 992 defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setoge, i1, F64>; 993 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setolt, i1, F64>; 994 defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setole, i1, F64>; 995} 996 997def: OpR_RR_pat<A2_vminb, Smin, v8i8, V8I8>; 998def: OpR_RR_pat<A2_vmaxb, Smax, v8i8, V8I8>; 999def: OpR_RR_pat<A2_vminub, Umin, v8i8, V8I8>; 1000def: OpR_RR_pat<A2_vmaxub, Umax, v8i8, V8I8>; 1001 1002def: OpR_RR_pat<A2_vminh, Smin, v4i16, V4I16>; 1003def: OpR_RR_pat<A2_vmaxh, Smax, v4i16, V4I16>; 1004def: OpR_RR_pat<A2_vminuh, Umin, v4i16, V4I16>; 1005def: OpR_RR_pat<A2_vmaxuh, Umax, v4i16, V4I16>; 1006 1007def: OpR_RR_pat<A2_vminw, Smin, v2i32, V2I32>; 1008def: OpR_RR_pat<A2_vmaxw, Smax, v2i32, V2I32>; 1009def: OpR_RR_pat<A2_vminuw, Umin, v2i32, V2I32>; 1010def: OpR_RR_pat<A2_vmaxuw, Umax, v2i32, V2I32>; 1011 1012// --(7) Insert/extract -------------------------------------------------- 1013// 1014 1015def SDTHexagonINSERT: 1016 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 1017 SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>; 1018def HexagonINSERT: SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>; 1019 1020let AddedComplexity = 10 in { 1021 def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2), 1022 (S2_insert I32:$Rs, I32:$Rt, imm:$u1, imm:$u2)>; 1023 def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2), 1024 (S2_insertp I64:$Rs, I64:$Rt, imm:$u1, imm:$u2)>; 1025} 1026def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, I32:$Width, I32:$Off), 1027 (S2_insert_rp I32:$Rs, I32:$Rt, (Combinew $Width, $Off))>; 1028def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, I32:$Width, I32:$Off), 1029 (S2_insertp_rp I64:$Rs, I64:$Rt, (Combinew $Width, $Off))>; 1030 1031def SDTHexagonEXTRACTU 1032 : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>, 1033 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 1034def HexagonEXTRACTU: SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>; 1035 1036let AddedComplexity = 10 in { 1037 def: Pat<(HexagonEXTRACTU I32:$Rs, u5_0ImmPred:$u5, u5_0ImmPred:$U5), 1038 (S2_extractu I32:$Rs, imm:$u5, imm:$U5)>; 1039 def: Pat<(HexagonEXTRACTU I64:$Rs, u6_0ImmPred:$u6, u6_0ImmPred:$U6), 1040 (S2_extractup I64:$Rs, imm:$u6, imm:$U6)>; 1041} 1042def: Pat<(HexagonEXTRACTU I32:$Rs, I32:$Width, I32:$Off), 1043 (S2_extractu_rp I32:$Rs, (Combinew $Width, $Off))>; 1044def: Pat<(HexagonEXTRACTU I64:$Rs, I32:$Width, I32:$Off), 1045 (S2_extractup_rp I64:$Rs, (Combinew $Width, $Off))>; 1046 1047def: Pat<(v4i8 (splat_vector anyint:$V)), (ToI32 (SplatB $V))>; 1048def: Pat<(v2i16 (splat_vector anyint:$V)), (ToI32 (SplatH $V))>; 1049def: Pat<(v8i8 (splat_vector anyint:$V)), 1050 (Combinew (ToI32 (SplatB $V)), (ToI32 (SplatB $V)))>; 1051def: Pat<(v4i16 (splat_vector anyint:$V)), 1052 (Combinew (ToI32 (SplatH $V)), (ToI32 (SplatH $V)))>; 1053let AddedComplexity = 10 in 1054def: Pat<(v2i32 (splat_vector s8_0ImmPred:$s8)), 1055 (A2_combineii imm:$s8, imm:$s8)>; 1056def: Pat<(v2i32 (splat_vector anyimm:$V)), (Combinew (ToI32 $V), (ToI32 $V))>; 1057 1058def: Pat<(v4i8 (splat_vector I32:$Rs)), (S2_vsplatrb I32:$Rs)>; 1059def: Pat<(v2i16 (splat_vector I32:$Rs)), (LoReg (S2_vsplatrh I32:$Rs))>; 1060def: Pat<(v4i16 (splat_vector I32:$Rs)), (S2_vsplatrh I32:$Rs)>; 1061def: Pat<(v2i32 (splat_vector I32:$Rs)), (Combinew I32:$Rs, I32:$Rs)>; 1062 1063let AddedComplexity = 10 in 1064def: Pat<(v8i8 (splat_vector I32:$Rs)), (S6_vsplatrbp I32:$Rs)>, 1065 Requires<[HasV62]>; 1066def: Pat<(v8i8 (splat_vector I32:$Rs)), 1067 (Combinew (S2_vsplatrb I32:$Rs), (S2_vsplatrb I32:$Rs))>; 1068 1069let AddedComplexity = 10 in { 1070 def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 8, u5_0ImmPred:$U5), i8), 1071 (S4_extract I32:$Rs, 8, imm:$U5)>; 1072 def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 16, u5_0ImmPred:$U5), i16), 1073 (S4_extract I32:$Rs, 16, imm:$U5)>; 1074 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 8, u6_0ImmPred:$U6), i8), 1075 (S4_extractp I64:$Rs, 8, imm:$U6)>; 1076 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 16, u6_0ImmPred:$U6), i16), 1077 (S4_extractp I64:$Rs, 16, imm:$U6)>; 1078 def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 32, u6_0ImmPred:$U6), i32), 1079 (S4_extractp I64:$Rs, 32, imm:$U6)>; 1080} 1081 1082def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 8, I32:$Off), i8), 1083 (S4_extract_rp I32:$Rs, (Combinew (ToI32 8), I32:$Off))>; 1084def: Pat<(sext_inreg (HexagonEXTRACTU I32:$Rs, 16, I32:$Off), i16), 1085 (S4_extract_rp I32:$Rs, (Combinew (ToI32 16), I32:$Off))>; 1086def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 8, I32:$Off), i8), 1087 (S4_extractp_rp I64:$Rs, (Combinew (ToI32 8), I32:$Off))>; 1088def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 16, I32:$Off), i16), 1089 (S4_extractp_rp I64:$Rs, (Combinew (ToI32 16), I32:$Off))>; 1090def: Pat<(sext_inreg (HexagonEXTRACTU I64:$Rs, 32, I32:$Off), i32), 1091 (S4_extractp_rp I64:$Rs, (Combinew (ToI32 32), I32:$Off))>; 1092 1093 1094// --(8) Shift/permute --------------------------------------------------- 1095// 1096 1097def SDTHexagonI64I32I32: SDTypeProfile<1, 2, 1098 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 1099 1100def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>; 1101 1102def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>; 1103 1104// The complexity of the combines involving immediates should be greater 1105// than the complexity of the combine with two registers. 1106let AddedComplexity = 50 in { 1107 def: Pat<(HexagonCOMBINE I32:$Rs, anyimm:$s8), 1108 (A4_combineri IntRegs:$Rs, imm:$s8)>; 1109 def: Pat<(HexagonCOMBINE anyimm:$s8, I32:$Rs), 1110 (A4_combineir imm:$s8, IntRegs:$Rs)>; 1111} 1112 1113// The complexity of the combine with two immediates should be greater than 1114// the complexity of a combine involving a register. 1115let AddedComplexity = 75 in { 1116 def: Pat<(HexagonCOMBINE s8_0ImmPred:$s8, anyimm:$u6), 1117 (A4_combineii imm:$s8, imm:$u6)>; 1118 def: Pat<(HexagonCOMBINE anyimm:$s8, s8_0ImmPred:$S8), 1119 (A2_combineii imm:$s8, imm:$S8)>; 1120} 1121 1122def: Pat<(bswap I32:$Rs), (A2_swiz I32:$Rs)>; 1123def: Pat<(bswap I64:$Rss), (Combinew (A2_swiz (LoReg $Rss)), 1124 (A2_swiz (HiReg $Rss)))>; 1125 1126def: Pat<(bswap V2I16:$Rs), (A2_combine_lh (A2_swiz $Rs), (A2_swiz $Rs))>; 1127def: Pat<(bswap V2I32:$Rs), (Combinew (A2_swiz (HiReg $Rs)), 1128 (A2_swiz (LoReg $Rs)))>; 1129def: Pat<(bswap V4I16:$Rs), (A2_orp (S2_lsr_i_vh $Rs, 8), 1130 (S2_asl_i_vh $Rs, 8))>; 1131 1132def: Pat<(shl s6_0ImmPred:$s6, I32:$Rt), (S4_lsli imm:$s6, I32:$Rt)>; 1133def: Pat<(shl I32:$Rs, (i32 16)), (A2_aslh I32:$Rs)>; 1134def: Pat<(sra I32:$Rs, (i32 16)), (A2_asrh I32:$Rs)>; 1135 1136def: OpR_RI_pat<S2_asr_i_r, Sra, i32, I32, u5_0ImmPred>; 1137def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>; 1138def: OpR_RI_pat<S2_asl_i_r, Shl, i32, I32, u5_0ImmPred>; 1139def: OpR_RI_pat<S2_asr_i_p, Sra, i64, I64, u6_0ImmPred>; 1140def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>; 1141def: OpR_RI_pat<S2_asl_i_p, Shl, i64, I64, u6_0ImmPred>; 1142def: OpR_RI_pat<S2_asr_i_vh, Sra, v4i16, V4I16, u4_0ImmPred>; 1143def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>; 1144def: OpR_RI_pat<S2_asl_i_vh, Shl, v4i16, V4I16, u4_0ImmPred>; 1145def: OpR_RI_pat<S2_asr_i_vh, Sra, v2i32, V2I32, u5_0ImmPred>; 1146def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>; 1147def: OpR_RI_pat<S2_asl_i_vh, Shl, v2i32, V2I32, u5_0ImmPred>; 1148 1149def: OpR_RR_pat<S2_asr_r_r, Sra, i32, I32, I32>; 1150def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>; 1151def: OpR_RR_pat<S2_asl_r_r, Shl, i32, I32, I32>; 1152def: OpR_RR_pat<S2_asr_r_p, Sra, i64, I64, I32>; 1153def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>; 1154def: OpR_RR_pat<S2_asl_r_p, Shl, i64, I64, I32>; 1155 1156// Funnel shifts. 1157def IsMul8_U3: PatLeaf<(i32 imm), [{ 1158 uint64_t V = N->getZExtValue(); 1159 return V % 8 == 0 && isUInt<3>(V / 8); 1160}]>; 1161 1162def Divu8: SDNodeXForm<imm, [{ 1163 return CurDAG->getTargetConstant(N->getZExtValue() / 8, SDLoc(N), MVT::i32); 1164}]>; 1165 1166// Funnel shift-left. 1167def FShl32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1168 (HiReg (S2_asl_i_p (Combinew $Rs, $Rt), $S))>; 1169def FShl32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1170 (HiReg (S2_asl_r_p (Combinew $Rs, $Rt), $Ru))>; 1171 1172def FShl64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1173 (S2_lsr_i_p_or (S2_asl_i_p $Rs, $S), $Rt, (Subi<64> $S))>; 1174def FShl64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1175 (S2_lsr_r_p_or (S2_asl_r_p $Rs, $Ru), $Rt, (A2_subri 64, $Ru))>; 1176 1177// Combined SDNodeXForm: (Divu8 (Subi<64> $S)) 1178def Divu64_8: SDNodeXForm<imm, [{ 1179 return CurDAG->getTargetConstant((64 - N->getSExtValue()) / 8, 1180 SDLoc(N), MVT::i32); 1181}]>; 1182 1183// Special cases: 1184let AddedComplexity = 100 in { 1185 def: Pat<(fshl I32:$Rs, I32:$Rt, (i32 16)), 1186 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1187 def: Pat<(fshl I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1188 (S2_valignib I64:$Rs, I64:$Rt, (Divu64_8 $S))>; 1189} 1190 1191let Predicates = [HasV60], AddedComplexity = 50 in { 1192 def: OpR_RI_pat<S6_rol_i_r, Rol, i32, I32, u5_0ImmPred>; 1193 def: OpR_RI_pat<S6_rol_i_p, Rol, i64, I64, u6_0ImmPred>; 1194} 1195let AddedComplexity = 30 in { 1196 def: Pat<(rotl I32:$Rs, u5_0ImmPred:$S), (FShl32i $Rs, $Rs, imm:$S)>; 1197 def: Pat<(rotl I64:$Rs, u6_0ImmPred:$S), (FShl64i $Rs, $Rs, imm:$S)>; 1198 def: Pat<(fshl I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShl32i $Rs, $Rt, imm:$S)>; 1199 def: Pat<(fshl I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShl64i $Rs, $Rt, imm:$S)>; 1200} 1201def: Pat<(rotl I32:$Rs, I32:$Rt), (FShl32r $Rs, $Rs, $Rt)>; 1202def: Pat<(rotl I64:$Rs, I32:$Rt), (FShl64r $Rs, $Rs, $Rt)>; 1203def: Pat<(fshl I32:$Rs, I32:$Rt, I32:$Ru), (FShl32r $Rs, $Rt, $Ru)>; 1204def: Pat<(fshl I64:$Rs, I64:$Rt, I32:$Ru), (FShl64r $Rs, $Rt, $Ru)>; 1205 1206// Funnel shift-right. 1207def FShr32i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1208 (LoReg (S2_lsr_i_p (Combinew $Rs, $Rt), $S))>; 1209def FShr32r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1210 (LoReg (S2_lsr_r_p (Combinew $Rs, $Rt), $Ru))>; 1211 1212def FShr64i: OutPatFrag<(ops node:$Rs, node:$Rt, node:$S), 1213 (S2_asl_i_p_or (S2_lsr_i_p $Rt, $S), $Rs, (Subi<64> $S))>; 1214def FShr64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru), 1215 (S2_asl_r_p_or (S2_lsr_r_p $Rt, $Ru), $Rs, (A2_subri 64, $Ru))>; 1216 1217// Special cases: 1218let AddedComplexity = 100 in { 1219 def: Pat<(fshr I32:$Rs, I32:$Rt, (i32 16)), 1220 (A2_combine_lh I32:$Rs, I32:$Rt)>; 1221 def: Pat<(fshr I64:$Rs, I64:$Rt, IsMul8_U3:$S), 1222 (S2_valignib I64:$Rs, I64:$Rt, (Divu8 $S))>; 1223} 1224 1225let Predicates = [HasV60], AddedComplexity = 50 in { 1226 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (S6_rol_i_r I32:$Rs, (Subi<32> $S))>; 1227 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (S6_rol_i_p I64:$Rs, (Subi<64> $S))>; 1228} 1229let AddedComplexity = 30 in { 1230 def: Pat<(rotr I32:$Rs, u5_0ImmPred:$S), (FShr32i $Rs, $Rs, imm:$S)>; 1231 def: Pat<(rotr I64:$Rs, u6_0ImmPred:$S), (FShr64i $Rs, $Rs, imm:$S)>; 1232 def: Pat<(fshr I32:$Rs, I32:$Rt, u5_0ImmPred:$S), (FShr32i $Rs, $Rt, imm:$S)>; 1233 def: Pat<(fshr I64:$Rs, I64:$Rt, u6_0ImmPred:$S), (FShr64i $Rs, $Rt, imm:$S)>; 1234} 1235def: Pat<(rotr I32:$Rs, I32:$Rt), (FShr32r $Rs, $Rs, $Rt)>; 1236def: Pat<(rotr I64:$Rs, I32:$Rt), (FShr64r $Rs, $Rs, $Rt)>; 1237def: Pat<(fshr I32:$Rs, I32:$Rt, I32:$Ru), (FShr32r $Rs, $Rt, $Ru)>; 1238def: Pat<(fshr I64:$Rs, I64:$Rt, I32:$Ru), (FShr64r $Rs, $Rt, $Ru)>; 1239 1240 1241def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)), 1242 (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>; 1243def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)), 1244 (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>; 1245 1246// Prefer S2_addasl_rrri over S2_asl_i_r_acc. 1247let AddedComplexity = 120 in 1248def: Pat<(add I32:$Rt, (shl I32:$Rs, u3_0ImmPred:$u3)), 1249 (S2_addasl_rrri IntRegs:$Rt, IntRegs:$Rs, imm:$u3)>; 1250 1251let AddedComplexity = 100 in { 1252 def: AccRRI_pat<S2_asr_i_r_acc, Add, Su<Sra>, I32, u5_0ImmPred>; 1253 def: AccRRI_pat<S2_asr_i_r_nac, Sub, Su<Sra>, I32, u5_0ImmPred>; 1254 def: AccRRI_pat<S2_asr_i_r_and, And, Su<Sra>, I32, u5_0ImmPred>; 1255 def: AccRRI_pat<S2_asr_i_r_or, Or, Su<Sra>, I32, u5_0ImmPred>; 1256 1257 def: AccRRI_pat<S2_asr_i_p_acc, Add, Su<Sra>, I64, u6_0ImmPred>; 1258 def: AccRRI_pat<S2_asr_i_p_nac, Sub, Su<Sra>, I64, u6_0ImmPred>; 1259 def: AccRRI_pat<S2_asr_i_p_and, And, Su<Sra>, I64, u6_0ImmPred>; 1260 def: AccRRI_pat<S2_asr_i_p_or, Or, Su<Sra>, I64, u6_0ImmPred>; 1261 1262 def: AccRRI_pat<S2_lsr_i_r_acc, Add, Su<Srl>, I32, u5_0ImmPred>; 1263 def: AccRRI_pat<S2_lsr_i_r_nac, Sub, Su<Srl>, I32, u5_0ImmPred>; 1264 def: AccRRI_pat<S2_lsr_i_r_and, And, Su<Srl>, I32, u5_0ImmPred>; 1265 def: AccRRI_pat<S2_lsr_i_r_or, Or, Su<Srl>, I32, u5_0ImmPred>; 1266 def: AccRRI_pat<S2_lsr_i_r_xacc, Xor, Su<Srl>, I32, u5_0ImmPred>; 1267 1268 def: AccRRI_pat<S2_lsr_i_p_acc, Add, Su<Srl>, I64, u6_0ImmPred>; 1269 def: AccRRI_pat<S2_lsr_i_p_nac, Sub, Su<Srl>, I64, u6_0ImmPred>; 1270 def: AccRRI_pat<S2_lsr_i_p_and, And, Su<Srl>, I64, u6_0ImmPred>; 1271 def: AccRRI_pat<S2_lsr_i_p_or, Or, Su<Srl>, I64, u6_0ImmPred>; 1272 def: AccRRI_pat<S2_lsr_i_p_xacc, Xor, Su<Srl>, I64, u6_0ImmPred>; 1273 1274 def: AccRRI_pat<S2_asl_i_r_acc, Add, Su<Shl>, I32, u5_0ImmPred>; 1275 def: AccRRI_pat<S2_asl_i_r_nac, Sub, Su<Shl>, I32, u5_0ImmPred>; 1276 def: AccRRI_pat<S2_asl_i_r_and, And, Su<Shl>, I32, u5_0ImmPred>; 1277 def: AccRRI_pat<S2_asl_i_r_or, Or, Su<Shl>, I32, u5_0ImmPred>; 1278 def: AccRRI_pat<S2_asl_i_r_xacc, Xor, Su<Shl>, I32, u5_0ImmPred>; 1279 1280 def: AccRRI_pat<S2_asl_i_p_acc, Add, Su<Shl>, I64, u6_0ImmPred>; 1281 def: AccRRI_pat<S2_asl_i_p_nac, Sub, Su<Shl>, I64, u6_0ImmPred>; 1282 def: AccRRI_pat<S2_asl_i_p_and, And, Su<Shl>, I64, u6_0ImmPred>; 1283 def: AccRRI_pat<S2_asl_i_p_or, Or, Su<Shl>, I64, u6_0ImmPred>; 1284 def: AccRRI_pat<S2_asl_i_p_xacc, Xor, Su<Shl>, I64, u6_0ImmPred>; 1285 1286 let Predicates = [HasV60] in { 1287 def: AccRRI_pat<S6_rol_i_r_acc, Add, Su<Rol>, I32, u5_0ImmPred>; 1288 def: AccRRI_pat<S6_rol_i_r_nac, Sub, Su<Rol>, I32, u5_0ImmPred>; 1289 def: AccRRI_pat<S6_rol_i_r_and, And, Su<Rol>, I32, u5_0ImmPred>; 1290 def: AccRRI_pat<S6_rol_i_r_or, Or, Su<Rol>, I32, u5_0ImmPred>; 1291 def: AccRRI_pat<S6_rol_i_r_xacc, Xor, Su<Rol>, I32, u5_0ImmPred>; 1292 1293 def: AccRRI_pat<S6_rol_i_p_acc, Add, Su<Rol>, I64, u6_0ImmPred>; 1294 def: AccRRI_pat<S6_rol_i_p_nac, Sub, Su<Rol>, I64, u6_0ImmPred>; 1295 def: AccRRI_pat<S6_rol_i_p_and, And, Su<Rol>, I64, u6_0ImmPred>; 1296 def: AccRRI_pat<S6_rol_i_p_or, Or, Su<Rol>, I64, u6_0ImmPred>; 1297 def: AccRRI_pat<S6_rol_i_p_xacc, Xor, Su<Rol>, I64, u6_0ImmPred>; 1298 } 1299} 1300 1301let AddedComplexity = 100 in { 1302 def: AccRRR_pat<S2_asr_r_r_acc, Add, Su<Sra>, I32, I32, I32>; 1303 def: AccRRR_pat<S2_asr_r_r_nac, Sub, Su<Sra>, I32, I32, I32>; 1304 def: AccRRR_pat<S2_asr_r_r_and, And, Su<Sra>, I32, I32, I32>; 1305 def: AccRRR_pat<S2_asr_r_r_or, Or, Su<Sra>, I32, I32, I32>; 1306 1307 def: AccRRR_pat<S2_asr_r_p_acc, Add, Su<Sra>, I64, I64, I32>; 1308 def: AccRRR_pat<S2_asr_r_p_nac, Sub, Su<Sra>, I64, I64, I32>; 1309 def: AccRRR_pat<S2_asr_r_p_and, And, Su<Sra>, I64, I64, I32>; 1310 def: AccRRR_pat<S2_asr_r_p_or, Or, Su<Sra>, I64, I64, I32>; 1311 def: AccRRR_pat<S2_asr_r_p_xor, Xor, Su<Sra>, I64, I64, I32>; 1312 1313 def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32, I32>; 1314 def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32, I32>; 1315 def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32, I32>; 1316 def: AccRRR_pat<S2_lsr_r_r_or, Or, Su<Srl>, I32, I32, I32>; 1317 1318 def: AccRRR_pat<S2_lsr_r_p_acc, Add, Su<Srl>, I64, I64, I32>; 1319 def: AccRRR_pat<S2_lsr_r_p_nac, Sub, Su<Srl>, I64, I64, I32>; 1320 def: AccRRR_pat<S2_lsr_r_p_and, And, Su<Srl>, I64, I64, I32>; 1321 def: AccRRR_pat<S2_lsr_r_p_or, Or, Su<Srl>, I64, I64, I32>; 1322 def: AccRRR_pat<S2_lsr_r_p_xor, Xor, Su<Srl>, I64, I64, I32>; 1323 1324 def: AccRRR_pat<S2_asl_r_r_acc, Add, Su<Shl>, I32, I32, I32>; 1325 def: AccRRR_pat<S2_asl_r_r_nac, Sub, Su<Shl>, I32, I32, I32>; 1326 def: AccRRR_pat<S2_asl_r_r_and, And, Su<Shl>, I32, I32, I32>; 1327 def: AccRRR_pat<S2_asl_r_r_or, Or, Su<Shl>, I32, I32, I32>; 1328 1329 def: AccRRR_pat<S2_asl_r_p_acc, Add, Su<Shl>, I64, I64, I32>; 1330 def: AccRRR_pat<S2_asl_r_p_nac, Sub, Su<Shl>, I64, I64, I32>; 1331 def: AccRRR_pat<S2_asl_r_p_and, And, Su<Shl>, I64, I64, I32>; 1332 def: AccRRR_pat<S2_asl_r_p_or, Or, Su<Shl>, I64, I64, I32>; 1333 def: AccRRR_pat<S2_asl_r_p_xor, Xor, Su<Shl>, I64, I64, I32>; 1334} 1335 1336 1337class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp, 1338 PatFrag RegPred, PatFrag ImmPred> 1339 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)), 1340 (MI anyimm:$u8, RegPred:$Rs, imm:$U5)>; 1341 1342let AddedComplexity = 200, Predicates = [UseCompound] in { 1343 def: OpshIRI_pat<S4_addi_asl_ri, Add, Su<Shl>, I32, u5_0ImmPred>; 1344 def: OpshIRI_pat<S4_addi_lsr_ri, Add, Su<Srl>, I32, u5_0ImmPred>; 1345 def: OpshIRI_pat<S4_subi_asl_ri, Sub, Su<Shl>, I32, u5_0ImmPred>; 1346 def: OpshIRI_pat<S4_subi_lsr_ri, Sub, Su<Srl>, I32, u5_0ImmPred>; 1347 def: OpshIRI_pat<S4_andi_asl_ri, And, Su<Shl>, I32, u5_0ImmPred>; 1348 def: OpshIRI_pat<S4_andi_lsr_ri, And, Su<Srl>, I32, u5_0ImmPred>; 1349 def: OpshIRI_pat<S4_ori_asl_ri, Or, Su<Shl>, I32, u5_0ImmPred>; 1350 def: OpshIRI_pat<S4_ori_lsr_ri, Or, Su<Srl>, I32, u5_0ImmPred>; 1351} 1352 1353// Prefer this pattern to S2_asl_i_p_or for the special case of joining 1354// two 32-bit words into a 64-bit word. 1355let AddedComplexity = 200 in 1356def: Pat<(or (shl (Aext64 I32:$a), (i32 32)), (Zext64 I32:$b)), 1357 (Combinew I32:$a, I32:$b)>; 1358 1359def: Pat<(or (or (or (shl (Zext64 (and I32:$b, (i32 65535))), (i32 16)), 1360 (Zext64 (and I32:$a, (i32 65535)))), 1361 (shl (Aext64 (and I32:$c, (i32 65535))), (i32 32))), 1362 (shl (Aext64 I32:$d), (i32 48))), 1363 (Combinew (A2_combine_ll I32:$d, I32:$c), 1364 (A2_combine_ll I32:$b, I32:$a))>; 1365 1366let AddedComplexity = 200 in { 1367 def: Pat<(or (shl I32:$Rt, (i32 16)), (and I32:$Rs, (i32 65535))), 1368 (A2_combine_ll I32:$Rt, I32:$Rs)>; 1369 def: Pat<(or (shl I32:$Rt, (i32 16)), (srl I32:$Rs, (i32 16))), 1370 (A2_combine_lh I32:$Rt, I32:$Rs)>; 1371 def: Pat<(or (and I32:$Rt, (i32 268431360)), (and I32:$Rs, (i32 65535))), 1372 (A2_combine_hl I32:$Rt, I32:$Rs)>; 1373 def: Pat<(or (and I32:$Rt, (i32 268431360)), (srl I32:$Rs, (i32 16))), 1374 (A2_combine_hh I32:$Rt, I32:$Rs)>; 1375} 1376 1377def SDTHexagonVShift 1378 : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<0>, SDTCisVT<2, i32>]>; 1379 1380def HexagonVASL: SDNode<"HexagonISD::VASL", SDTHexagonVShift>; 1381def HexagonVASR: SDNode<"HexagonISD::VASR", SDTHexagonVShift>; 1382def HexagonVLSR: SDNode<"HexagonISD::VLSR", SDTHexagonVShift>; 1383 1384// Funnel shifts with the shift amount module element bit width. 1385def HexagonMFSHL: SDNode<"HexagonISD::MFSHL", SDTIntShiftDOp>; 1386def HexagonMFSHR: SDNode<"HexagonISD::MFSHR", SDTIntShiftDOp>; 1387 1388def: OpR_RI_pat<S2_asl_i_vw, pf2<HexagonVASL>, v2i32, V2I32, u5_0ImmPred>; 1389def: OpR_RI_pat<S2_asl_i_vh, pf2<HexagonVASL>, v4i16, V4I16, u4_0ImmPred>; 1390def: OpR_RI_pat<S2_asr_i_vw, pf2<HexagonVASR>, v2i32, V2I32, u5_0ImmPred>; 1391def: OpR_RI_pat<S2_asr_i_vh, pf2<HexagonVASR>, v4i16, V4I16, u4_0ImmPred>; 1392def: OpR_RI_pat<S2_lsr_i_vw, pf2<HexagonVLSR>, v2i32, V2I32, u5_0ImmPred>; 1393def: OpR_RI_pat<S2_lsr_i_vh, pf2<HexagonVLSR>, v4i16, V4I16, u4_0ImmPred>; 1394 1395def: OpR_RR_pat<S2_asl_r_vw, pf2<HexagonVASL>, v2i32, V2I32, I32>; 1396def: OpR_RR_pat<S2_asl_r_vh, pf2<HexagonVASL>, v4i16, V4I16, I32>; 1397def: OpR_RR_pat<S2_asr_r_vw, pf2<HexagonVASR>, v2i32, V2I32, I32>; 1398def: OpR_RR_pat<S2_asr_r_vh, pf2<HexagonVASR>, v4i16, V4I16, I32>; 1399def: OpR_RR_pat<S2_lsr_r_vw, pf2<HexagonVLSR>, v2i32, V2I32, I32>; 1400def: OpR_RR_pat<S2_lsr_r_vh, pf2<HexagonVLSR>, v4i16, V4I16, I32>; 1401 1402def: Pat<(sra V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1403 (S2_asr_i_vw V2I32:$b, imm:$c)>; 1404def: Pat<(srl V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1405 (S2_lsr_i_vw V2I32:$b, imm:$c)>; 1406def: Pat<(shl V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))), 1407 (S2_asl_i_vw V2I32:$b, imm:$c)>; 1408def: Pat<(sra V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1409 (S2_asr_i_vh V4I16:$b, imm:$c)>; 1410def: Pat<(srl V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1411 (S2_lsr_i_vh V4I16:$b, imm:$c)>; 1412def: Pat<(shl V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))), 1413 (S2_asl_i_vh V4I16:$b, imm:$c)>; 1414 1415def: Pat<(HexagonVASR V2I16:$Rs, u4_0ImmPred:$S), 1416 (LoReg (S2_asr_i_vh (ToAext64 $Rs), imm:$S))>; 1417def: Pat<(HexagonVASL V2I16:$Rs, u4_0ImmPred:$S), 1418 (LoReg (S2_asl_i_vh (ToAext64 $Rs), imm:$S))>; 1419def: Pat<(HexagonVLSR V2I16:$Rs, u4_0ImmPred:$S), 1420 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), imm:$S))>; 1421def: Pat<(HexagonVASR V2I16:$Rs, I32:$Rt), 1422 (LoReg (S2_asr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1423def: Pat<(HexagonVASL V2I16:$Rs, I32:$Rt), 1424 (LoReg (S2_asl_i_vh (ToAext64 $Rs), I32:$Rt))>; 1425def: Pat<(HexagonVLSR V2I16:$Rs, I32:$Rt), 1426 (LoReg (S2_lsr_i_vh (ToAext64 $Rs), I32:$Rt))>; 1427 1428 1429// --(9) Arithmetic/bitwise ---------------------------------------------- 1430// 1431 1432def: Pat<(abs I32:$Rs), (A2_abs I32:$Rs)>; 1433def: Pat<(abs I64:$Rs), (A2_absp I64:$Rs)>; 1434def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>; 1435def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>; 1436def: Pat<(ineg I64:$Rs), (A2_negp I64:$Rs)>; 1437 1438def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>; 1439def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>; 1440 1441def: Pat<(fabs F64:$Rs), 1442 (Combinew (S2_clrbit_i (HiReg $Rs), 31), 1443 (i32 (LoReg $Rs)))>; 1444def: Pat<(fneg F64:$Rs), 1445 (Combinew (S2_togglebit_i (HiReg $Rs), 31), 1446 (i32 (LoReg $Rs)))>; 1447 1448def: Pat<(add I32:$Rs, anyimm:$s16), (A2_addi I32:$Rs, imm:$s16)>; 1449def: Pat<(or I32:$Rs, anyimm:$s10), (A2_orir I32:$Rs, imm:$s10)>; 1450def: Pat<(and I32:$Rs, anyimm:$s10), (A2_andir I32:$Rs, imm:$s10)>; 1451def: Pat<(sub anyimm:$s10, I32:$Rs), (A2_subri imm:$s10, I32:$Rs)>; 1452 1453def: OpR_RR_pat<A2_add, Add, i32, I32>; 1454def: OpR_RR_pat<A2_sub, Sub, i32, I32>; 1455def: OpR_RR_pat<A2_and, And, i32, I32>; 1456def: OpR_RR_pat<A2_or, Or, i32, I32>; 1457def: OpR_RR_pat<A2_xor, Xor, i32, I32>; 1458def: OpR_RR_pat<A2_addp, Add, i64, I64>; 1459def: OpR_RR_pat<A2_subp, Sub, i64, I64>; 1460def: OpR_RR_pat<A2_andp, And, i64, I64>; 1461def: OpR_RR_pat<A2_orp, Or, i64, I64>; 1462def: OpR_RR_pat<A2_xorp, Xor, i64, I64>; 1463def: OpR_RR_pat<A4_andnp, Not2<And>, i64, I64>; 1464def: OpR_RR_pat<A4_ornp, Not2<Or>, i64, I64>; 1465 1466def: OpR_RR_pat<A2_svaddh, Add, v2i16, V2I16>; 1467def: OpR_RR_pat<A2_svsubh, Sub, v2i16, V2I16>; 1468 1469def: OpR_RR_pat<A2_vaddub, Add, v8i8, V8I8>; 1470def: OpR_RR_pat<A2_vaddh, Add, v4i16, V4I16>; 1471def: OpR_RR_pat<A2_vaddw, Add, v2i32, V2I32>; 1472def: OpR_RR_pat<A2_vsubub, Sub, v8i8, V8I8>; 1473def: OpR_RR_pat<A2_vsubh, Sub, v4i16, V4I16>; 1474def: OpR_RR_pat<A2_vsubw, Sub, v2i32, V2I32>; 1475 1476def: OpR_RR_pat<A2_and, And, v4i8, V4I8>; 1477def: OpR_RR_pat<A2_xor, Xor, v4i8, V4I8>; 1478def: OpR_RR_pat<A2_or, Or, v4i8, V4I8>; 1479def: OpR_RR_pat<A2_and, And, v2i16, V2I16>; 1480def: OpR_RR_pat<A2_xor, Xor, v2i16, V2I16>; 1481def: OpR_RR_pat<A2_or, Or, v2i16, V2I16>; 1482def: OpR_RR_pat<A2_andp, And, v8i8, V8I8>; 1483def: OpR_RR_pat<A2_orp, Or, v8i8, V8I8>; 1484def: OpR_RR_pat<A2_xorp, Xor, v8i8, V8I8>; 1485def: OpR_RR_pat<A2_andp, And, v4i16, V4I16>; 1486def: OpR_RR_pat<A2_orp, Or, v4i16, V4I16>; 1487def: OpR_RR_pat<A2_xorp, Xor, v4i16, V4I16>; 1488def: OpR_RR_pat<A2_andp, And, v2i32, V2I32>; 1489def: OpR_RR_pat<A2_orp, Or, v2i32, V2I32>; 1490def: OpR_RR_pat<A2_xorp, Xor, v2i32, V2I32>; 1491 1492def: OpR_RR_pat<M2_mpyi, Mul, i32, I32>; 1493def: OpR_RR_pat<M2_mpy_up, pf2<mulhs>, i32, I32>; 1494def: OpR_RR_pat<M2_mpyu_up, pf2<mulhu>, i32, I32>; 1495def: OpR_RI_pat<M2_mpysip, Mul, i32, I32, u32_0ImmPred>; 1496def: OpR_RI_pat<M2_mpysmi, Mul, i32, I32, s32_0ImmPred>; 1497 1498// Arithmetic on predicates. 1499def: OpR_RR_pat<C2_xor, Add, i1, I1>; 1500def: OpR_RR_pat<C2_xor, Add, v2i1, V2I1>; 1501def: OpR_RR_pat<C2_xor, Add, v4i1, V4I1>; 1502def: OpR_RR_pat<C2_xor, Add, v8i1, V8I1>; 1503def: OpR_RR_pat<C2_xor, Sub, i1, I1>; 1504def: OpR_RR_pat<C2_xor, Sub, v2i1, V2I1>; 1505def: OpR_RR_pat<C2_xor, Sub, v4i1, V4I1>; 1506def: OpR_RR_pat<C2_xor, Sub, v8i1, V8I1>; 1507def: OpR_RR_pat<C2_and, Mul, i1, I1>; 1508def: OpR_RR_pat<C2_and, Mul, v2i1, V2I1>; 1509def: OpR_RR_pat<C2_and, Mul, v4i1, V4I1>; 1510def: OpR_RR_pat<C2_and, Mul, v8i1, V8I1>; 1511 1512def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>; 1513def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>; 1514def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>; 1515def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>; 1516def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>; 1517 1518let Predicates = [HasV66] in { 1519 def: OpR_RR_pat<F2_dfadd, pf2<fadd>, f64, F64>; 1520 def: OpR_RR_pat<F2_dfsub, pf2<fsub>, f64, F64>; 1521} 1522 1523def DfMpy: OutPatFrag<(ops node:$Rs, node:$Rt), 1524 (F2_dfmpyhh 1525 (F2_dfmpylh 1526 (F2_dfmpylh 1527 (F2_dfmpyll $Rs, $Rt), 1528 $Rs, $Rt), 1529 $Rt, $Rs), 1530 $Rs, $Rt)>; 1531 1532let Predicates = [HasV67,UseUnsafeMath], AddedComplexity = 50 in { 1533 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy $Rs, $Rt)>; 1534} 1535let Predicates = [HasV67] in { 1536 def: OpR_RR_pat<F2_dfmin, pf2<fminnum>, f64, F64>; 1537 def: OpR_RR_pat<F2_dfmax, pf2<fmaxnum>, f64, F64>; 1538 1539 def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy (F2_dfmpyfix $Rs, $Rt), 1540 (F2_dfmpyfix $Rt, $Rs))>; 1541} 1542 1543// In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add, 1544// over add-add with individual multiplies as inputs. 1545let AddedComplexity = 10 in { 1546 def: AccRRI_pat<M2_macsip, Add, Su<Mul>, I32, u32_0ImmPred>; 1547 def: AccRRI_pat<M2_macsin, Sub, Su<Mul>, I32, u32_0ImmPred>; 1548 def: AccRRR_pat<M2_maci, Add, Su<Mul>, I32, I32, I32>; 1549 let Predicates = [HasV66] in 1550 def: AccRRR_pat<M2_mnaci, Sub, Su<Mul>, I32, I32, I32>; 1551} 1552 1553def: AccRRI_pat<M2_naccii, Sub, Su<Add>, I32, s32_0ImmPred>; 1554def: AccRRI_pat<M2_accii, Add, Su<Add>, I32, s32_0ImmPred>; 1555def: AccRRR_pat<M2_acci, Add, Su<Add>, I32, I32, I32>; 1556 1557// Mulh for vectors 1558// 1559def: Pat<(v2i32 (mulhu V2I32:$Rss, V2I32:$Rtt)), 1560 (Combinew (M2_mpyu_up (HiReg $Rss), (HiReg $Rtt)), 1561 (M2_mpyu_up (LoReg $Rss), (LoReg $Rtt)))>; 1562 1563def: Pat<(v2i32 (mulhs V2I32:$Rss, V2I32:$Rtt)), 1564 (Combinew (M2_mpy_up (HiReg $Rss), (HiReg $Rtt)), 1565 (M2_mpy_up (LoReg $Rss), (LoReg $Rtt)))>; 1566 1567def Mulhub4: 1568 OutPatFrag<(ops node:$Rs, node:$Rt), (S2_vtrunohb (M5_vmpybuu $Rs, $Rt))>; 1569def Mulhub8: 1570 OutPatFrag<(ops node:$Rss, node:$Rtt), 1571 (Combinew (Mulhub4 (HiReg $Rss), (HiReg $Rtt)), 1572 (Mulhub4 (LoReg $Rss), (LoReg $Rtt)))>; 1573 1574// (mux (x >= 0), 0, y) 1575def Negbytes8: 1576 OutPatFrag<(ops node:$Rss, node:$Rtt), 1577 (C2_vmux (A4_vcmpbgti $Rss, -1), (A2_tfrpi 0), $Rtt)>; 1578 1579def: Pat<(v4i8 (mulhu V4I8:$Rs, V4I8:$Rt)), (Mulhub4 $Rs, $Rt)>; 1580def: Pat<(v8i8 (mulhu V8I8:$Rss, V8I8:$Rtt)), (Mulhub8 $Rss, $Rtt)>; 1581 1582// (Mulhs x, y) = (Mulhu x, y) - (x < 0 ? y : 0) - (y < 0 ? x : 0) 1583def Mulhsb8: 1584 OutPatFrag<(ops node:$Rss, node:$Rtt), 1585 (A2_vsubub (Mulhub8 $Rss, $Rtt), 1586 (A2_vaddub (Negbytes8 $Rss, $Rtt), 1587 (Negbytes8 $Rtt, $Rss)))>; 1588 1589def: Pat<(v4i8 (mulhs V4I8:$Rs, V4I8:$Rt)), 1590 (LoReg (Mulhsb8 (v8i8 (ToAext64 $Rs)), (v8i8 (ToAext64 $Rt))))>; 1591def: Pat<(v8i8 (mulhs V8I8:$Rss, V8I8:$Rtt)), (Mulhsb8 $Rss, $Rtt)>; 1592 1593// v2i16 *s v2i16 -> v2i32 1594def Muli16: 1595 OutPatFrag<(ops node:$Rs, node:$Rt), (M2_vmpy2s_s0 $Rs, $Rt)>; 1596 1597def Mulhsh2: 1598 OutPatFrag<(ops node:$Rs, node:$Rt), 1599 (A2_combine_hh (HiReg (Muli16 $Rs, $Rt)), 1600 (LoReg (Muli16 $Rs, $Rt)))>; 1601def Mulhsh4: 1602 OutPatFrag<(ops node:$Rss, node:$Rtt), 1603 (Combinew (Mulhsh2 (HiReg $Rss), (HiReg $Rtt)), 1604 (Mulhsh2 (LoReg $Rss), (LoReg $Rtt)))>; 1605 1606def: Pat<(v2i16 (mulhs V2I16:$Rs, V2I16:$Rt)), (Mulhsh2 $Rs, $Rt)>; 1607def: Pat<(v4i16 (mulhs V4I16:$Rss, V4I16:$Rtt)), (Mulhsh4 $Rss, $Rtt)>; 1608 1609def: Pat<(v2i16 (mulhu V2I16:$Rs, V2I16:$Rt)), 1610 (A2_svaddh 1611 (Mulhsh2 $Rs, $Rt), 1612 (A2_svaddh (LoReg (A2_andp (Combinew $Rt, $Rs), 1613 (S2_asr_i_vh (Combinew $Rs, $Rt), 15))), 1614 (HiReg (A2_andp (Combinew $Rt, $Rs), 1615 (S2_asr_i_vh (Combinew $Rs, $Rt), 15)))))>; 1616 1617def: Pat<(v4i16 (mulhu V4I16:$Rss, V4I16:$Rtt)), 1618 (A2_vaddh 1619 (Mulhsh4 $Rss, $Rtt), 1620 (A2_vaddh (A2_andp V4I16:$Rss, (S2_asr_i_vh $Rtt, 15)), 1621 (A2_andp V4I16:$Rtt, (S2_asr_i_vh $Rss, 15))))>; 1622 1623 1624def: Pat<(ineg (mul I32:$Rs, u8_0ImmPred:$u8)), 1625 (M2_mpysin IntRegs:$Rs, imm:$u8)>; 1626 1627def n8_0ImmPred: PatLeaf<(i32 imm), [{ 1628 int64_t V = N->getSExtValue(); 1629 return -255 <= V && V <= 0; 1630}]>; 1631 1632// Change the sign of the immediate for Rd=-mpyi(Rs,#u8) 1633def: Pat<(mul I32:$Rs, n8_0ImmPred:$n8), 1634 (M2_mpysin I32:$Rs, (NegImm8 imm:$n8))>; 1635 1636def: Pat<(add Sext64:$Rs, I64:$Rt), 1637 (A2_addsp (LoReg Sext64:$Rs), I64:$Rt)>; 1638 1639def: AccRRR_pat<M4_and_and, And, Su_ni1<And>, I32, I32, I32>; 1640def: AccRRR_pat<M4_and_or, And, Su_ni1<Or>, I32, I32, I32>; 1641def: AccRRR_pat<M4_and_xor, And, Su<Xor>, I32, I32, I32>; 1642def: AccRRR_pat<M4_or_and, Or, Su_ni1<And>, I32, I32, I32>; 1643def: AccRRR_pat<M4_or_or, Or, Su_ni1<Or>, I32, I32, I32>; 1644def: AccRRR_pat<M4_or_xor, Or, Su<Xor>, I32, I32, I32>; 1645def: AccRRR_pat<M4_xor_and, Xor, Su_ni1<And>, I32, I32, I32>; 1646def: AccRRR_pat<M4_xor_or, Xor, Su_ni1<Or>, I32, I32, I32>; 1647def: AccRRR_pat<M2_xor_xacc, Xor, Su<Xor>, I32, I32, I32>; 1648def: AccRRR_pat<M4_xor_xacc, Xor, Su<Xor>, I64, I64, I64>; 1649 1650// For dags like (or (and (not _), _), (shl _, _)) where the "or" with 1651// one argument matches the patterns below, and with the other argument 1652// matches S2_asl_r_r_or, etc, prefer the patterns below. 1653let AddedComplexity = 110 in { // greater than S2_asl_r_r_and/or/xor. 1654 def: AccRRR_pat<M4_and_andn, And, Su<Not2<And>>, I32, I32, I32>; 1655 def: AccRRR_pat<M4_or_andn, Or, Su<Not2<And>>, I32, I32, I32>; 1656 def: AccRRR_pat<M4_xor_andn, Xor, Su<Not2<And>>, I32, I32, I32>; 1657} 1658 1659// S4_addaddi and S4_subaddi don't have tied operands, so give them 1660// a bit of preference. 1661let AddedComplexity = 30, Predicates = [UseCompound] in { 1662 def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)), 1663 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1664 def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)), 1665 (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>; 1666 def: Pat<(add I32:$Rs, (Su<Sub> anyimm:$s6, I32:$Ru)), 1667 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1668 def: Pat<(sub (Su<Add> I32:$Rs, anyimm:$s6), I32:$Ru), 1669 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1670 def: Pat<(add (Su<Sub> I32:$Rs, I32:$Ru), anyimm:$s6), 1671 (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>; 1672} 1673 1674let Predicates = [UseCompound] in 1675def: Pat<(or I32:$Ru, (Su<And> I32:$Rx, anyimm:$s10)), 1676 (S4_or_andix IntRegs:$Ru, IntRegs:$Rx, imm:$s10)>; 1677 1678def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)), 1679 (S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1680def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)), 1681 (S4_or_ori IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>; 1682 1683 1684def: Pat<(i32 (trunc (sra (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1685 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1686def: Pat<(i32 (trunc (srl (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))), 1687 (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1688 1689def: Pat<(mul (Zext64 I32:$Rs), (Zext64 I32:$Rt)), 1690 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1691def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)), 1692 (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>; 1693def: Pat<(mul Sext64:$Rs, Sext64:$Rt), 1694 (M2_dpmpyss_s0 (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1695 1696def: Pat<(add I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1697 (M2_dpmpyss_acc_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1698def: Pat<(sub I64:$Rx, (Su<Mul> Sext64:$Rs, Sext64:$Rt)), 1699 (M2_dpmpyss_nac_s0 I64:$Rx, (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>; 1700def: Pat<(add I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1701 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1702def: Pat<(add I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1703 (M2_dpmpyuu_acc_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1704def: Pat<(sub I64:$Rx, (Su<Mul> (Aext64 I32:$Rs), (Aext64 I32:$Rt))), 1705 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1706def: Pat<(sub I64:$Rx, (Su<Mul> (Zext64 I32:$Rs), (Zext64 I32:$Rt))), 1707 (M2_dpmpyuu_nac_s0 I64:$Rx, I32:$Rs, I32:$Rt)>; 1708 1709// Add halfword. 1710def: Pat<(sext_inreg (add I32:$Rt, I32:$Rs), i16), 1711 (A2_addh_l16_ll I32:$Rt, I32:$Rs)>; 1712def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1713 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1714def: Pat<(shl (add I32:$Rt, I32:$Rs), (i32 16)), 1715 (A2_addh_h16_ll I32:$Rt, I32:$Rs)>; 1716 1717// Subtract halfword. 1718def: Pat<(sext_inreg (sub I32:$Rt, I32:$Rs), i16), 1719 (A2_subh_l16_ll I32:$Rt, I32:$Rs)>; 1720def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)), 1721 (A2_addh_l16_hl I32:$Rt, I32:$Rs)>; 1722def: Pat<(shl (sub I32:$Rt, I32:$Rs), (i32 16)), 1723 (A2_subh_h16_ll I32:$Rt, I32:$Rs)>; 1724 1725def: Pat<(mul I64:$Rss, I64:$Rtt), 1726 (Combinew 1727 (M2_maci (M2_maci (HiReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt))), 1728 (LoReg $Rss), 1729 (HiReg $Rtt)), 1730 (LoReg $Rtt), 1731 (HiReg $Rss)), 1732 (i32 (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)))))>; 1733 1734def MulHU : OutPatFrag<(ops node:$Rss, node:$Rtt), 1735 (A2_addp 1736 (M2_dpmpyuu_acc_s0 1737 (S2_lsr_i_p 1738 (A2_addp 1739 (M2_dpmpyuu_acc_s0 1740 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (LoReg $Rtt)), 32), 1741 (HiReg $Rss), 1742 (LoReg $Rtt)), 1743 (A4_combineir 0, (LoReg (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt))))), 1744 32), 1745 (HiReg $Rss), 1746 (HiReg $Rtt)), 1747 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $Rss), (HiReg $Rtt)), 32))>; 1748 1749// Multiply 64-bit unsigned and use upper result. 1750def : Pat <(mulhu I64:$Rss, I64:$Rtt), (MulHU $Rss, $Rtt)>; 1751 1752// Multiply 64-bit signed and use upper result. 1753// 1754// For two signed 64-bit integers A and B, let A' and B' denote A and B 1755// with the sign bit cleared. Then A = -2^63*s(A) + A', where s(A) is the 1756// sign bit of A (and identically for B). With this notation, the signed 1757// product A*B can be written as: 1758// AB = (-2^63 s(A) + A') * (-2^63 s(B) + B') 1759// = 2^126 s(A)s(B) - 2^63 [s(A)B'+s(B)A'] + A'B' 1760// = 2^126 s(A)s(B) + 2^63 [s(A)B'+s(B)A'] + A'B' - 2*2^63 [s(A)B'+s(B)A'] 1761// = (unsigned product AB) - 2^64 [s(A)B'+s(B)A'] 1762 1763// Clear the sign bit in a 64-bit register. 1764def ClearSign : OutPatFrag<(ops node:$Rss), 1765 (Combinew (S2_clrbit_i (HiReg $Rss), 31), (i32 (LoReg $Rss)))>; 1766 1767def : Pat <(mulhs I64:$Rss, I64:$Rtt), 1768 (A2_subp 1769 (MulHU $Rss, $Rtt), 1770 (A2_addp 1771 (A2_andp (S2_asr_i_p $Rss, 63), (ClearSign $Rtt)), 1772 (A2_andp (S2_asr_i_p $Rtt, 63), (ClearSign $Rss))))>; 1773 1774// Prefer these instructions over M2_macsip/M2_macsin: the macsi* instructions 1775// will put the immediate addend into a register, while these instructions will 1776// use it directly. Such a construct does not appear in the middle of a gep, 1777// where M2_macsip would be preferable. 1778let AddedComplexity = 20, Predicates = [UseCompound] in { 1779 def: Pat<(add (Su<Mul> I32:$Rs, u6_0ImmPred:$U6), anyimm:$u6), 1780 (M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>; 1781 def: Pat<(add (Su<Mul> I32:$Rs, I32:$Rt), anyimm:$u6), 1782 (M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>; 1783} 1784 1785// Keep these instructions less preferable to M2_macsip/M2_macsin. 1786let Predicates = [UseCompound] in { 1787 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)), 1788 (M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>; 1789 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)), 1790 (M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>; 1791 def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)), 1792 (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>; 1793} 1794 1795def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), 1796 (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; 1797def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), 1798 (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; 1799 1800def: Pat<(mul V2I32:$Rs, V2I32:$Rt), 1801 (PS_vmulw V2I32:$Rs, V2I32:$Rt)>; 1802def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)), 1803 (PS_vmulw_acc V2I32:$Rx, V2I32:$Rs, V2I32:$Rt)>; 1804 1805// Add/subtract two v4i8: Hexagon does not have an insn for this one, so 1806// we use the double add v8i8, and use only the low part of the result. 1807def: Pat<(add V4I8:$Rs, V4I8:$Rt), 1808 (LoReg (A2_vaddub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1809def: Pat<(sub V4I8:$Rs, V4I8:$Rt), 1810 (LoReg (A2_vsubub (ToAext64 $Rs), (ToAext64 $Rt)))>; 1811 1812// Use M2_vmpy2s_s0 for half-word vector multiply. It multiplies two 1813// half-words, and saturates the result to a 32-bit value, except the 1814// saturation never happens (it can only occur with scaling). 1815def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)), 1816 (LoReg (S2_vtrunewh (IMPLICIT_DEF), 1817 (M2_vmpy2s_s0 V2I16:$Rs, V2I16:$Rt)))>; 1818def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)), 1819 (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)), 1820 (M2_vmpy2s_s0 (LoReg $Rs), (LoReg $Rt)))>; 1821 1822// Multiplies two v4i8 vectors. 1823def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)), 1824 (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>; 1825 1826// Multiplies two v8i8 vectors. 1827def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)), 1828 (Combinew (S2_vtrunehb (M5_vmpybuu (HiReg $Rs), (HiReg $Rt))), 1829 (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>; 1830 1831 1832// --(10) Bit ------------------------------------------------------------ 1833// 1834 1835// Count leading zeros. 1836def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>; 1837def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>; 1838 1839// Count trailing zeros. 1840def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>; 1841def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>; 1842 1843// Count leading ones. 1844def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>; 1845def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>; 1846 1847// Count trailing ones. 1848def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>; 1849def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>; 1850 1851// Define leading/trailing patterns that require zero-extensions to 64 bits. 1852def: Pat<(i64 (ctlz I64:$Rss)), (ToZext64 (S2_cl0p I64:$Rss))>; 1853def: Pat<(i64 (cttz I64:$Rss)), (ToZext64 (S2_ct0p I64:$Rss))>; 1854def: Pat<(i64 (ctlz (not I64:$Rss))), (ToZext64 (S2_cl1p I64:$Rss))>; 1855def: Pat<(i64 (cttz (not I64:$Rss))), (ToZext64 (S2_ct1p I64:$Rss))>; 1856 1857def: Pat<(i64 (ctpop I64:$Rss)), (ToZext64 (S5_popcountp I64:$Rss))>; 1858def: Pat<(i32 (ctpop I32:$Rs)), (S5_popcountp (A4_combineir 0, I32:$Rs))>; 1859 1860def: Pat<(bitreverse I32:$Rs), (S2_brev I32:$Rs)>; 1861def: Pat<(bitreverse I64:$Rss), (S2_brevp I64:$Rss)>; 1862 1863def: Pat<(bitreverse V4I8:$Rs), (A2_swiz (S2_brev $Rs))>; 1864def: Pat<(bitreverse V8I8:$Rs), (Combinew (A2_swiz (LoReg (S2_brevp $Rs))), 1865 (A2_swiz (HiReg (S2_brevp $Rs))))>; 1866def: Pat<(bitreverse V2I16:$Rs), (A2_combine_lh (S2_brev $Rs), 1867 (S2_brev $Rs))>; 1868def: Pat<(bitreverse V4I16:$Rs), 1869 (Combinew (A2_combine_lh (LoReg (S2_brevp $Rs)), 1870 (LoReg (S2_brevp $Rs))), 1871 (A2_combine_lh (HiReg (S2_brevp $Rs)), 1872 (HiReg (S2_brevp $Rs))))>; 1873def: Pat<(bitreverse V2I32:$Rs), 1874 (Combinew (i32 (LoReg (S2_brevp $Rs))), 1875 (i32 (HiReg (S2_brevp $Rs))))>; 1876 1877let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1878 def: Pat<(and I32:$Rs, IsNPow2_32:$V), 1879 (S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>; 1880 def: Pat<(or I32:$Rs, IsPow2_32:$V), 1881 (S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>; 1882 def: Pat<(xor I32:$Rs, IsPow2_32:$V), 1883 (S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>; 1884 1885 def: Pat<(and I32:$Rs, (not (shl 1, I32:$Rt))), 1886 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1887 def: Pat<(or I32:$Rs, (shl 1, I32:$Rt)), 1888 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1889 def: Pat<(xor I32:$Rs, (shl 1, I32:$Rt)), 1890 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>; 1891} 1892 1893// Clr/set/toggle bit for 64-bit values with immediate bit index. 1894let AddedComplexity = 20 in { // Complexity greater than and/or/xor 1895 def: Pat<(and I64:$Rss, IsNPow2_64L:$V), 1896 (Combinew (i32 (HiReg $Rss)), 1897 (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)))>; 1898 def: Pat<(and I64:$Rss, IsNPow2_64H:$V), 1899 (Combinew (S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))), 1900 (i32 (LoReg $Rss)))>; 1901 1902 def: Pat<(or I64:$Rss, IsPow2_64L:$V), 1903 (Combinew (i32 (HiReg $Rss)), 1904 (S2_setbit_i (LoReg $Rss), (Log2_64 $V)))>; 1905 def: Pat<(or I64:$Rss, IsPow2_64H:$V), 1906 (Combinew (S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1907 (i32 (LoReg $Rss)))>; 1908 1909 def: Pat<(xor I64:$Rss, IsPow2_64L:$V), 1910 (Combinew (i32 (HiReg $Rss)), 1911 (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)))>; 1912 def: Pat<(xor I64:$Rss, IsPow2_64H:$V), 1913 (Combinew (S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))), 1914 (i32 (LoReg $Rss)))>; 1915} 1916 1917 1918let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1919 def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)), 1920 (S2_tstbit_i IntRegs:$Rs, imm:$u5)>; 1921 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1922 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>; 1923 def: Pat<(i1 (trunc I32:$Rs)), 1924 (S2_tstbit_i IntRegs:$Rs, 0)>; 1925 def: Pat<(i1 (trunc I64:$Rs)), 1926 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>; 1927} 1928 1929def: Pat<(and (srl I32:$Rs, u5_0ImmPred:$u5), 1), 1930 (I1toI32 (S2_tstbit_i I32:$Rs, imm:$u5))>; 1931def: Pat<(and (srl I64:$Rss, IsULE<32,31>:$u6), 1), 1932 (ToZext64 (I1toI32 (S2_tstbit_i (LoReg $Rss), imm:$u6)))>; 1933def: Pat<(and (srl I64:$Rss, IsUGT<32,31>:$u6), 1), 1934 (ToZext64 (I1toI32 (S2_tstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1935 1936def: Pat<(and (not (srl I32:$Rs, u5_0ImmPred:$u5)), 1), 1937 (I1toI32 (S4_ntstbit_i I32:$Rs, imm:$u5))>; 1938def: Pat<(and (not (srl I64:$Rss, IsULE<32,31>:$u6)), 1), 1939 (ToZext64 (I1toI32 (S4_ntstbit_i (LoReg $Rss), imm:$u6)))>; 1940def: Pat<(and (not (srl I64:$Rss, IsUGT<32,31>:$u6)), 1), 1941 (ToZext64 (I1toI32 (S4_ntstbit_i (HiReg $Rss), (UDEC32 $u6))))>; 1942 1943let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1944 def: Pat<(i1 (seteq (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1945 (C2_bitsclri IntRegs:$Rs, imm:$u6)>; 1946 def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), 0)), 1947 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>; 1948} 1949 1950let AddedComplexity = 10 in // Complexity greater than compare reg-reg. 1951def: Pat<(i1 (seteq (and I32:$Rs, I32:$Rt), IntRegs:$Rt)), 1952 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>; 1953 1954def SDTTestBit: 1955 SDTypeProfile<1, 2, [SDTCisVT<0, i1>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 1956def HexagonTSTBIT: SDNode<"HexagonISD::TSTBIT", SDTTestBit>; 1957 1958def: Pat<(HexagonTSTBIT I32:$Rs, u5_0ImmPred:$u5), 1959 (S2_tstbit_i I32:$Rs, imm:$u5)>; 1960def: Pat<(HexagonTSTBIT I32:$Rs, I32:$Rt), 1961 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 1962 1963// Add extra complexity to prefer these instructions over bitsset/bitsclr. 1964// The reason is that tstbit/ntstbit can be folded into a compound instruction: 1965// if ([!]tstbit(...)) jump ... 1966let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1967 def: Pat<(i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)), 1968 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 1969 def: Pat<(i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)), 1970 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5))>; 1971 def: Pat<(i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1972 (S4_ntstbit_r I32:$Rs, I32:$Rt)>; 1973 def: Pat<(i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)), 1974 (S2_tstbit_r I32:$Rs, I32:$Rt)>; 1975} 1976 1977def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64L:$u6), 0)), 1978 (S4_ntstbit_i (LoReg $Rs), (Log2_64 $u6))>; 1979def: Pat<(i1 (seteq (and I64:$Rs, IsPow2_64H:$u6), 0)), 1980 (S4_ntstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 $u6))))>; 1981def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64L:$u6), 0)), 1982 (S2_tstbit_i (LoReg $Rs), (Log2_64 imm:$u6))>; 1983def: Pat<(i1 (setne (and I64:$Rs, IsPow2_64H:$u6), 0)), 1984 (S2_tstbit_i (HiReg $Rs), (UDEC32 (i32 (Log2_64 imm:$u6))))>; 1985 1986// Do not increase complexity of these patterns. In the DAG, "cmp i8" may be 1987// represented as a compare against "value & 0xFF", which is an exact match 1988// for cmpb (same for cmph). The patterns below do not contain any additional 1989// complexity that would make them preferable, and if they were actually used 1990// instead of cmpb/cmph, they would result in a compare against register that 1991// is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF). 1992def: Pat<(i1 (setne (and I32:$Rs, u6_0ImmPred:$u6), 0)), 1993 (C4_nbitsclri I32:$Rs, imm:$u6)>; 1994def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)), 1995 (C4_nbitsclr I32:$Rs, I32:$Rt)>; 1996def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)), 1997 (C4_nbitsset I32:$Rs, I32:$Rt)>; 1998 1999// Special patterns to address certain cases where the "top-down" matching 2000// algorithm would cause suboptimal selection. 2001 2002let AddedComplexity = 100 in { 2003 // Avoid A4_rcmp[n]eqi in these cases: 2004 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 2005 (I1toI32 (S4_ntstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 2006 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 2007 (I1toI32 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt))>; 2008 def: Pat<(i32 (zext (i1 (seteq (and I32:$Rs, IsPow2_32:$u5), 0)))), 2009 (I1toI32 (S4_ntstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 2010 def: Pat<(i32 (zext (i1 (setne (and I32:$Rs, IsPow2_32:$u5), 0)))), 2011 (I1toI32 (S2_tstbit_i I32:$Rs, (Log2_32 imm:$u5)))>; 2012 def: Pat<(i32 (zext (i1 (seteq (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 2013 (I1toI32 (S4_ntstbit_r I32:$Rs, I32:$Rt))>; 2014 def: Pat<(i32 (zext (i1 (setne (and (shl 1, I32:$Rt), I32:$Rs), 0)))), 2015 (I1toI32 (S2_tstbit_r I32:$Rs, I32:$Rt))>; 2016} 2017 2018// --(11) PIC ------------------------------------------------------------ 2019// 2020 2021def SDT_HexagonAtGot 2022 : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; 2023def SDT_HexagonAtPcrel 2024 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 2025 2026// AT_GOT address-of-GOT, address-of-global, offset-in-global 2027def HexagonAtGot : SDNode<"HexagonISD::AT_GOT", SDT_HexagonAtGot>; 2028// AT_PCREL address-of-global 2029def HexagonAtPcrel : SDNode<"HexagonISD::AT_PCREL", SDT_HexagonAtPcrel>; 2030 2031def: Pat<(HexagonAtGot I32:$got, I32:$addr, (i32 0)), 2032 (L2_loadri_io I32:$got, imm:$addr)>; 2033def: Pat<(HexagonAtGot I32:$got, I32:$addr, s30_2ImmPred:$off), 2034 (A2_addi (L2_loadri_io I32:$got, imm:$addr), imm:$off)>; 2035def: Pat<(HexagonAtPcrel I32:$addr), 2036 (C4_addipc imm:$addr)>; 2037 2038// The HVX load patterns also match AT_PCREL directly. Make sure that 2039// if the selection of this opcode changes, it's updated in all places. 2040 2041 2042// --(12) Load ----------------------------------------------------------- 2043// 2044 2045def L1toI32: OutPatFrag<(ops node:$Rs), (A2_subri 0, (i32 $Rs))>; 2046def L1toI64: OutPatFrag<(ops node:$Rs), (ToSext64 (L1toI32 $Rs))>; 2047 2048def extloadv2i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 2049 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 2050}]>; 2051def extloadv4i8: PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 2052 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 2053}]>; 2054 2055def zextloadv2i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 2056 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 2057}]>; 2058def zextloadv4i8: PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 2059 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 2060}]>; 2061 2062def sextloadv2i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 2063 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8; 2064}]>; 2065def sextloadv4i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 2066 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8; 2067}]>; 2068 2069// Patterns to select load-indexed: Rs + Off. 2070// - frameindex [+ imm], 2071multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 2072 InstHexagon MI> { 2073 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 2074 (VT (MI AddrFI:$fi, imm:$Off))>; 2075 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 2076 (VT (MI AddrFI:$fi, imm:$Off))>; 2077 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>; 2078} 2079 2080// Patterns to select load-indexed: Rs + Off. 2081// - base reg [+ imm] 2082multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 2083 InstHexagon MI> { 2084 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 2085 (VT (MI IntRegs:$Rs, imm:$Off))>; 2086 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 2087 (VT (MI IntRegs:$Rs, imm:$Off))>; 2088 def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>; 2089} 2090 2091// Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi. 2092multiclass Loadxi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 2093 InstHexagon MI> { 2094 defm: Loadxfi_pat<Load, VT, ImmPred, MI>; 2095 defm: Loadxgi_pat<Load, VT, ImmPred, MI>; 2096} 2097 2098// Patterns to select load reg indexed: Rs + Off with a value modifier. 2099// - frameindex [+ imm] 2100multiclass Loadxfim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2101 PatLeaf ImmPred, InstHexagon MI> { 2102 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 2103 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 2104 def: Pat<(VT (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))), 2105 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>; 2106 def: Pat<(VT (Load AddrFI:$fi)), (VT (ValueMod (MI AddrFI:$fi, 0)))>; 2107} 2108 2109// Patterns to select load reg indexed: Rs + Off with a value modifier. 2110// - base reg [+ imm] 2111multiclass Loadxgim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2112 PatLeaf ImmPred, InstHexagon MI> { 2113 def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))), 2114 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 2115 def: Pat<(VT (Load (IsOrAdd I32:$Rs, ImmPred:$Off))), 2116 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; 2117 def: Pat<(VT (Load I32:$Rs)), (VT (ValueMod (MI IntRegs:$Rs, 0)))>; 2118} 2119 2120// Patterns to select load reg indexed: Rs + Off with a value modifier. 2121// Combines Loadxfim + Loadxgim. 2122multiclass Loadxim_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2123 PatLeaf ImmPred, InstHexagon MI> { 2124 defm: Loadxfim_pat<Load, VT, ValueMod, ImmPred, MI>; 2125 defm: Loadxgim_pat<Load, VT, ValueMod, ImmPred, MI>; 2126} 2127 2128// Pattern to select load reg reg-indexed: Rs + Rt<<u2. 2129class Loadxr_shl_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2130 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2131 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>; 2132 2133// Pattern to select load reg reg-indexed: Rs + Rt<<0. 2134class Loadxr_add_pat<PatFrag Load, ValueType VT, InstHexagon MI> 2135 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2136 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>; 2137 2138// Pattern to select load reg reg-indexed: Rs + Rt<<u2 with value modifier. 2139class Loadxrm_shl_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2140 InstHexagon MI> 2141 : Pat<(VT (Load (add I32:$Rs, (i32 (shl I32:$Rt, u2_0ImmPred:$u2))))), 2142 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2)))>; 2143 2144// Pattern to select load reg reg-indexed: Rs + Rt<<0 with value modifier. 2145class Loadxrm_add_pat<PatFrag Load, ValueType VT, PatFrag ValueMod, 2146 InstHexagon MI> 2147 : Pat<(VT (Load (add I32:$Rs, I32:$Rt))), 2148 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, 0)))>; 2149 2150// Pattern to select load long-offset reg-indexed: Addr + Rt<<u2. 2151// Don't match for u2==0, instead use reg+imm for those cases. 2152class Loadxu_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, InstHexagon MI> 2153 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2154 (VT (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr))>; 2155 2156class Loadxum_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, PatFrag ValueMod, 2157 InstHexagon MI> 2158 : Pat<(VT (Load (add (shl IntRegs:$Rt, u2_0ImmPred:$u2), ImmPred:$Addr))), 2159 (VT (ValueMod (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr)))>; 2160 2161// Pattern to select load absolute. 2162class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI> 2163 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>; 2164 2165// Pattern to select load absolute with value modifier. 2166class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod, 2167 InstHexagon MI> 2168 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>; 2169 2170 2171let AddedComplexity = 20 in { 2172 defm: Loadxi_pat<extloadi1, i32, anyimm0, L2_loadrub_io>; 2173 defm: Loadxi_pat<extloadi8, i32, anyimm0, L2_loadrub_io>; 2174 defm: Loadxi_pat<extloadi16, i32, anyimm1, L2_loadruh_io>; 2175 defm: Loadxi_pat<extloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2176 defm: Loadxi_pat<extloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2177 defm: Loadxi_pat<sextloadi8, i32, anyimm0, L2_loadrb_io>; 2178 defm: Loadxi_pat<sextloadi16, i32, anyimm1, L2_loadrh_io>; 2179 defm: Loadxi_pat<sextloadv2i8, v2i16, anyimm1, L2_loadbsw2_io>; 2180 defm: Loadxi_pat<sextloadv4i8, v4i16, anyimm2, L2_loadbsw4_io>; 2181 defm: Loadxi_pat<zextloadi1, i32, anyimm0, L2_loadrub_io>; 2182 defm: Loadxi_pat<zextloadi8, i32, anyimm0, L2_loadrub_io>; 2183 defm: Loadxi_pat<zextloadi16, i32, anyimm1, L2_loadruh_io>; 2184 defm: Loadxi_pat<zextloadv2i8, v2i16, anyimm1, L2_loadbzw2_io>; 2185 defm: Loadxi_pat<zextloadv4i8, v4i16, anyimm2, L2_loadbzw4_io>; 2186 defm: Loadxi_pat<load, i32, anyimm2, L2_loadri_io>; 2187 defm: Loadxi_pat<load, v2i16, anyimm2, L2_loadri_io>; 2188 defm: Loadxi_pat<load, v4i8, anyimm2, L2_loadri_io>; 2189 defm: Loadxi_pat<load, i64, anyimm3, L2_loadrd_io>; 2190 defm: Loadxi_pat<load, v2i32, anyimm3, L2_loadrd_io>; 2191 defm: Loadxi_pat<load, v4i16, anyimm3, L2_loadrd_io>; 2192 defm: Loadxi_pat<load, v8i8, anyimm3, L2_loadrd_io>; 2193 defm: Loadxi_pat<load, f32, anyimm2, L2_loadri_io>; 2194 defm: Loadxi_pat<load, f64, anyimm3, L2_loadrd_io>; 2195 // No sextloadi1. 2196 2197 defm: Loadxi_pat<atomic_load_8 , i32, anyimm0, L2_loadrub_io>; 2198 defm: Loadxi_pat<atomic_load_16, i32, anyimm1, L2_loadruh_io>; 2199 defm: Loadxi_pat<atomic_load_32, i32, anyimm2, L2_loadri_io>; 2200 defm: Loadxi_pat<atomic_load_64, i64, anyimm3, L2_loadrd_io>; 2201} 2202 2203let AddedComplexity = 30 in { 2204 // Loads of i1 are loading a byte, and the byte should be either 0 or 1. 2205 // It doesn't matter if it's sign- or zero-extended, so use zero-extension 2206 // everywhere. 2207 defm: Loadxim_pat<sextloadi1, i32, L1toI32, anyimm0, L2_loadrub_io>; 2208 defm: Loadxim_pat<extloadi1, i64, ToAext64, anyimm0, L2_loadrub_io>; 2209 defm: Loadxim_pat<sextloadi1, i64, L1toI64, anyimm0, L2_loadrub_io>; 2210 defm: Loadxim_pat<zextloadi1, i64, ToZext64, anyimm0, L2_loadrub_io>; 2211 2212 defm: Loadxim_pat<extloadi8, i64, ToAext64, anyimm0, L2_loadrub_io>; 2213 defm: Loadxim_pat<extloadi16, i64, ToAext64, anyimm1, L2_loadruh_io>; 2214 defm: Loadxim_pat<extloadi32, i64, ToAext64, anyimm2, L2_loadri_io>; 2215 defm: Loadxim_pat<zextloadi8, i64, ToZext64, anyimm0, L2_loadrub_io>; 2216 defm: Loadxim_pat<zextloadi16, i64, ToZext64, anyimm1, L2_loadruh_io>; 2217 defm: Loadxim_pat<zextloadi32, i64, ToZext64, anyimm2, L2_loadri_io>; 2218 defm: Loadxim_pat<sextloadi8, i64, ToSext64, anyimm0, L2_loadrb_io>; 2219 defm: Loadxim_pat<sextloadi16, i64, ToSext64, anyimm1, L2_loadrh_io>; 2220 defm: Loadxim_pat<sextloadi32, i64, ToSext64, anyimm2, L2_loadri_io>; 2221} 2222 2223let AddedComplexity = 60 in { 2224 def: Loadxu_pat<extloadi1, i32, anyimm0, L4_loadrub_ur>; 2225 def: Loadxu_pat<extloadi8, i32, anyimm0, L4_loadrub_ur>; 2226 def: Loadxu_pat<extloadi16, i32, anyimm1, L4_loadruh_ur>; 2227 def: Loadxu_pat<extloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2228 def: Loadxu_pat<extloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2229 def: Loadxu_pat<sextloadi8, i32, anyimm0, L4_loadrb_ur>; 2230 def: Loadxu_pat<sextloadi16, i32, anyimm1, L4_loadrh_ur>; 2231 def: Loadxu_pat<sextloadv2i8, v2i16, anyimm1, L4_loadbsw2_ur>; 2232 def: Loadxu_pat<sextloadv4i8, v4i16, anyimm2, L4_loadbsw4_ur>; 2233 def: Loadxu_pat<zextloadi1, i32, anyimm0, L4_loadrub_ur>; 2234 def: Loadxu_pat<zextloadi8, i32, anyimm0, L4_loadrub_ur>; 2235 def: Loadxu_pat<zextloadi16, i32, anyimm1, L4_loadruh_ur>; 2236 def: Loadxu_pat<zextloadv2i8, v2i16, anyimm1, L4_loadbzw2_ur>; 2237 def: Loadxu_pat<zextloadv4i8, v4i16, anyimm2, L4_loadbzw4_ur>; 2238 def: Loadxu_pat<load, i32, anyimm2, L4_loadri_ur>; 2239 def: Loadxu_pat<load, v2i16, anyimm2, L4_loadri_ur>; 2240 def: Loadxu_pat<load, v4i8, anyimm2, L4_loadri_ur>; 2241 def: Loadxu_pat<load, i64, anyimm3, L4_loadrd_ur>; 2242 def: Loadxu_pat<load, v2i32, anyimm3, L4_loadrd_ur>; 2243 def: Loadxu_pat<load, v4i16, anyimm3, L4_loadrd_ur>; 2244 def: Loadxu_pat<load, v8i8, anyimm3, L4_loadrd_ur>; 2245 def: Loadxu_pat<load, f32, anyimm2, L4_loadri_ur>; 2246 def: Loadxu_pat<load, f64, anyimm3, L4_loadrd_ur>; 2247 2248 def: Loadxum_pat<sextloadi1, i32, anyimm0, L1toI32, L4_loadrub_ur>; 2249 def: Loadxum_pat<extloadi1, i64, anyimm0, ToAext64, L4_loadrub_ur>; 2250 def: Loadxum_pat<sextloadi1, i64, anyimm0, L1toI64, L4_loadrub_ur>; 2251 def: Loadxum_pat<zextloadi1, i64, anyimm0, ToZext64, L4_loadrub_ur>; 2252 2253 def: Loadxum_pat<sextloadi8, i64, anyimm0, ToSext64, L4_loadrb_ur>; 2254 def: Loadxum_pat<zextloadi8, i64, anyimm0, ToZext64, L4_loadrub_ur>; 2255 def: Loadxum_pat<extloadi8, i64, anyimm0, ToAext64, L4_loadrub_ur>; 2256 def: Loadxum_pat<sextloadi16, i64, anyimm1, ToSext64, L4_loadrh_ur>; 2257 def: Loadxum_pat<zextloadi16, i64, anyimm1, ToZext64, L4_loadruh_ur>; 2258 def: Loadxum_pat<extloadi16, i64, anyimm1, ToAext64, L4_loadruh_ur>; 2259 def: Loadxum_pat<sextloadi32, i64, anyimm2, ToSext64, L4_loadri_ur>; 2260 def: Loadxum_pat<zextloadi32, i64, anyimm2, ToZext64, L4_loadri_ur>; 2261 def: Loadxum_pat<extloadi32, i64, anyimm2, ToAext64, L4_loadri_ur>; 2262} 2263 2264let AddedComplexity = 40 in { 2265 def: Loadxr_shl_pat<extloadi1, i32, L4_loadrub_rr>; 2266 def: Loadxr_shl_pat<extloadi8, i32, L4_loadrub_rr>; 2267 def: Loadxr_shl_pat<zextloadi1, i32, L4_loadrub_rr>; 2268 def: Loadxr_shl_pat<zextloadi8, i32, L4_loadrub_rr>; 2269 def: Loadxr_shl_pat<sextloadi8, i32, L4_loadrb_rr>; 2270 def: Loadxr_shl_pat<extloadi16, i32, L4_loadruh_rr>; 2271 def: Loadxr_shl_pat<zextloadi16, i32, L4_loadruh_rr>; 2272 def: Loadxr_shl_pat<sextloadi16, i32, L4_loadrh_rr>; 2273 def: Loadxr_shl_pat<load, i32, L4_loadri_rr>; 2274 def: Loadxr_shl_pat<load, v2i16, L4_loadri_rr>; 2275 def: Loadxr_shl_pat<load, v4i8, L4_loadri_rr>; 2276 def: Loadxr_shl_pat<load, i64, L4_loadrd_rr>; 2277 def: Loadxr_shl_pat<load, v2i32, L4_loadrd_rr>; 2278 def: Loadxr_shl_pat<load, v4i16, L4_loadrd_rr>; 2279 def: Loadxr_shl_pat<load, v8i8, L4_loadrd_rr>; 2280 def: Loadxr_shl_pat<load, f32, L4_loadri_rr>; 2281 def: Loadxr_shl_pat<load, f64, L4_loadrd_rr>; 2282} 2283 2284let AddedComplexity = 20 in { 2285 def: Loadxr_add_pat<extloadi1, i32, L4_loadrub_rr>; 2286 def: Loadxr_add_pat<extloadi8, i32, L4_loadrub_rr>; 2287 def: Loadxr_add_pat<zextloadi8, i32, L4_loadrub_rr>; 2288 def: Loadxr_add_pat<zextloadi1, i32, L4_loadrub_rr>; 2289 def: Loadxr_add_pat<sextloadi8, i32, L4_loadrb_rr>; 2290 def: Loadxr_add_pat<extloadi16, i32, L4_loadruh_rr>; 2291 def: Loadxr_add_pat<zextloadi16, i32, L4_loadruh_rr>; 2292 def: Loadxr_add_pat<sextloadi16, i32, L4_loadrh_rr>; 2293 def: Loadxr_add_pat<load, i32, L4_loadri_rr>; 2294 def: Loadxr_add_pat<load, v2i16, L4_loadri_rr>; 2295 def: Loadxr_add_pat<load, v4i8, L4_loadri_rr>; 2296 def: Loadxr_add_pat<load, i64, L4_loadrd_rr>; 2297 def: Loadxr_add_pat<load, v2i32, L4_loadrd_rr>; 2298 def: Loadxr_add_pat<load, v4i16, L4_loadrd_rr>; 2299 def: Loadxr_add_pat<load, v8i8, L4_loadrd_rr>; 2300 def: Loadxr_add_pat<load, f32, L4_loadri_rr>; 2301 def: Loadxr_add_pat<load, f64, L4_loadrd_rr>; 2302} 2303 2304let AddedComplexity = 40 in { 2305 def: Loadxrm_shl_pat<sextloadi1, i32, L1toI32, L4_loadrub_rr>; 2306 def: Loadxrm_shl_pat<extloadi1, i64, ToAext64, L4_loadrub_rr>; 2307 def: Loadxrm_shl_pat<sextloadi1, i64, L1toI64, L4_loadrub_rr>; 2308 def: Loadxrm_shl_pat<zextloadi1, i64, ToZext64, L4_loadrub_rr>; 2309 2310 def: Loadxrm_shl_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2311 def: Loadxrm_shl_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2312 def: Loadxrm_shl_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2313 def: Loadxrm_shl_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2314 def: Loadxrm_shl_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2315 def: Loadxrm_shl_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2316 def: Loadxrm_shl_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2317 def: Loadxrm_shl_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2318 def: Loadxrm_shl_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2319} 2320 2321let AddedComplexity = 30 in { 2322 def: Loadxrm_add_pat<sextloadi1, i32, L1toI32, L4_loadrub_rr>; 2323 def: Loadxrm_add_pat<extloadi1, i64, ToAext64, L4_loadrub_rr>; 2324 def: Loadxrm_add_pat<sextloadi1, i64, L1toI64, L4_loadrub_rr>; 2325 def: Loadxrm_add_pat<zextloadi1, i64, ToZext64, L4_loadrub_rr>; 2326 2327 def: Loadxrm_add_pat<extloadi8, i64, ToAext64, L4_loadrub_rr>; 2328 def: Loadxrm_add_pat<zextloadi8, i64, ToZext64, L4_loadrub_rr>; 2329 def: Loadxrm_add_pat<sextloadi8, i64, ToSext64, L4_loadrb_rr>; 2330 def: Loadxrm_add_pat<extloadi16, i64, ToAext64, L4_loadruh_rr>; 2331 def: Loadxrm_add_pat<zextloadi16, i64, ToZext64, L4_loadruh_rr>; 2332 def: Loadxrm_add_pat<sextloadi16, i64, ToSext64, L4_loadrh_rr>; 2333 def: Loadxrm_add_pat<extloadi32, i64, ToAext64, L4_loadri_rr>; 2334 def: Loadxrm_add_pat<zextloadi32, i64, ToZext64, L4_loadri_rr>; 2335 def: Loadxrm_add_pat<sextloadi32, i64, ToSext64, L4_loadri_rr>; 2336} 2337 2338// Absolute address 2339 2340let AddedComplexity = 60 in { 2341 def: Loada_pat<extloadi1, i32, anyimm0, PS_loadrubabs>; 2342 def: Loada_pat<zextloadi1, i32, anyimm0, PS_loadrubabs>; 2343 def: Loada_pat<extloadi8, i32, anyimm0, PS_loadrubabs>; 2344 def: Loada_pat<sextloadi8, i32, anyimm0, PS_loadrbabs>; 2345 def: Loada_pat<zextloadi8, i32, anyimm0, PS_loadrubabs>; 2346 def: Loada_pat<extloadi16, i32, anyimm1, PS_loadruhabs>; 2347 def: Loada_pat<sextloadi16, i32, anyimm1, PS_loadrhabs>; 2348 def: Loada_pat<zextloadi16, i32, anyimm1, PS_loadruhabs>; 2349 def: Loada_pat<load, i32, anyimm2, PS_loadriabs>; 2350 def: Loada_pat<load, v2i16, anyimm2, PS_loadriabs>; 2351 def: Loada_pat<load, v4i8, anyimm2, PS_loadriabs>; 2352 def: Loada_pat<load, i64, anyimm3, PS_loadrdabs>; 2353 def: Loada_pat<load, v2i32, anyimm3, PS_loadrdabs>; 2354 def: Loada_pat<load, v4i16, anyimm3, PS_loadrdabs>; 2355 def: Loada_pat<load, v8i8, anyimm3, PS_loadrdabs>; 2356 def: Loada_pat<load, f32, anyimm2, PS_loadriabs>; 2357 def: Loada_pat<load, f64, anyimm3, PS_loadrdabs>; 2358 2359 def: Loada_pat<atomic_load_8, i32, anyimm0, PS_loadrubabs>; 2360 def: Loada_pat<atomic_load_16, i32, anyimm1, PS_loadruhabs>; 2361 def: Loada_pat<atomic_load_32, i32, anyimm2, PS_loadriabs>; 2362 def: Loada_pat<atomic_load_64, i64, anyimm3, PS_loadrdabs>; 2363} 2364 2365let AddedComplexity = 30 in { 2366 def: Loadam_pat<load, i1, anyimm0, I32toI1, PS_loadrubabs>; 2367 def: Loadam_pat<sextloadi1, i32, anyimm0, L1toI32, PS_loadrubabs>; 2368 def: Loadam_pat<extloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>; 2369 def: Loadam_pat<sextloadi1, i64, anyimm0, L1toI64, PS_loadrubabs>; 2370 def: Loadam_pat<zextloadi1, i64, anyimm0, ToZext64, PS_loadrubabs>; 2371 2372 def: Loadam_pat<extloadi8, i64, anyimm0, ToAext64, PS_loadrubabs>; 2373 def: Loadam_pat<sextloadi8, i64, anyimm0, ToSext64, PS_loadrbabs>; 2374 def: Loadam_pat<zextloadi8, i64, anyimm0, ToZext64, PS_loadrubabs>; 2375 def: Loadam_pat<extloadi16, i64, anyimm1, ToAext64, PS_loadruhabs>; 2376 def: Loadam_pat<sextloadi16, i64, anyimm1, ToSext64, PS_loadrhabs>; 2377 def: Loadam_pat<zextloadi16, i64, anyimm1, ToZext64, PS_loadruhabs>; 2378 def: Loadam_pat<extloadi32, i64, anyimm2, ToAext64, PS_loadriabs>; 2379 def: Loadam_pat<sextloadi32, i64, anyimm2, ToSext64, PS_loadriabs>; 2380 def: Loadam_pat<zextloadi32, i64, anyimm2, ToZext64, PS_loadriabs>; 2381} 2382 2383// GP-relative address 2384 2385let AddedComplexity = 100 in { 2386 def: Loada_pat<extloadi1, i32, addrgp, L2_loadrubgp>; 2387 def: Loada_pat<zextloadi1, i32, addrgp, L2_loadrubgp>; 2388 def: Loada_pat<extloadi8, i32, addrgp, L2_loadrubgp>; 2389 def: Loada_pat<sextloadi8, i32, addrgp, L2_loadrbgp>; 2390 def: Loada_pat<zextloadi8, i32, addrgp, L2_loadrubgp>; 2391 def: Loada_pat<extloadi16, i32, addrgp, L2_loadruhgp>; 2392 def: Loada_pat<sextloadi16, i32, addrgp, L2_loadrhgp>; 2393 def: Loada_pat<zextloadi16, i32, addrgp, L2_loadruhgp>; 2394 def: Loada_pat<load, i32, addrgp, L2_loadrigp>; 2395 def: Loada_pat<load, v2i16, addrgp, L2_loadrigp>; 2396 def: Loada_pat<load, v4i8, addrgp, L2_loadrigp>; 2397 def: Loada_pat<load, i64, addrgp, L2_loadrdgp>; 2398 def: Loada_pat<load, v2i32, addrgp, L2_loadrdgp>; 2399 def: Loada_pat<load, v4i16, addrgp, L2_loadrdgp>; 2400 def: Loada_pat<load, v8i8, addrgp, L2_loadrdgp>; 2401 def: Loada_pat<load, f32, addrgp, L2_loadrigp>; 2402 def: Loada_pat<load, f64, addrgp, L2_loadrdgp>; 2403 2404 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>; 2405 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>; 2406 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>; 2407 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>; 2408} 2409 2410let AddedComplexity = 70 in { 2411 def: Loadam_pat<sextloadi1, i32, addrgp, L1toI32, L2_loadrubgp>; 2412 def: Loadam_pat<extloadi1, i64, addrgp, ToAext64, L2_loadrubgp>; 2413 def: Loadam_pat<sextloadi1, i64, addrgp, L1toI64, L2_loadrubgp>; 2414 def: Loadam_pat<zextloadi1, i64, addrgp, ToZext64, L2_loadrubgp>; 2415 2416 def: Loadam_pat<extloadi8, i64, addrgp, ToAext64, L2_loadrubgp>; 2417 def: Loadam_pat<sextloadi8, i64, addrgp, ToSext64, L2_loadrbgp>; 2418 def: Loadam_pat<zextloadi8, i64, addrgp, ToZext64, L2_loadrubgp>; 2419 def: Loadam_pat<extloadi16, i64, addrgp, ToAext64, L2_loadruhgp>; 2420 def: Loadam_pat<sextloadi16, i64, addrgp, ToSext64, L2_loadrhgp>; 2421 def: Loadam_pat<zextloadi16, i64, addrgp, ToZext64, L2_loadruhgp>; 2422 def: Loadam_pat<extloadi32, i64, addrgp, ToAext64, L2_loadrigp>; 2423 def: Loadam_pat<sextloadi32, i64, addrgp, ToSext64, L2_loadrigp>; 2424 def: Loadam_pat<zextloadi32, i64, addrgp, ToZext64, L2_loadrigp>; 2425 2426 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>; 2427} 2428 2429// Patterns for loads of i1: 2430def: Pat<(i1 (load AddrFI:$fi)), 2431 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>; 2432def: Pat<(i1 (load (add I32:$Rs, anyimm0:$Off))), 2433 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>; 2434def: Pat<(i1 (load I32:$Rs)), 2435 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>; 2436 2437 2438// --(13) Store ---------------------------------------------------------- 2439// 2440 2441class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset, InstHexagon MI> 2442 : Pat<(Store Value:$Rt, I32:$Rx, Offset:$s4), 2443 (MI I32:$Rx, imm:$s4, Value:$Rt)>; 2444 2445def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>; 2446def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>; 2447def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>; 2448def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>; 2449 2450// Patterns for generating stores, where the address takes different forms: 2451// - frameindex, 2452// - frameindex + offset, 2453// - base + offset, 2454// - simple (base address without offset). 2455// These would usually be used together (via Storexi_pat defined below), but 2456// in some cases one may want to apply different properties (such as 2457// AddedComplexity) to the individual patterns. 2458class Storexi_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2459 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>; 2460 2461multiclass Storexi_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2462 InstHexagon MI> { 2463 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2464 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2465 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2466 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 2467} 2468 2469multiclass Storexi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2470 InstHexagon MI> { 2471 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2472 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2473 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2474 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 2475} 2476 2477class Storexi_base_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2478 : Pat<(Store Value:$Rt, I32:$Rs), 2479 (MI IntRegs:$Rs, 0, Value:$Rt)>; 2480 2481// Patterns for generating stores, where the address takes different forms, 2482// and where the value being stored is transformed through the value modifier 2483// ValueMod. The address forms are same as above. 2484class Storexim_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2485 InstHexagon MI> 2486 : Pat<(Store Value:$Rs, AddrFI:$fi), 2487 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>; 2488 2489multiclass Storexim_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2490 PatFrag ValueMod, InstHexagon MI> { 2491 def: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 2492 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2493 def: Pat<(Store Value:$Rs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)), 2494 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 2495} 2496 2497multiclass Storexim_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 2498 PatFrag ValueMod, InstHexagon MI> { 2499 def: Pat<(Store Value:$Rt, (add I32:$Rs, ImmPred:$Off)), 2500 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2501 def: Pat<(Store Value:$Rt, (IsOrAdd I32:$Rs, ImmPred:$Off)), 2502 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 2503} 2504 2505class Storexim_base_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2506 InstHexagon MI> 2507 : Pat<(Store Value:$Rt, I32:$Rs), 2508 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>; 2509 2510multiclass Storexi_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2511 InstHexagon MI> { 2512 defm: Storexi_fi_add_pat <Store, Value, ImmPred, MI>; 2513 def: Storexi_fi_pat <Store, Value, MI>; 2514 defm: Storexi_add_pat <Store, Value, ImmPred, MI>; 2515} 2516 2517multiclass Storexim_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 2518 PatFrag ValueMod, InstHexagon MI> { 2519 defm: Storexim_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2520 def: Storexim_fi_pat <Store, Value, ValueMod, MI>; 2521 defm: Storexim_add_pat <Store, Value, ImmPred, ValueMod, MI>; 2522} 2523 2524// Reg<<S + Imm 2525class Storexu_shl_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, InstHexagon MI> 2526 : Pat<(Store Value:$Rt, (add (shl I32:$Ru, u2_0ImmPred:$u2), ImmPred:$A)), 2527 (MI IntRegs:$Ru, imm:$u2, ImmPred:$A, Value:$Rt)>; 2528 2529// Reg<<S + Reg 2530class Storexr_shl_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2531 : Pat<(Store Value:$Ru, (add I32:$Rs, (shl I32:$Rt, u2_0ImmPred:$u2))), 2532 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>; 2533 2534// Reg + Reg 2535class Storexr_add_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2536 : Pat<(Store Value:$Ru, (add I32:$Rs, I32:$Rt)), 2537 (MI IntRegs:$Rs, IntRegs:$Rt, 0, Value:$Ru)>; 2538 2539class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI> 2540 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>; 2541 2542class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod, 2543 InstHexagon MI> 2544 : Pat<(Store Value:$val, Addr:$addr), 2545 (MI Addr:$addr, (ValueMod Value:$val))>; 2546 2547// Regular stores in the DAG have two operands: value and address. 2548// Atomic stores also have two, but they are reversed: address, value. 2549// To use atomic stores with the patterns, they need to have their operands 2550// swapped. This relies on the knowledge that the F.Fragment uses names 2551// "ptr" and "val". 2552class AtomSt<PatFrag F> 2553 : PatFrag<(ops node:$val, node:$ptr), !head(F.Fragments), F.PredicateCode, 2554 F.OperandTransform> { 2555 let IsAtomic = F.IsAtomic; 2556 let MemoryVT = F.MemoryVT; 2557} 2558 2559 2560def IMM_BYTE : SDNodeXForm<imm, [{ 2561 // -1 can be represented as 255, etc. 2562 // assigning to a byte restores our desired signed value. 2563 int8_t imm = N->getSExtValue(); 2564 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2565}]>; 2566 2567def IMM_HALF : SDNodeXForm<imm, [{ 2568 // -1 can be represented as 65535, etc. 2569 // assigning to a short restores our desired signed value. 2570 int16_t imm = N->getSExtValue(); 2571 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2572}]>; 2573 2574def IMM_WORD : SDNodeXForm<imm, [{ 2575 // -1 can be represented as 4294967295, etc. 2576 // Currently, it's not doing this. But some optimization 2577 // might convert -1 to a large +ve number. 2578 // assigning to a word restores our desired signed value. 2579 int32_t imm = N->getSExtValue(); 2580 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32); 2581}]>; 2582 2583def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>; 2584def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>; 2585def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>; 2586 2587// Even though the offset is not extendable in the store-immediate, we 2588// can still generate the fi# in the base address. If the final offset 2589// is not valid for the instruction, we will replace it with a scratch 2590// register. 2591class SmallStackStore<PatFrag Store> 2592 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2593 return isSmallStackStore(cast<StoreSDNode>(N)); 2594}]>; 2595 2596// This is the complement of SmallStackStore. 2597class LargeStackStore<PatFrag Store> 2598 : PatFrag<(ops node:$Val, node:$Addr), (Store node:$Val, node:$Addr), [{ 2599 return !isSmallStackStore(cast<StoreSDNode>(N)); 2600}]>; 2601 2602// Preferred addressing modes for various combinations of stored value 2603// and address computation. 2604// For stores where the address and value are both immediates, prefer 2605// store-immediate. The reason is that the constant-extender optimization 2606// can replace store-immediate with a store-register, but there is nothing 2607// to generate a store-immediate out of a store-register. 2608// 2609// C R F F+C R+C R+R R<<S+C R<<S+R 2610// --+-------+-----+-----+------+-----+-----+--------+-------- 2611// C | imm | imm | imm | imm | imm | rr | ur | rr 2612// R | abs* | io | io | io | io | rr | ur | rr 2613// 2614// (*) Absolute or GP-relative. 2615// 2616// Note that any expression can be matched by Reg. In particular, an immediate 2617// can always be placed in a register, so patterns checking for Imm should 2618// have a higher priority than the ones involving Reg that could also match. 2619// For example, *(p+4) could become r1=#4; memw(r0+r1<<#0) instead of the 2620// preferred memw(r0+#4). Similarly Reg+Imm or Reg+Reg should be tried before 2621// Reg alone. 2622// 2623// The order in which the different combinations are tried: 2624// 2625// C F R F+C R+C R+R R<<S+C R<<S+R 2626// --+-------+-----+-----+------+-----+-----+--------+-------- 2627// C | 1 | 6 | - | 5 | 9 | - | - | - 2628// R | 2 | 8 | 12 | 7 | 10 | 11 | 3 | 4 2629 2630 2631// First, match the unusual case of doubleword store into Reg+Imm4, i.e. 2632// a store where the offset Imm4 is a multiple of 4, but not of 8. This 2633// implies that Reg is also a proper multiple of 4. To still generate a 2634// doubleword store, add 4 to Reg, and subtract 4 from the offset. 2635 2636def s30_2ProperPred : PatLeaf<(i32 imm), [{ 2637 int64_t v = (int64_t)N->getSExtValue(); 2638 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v); 2639}]>; 2640def RoundTo8 : SDNodeXForm<imm, [{ 2641 int32_t Imm = N->getSExtValue(); 2642 return CurDAG->getTargetConstant(Imm & -8, SDLoc(N), MVT::i32); 2643}]>; 2644 2645let AddedComplexity = 150 in 2646def: Pat<(store I64:$Ru, (add I32:$Rs, s30_2ProperPred:$Off)), 2647 (S2_storerd_io (A2_addi I32:$Rs, 4), (RoundTo8 $Off), I64:$Ru)>; 2648 2649class Storexi_abs_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 2650 : Pat<(Store Value:$val, anyimm:$addr), 2651 (MI (ToI32 $addr), 0, Value:$val)>; 2652class Storexim_abs_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 2653 InstHexagon MI> 2654 : Pat<(Store Value:$val, anyimm:$addr), 2655 (MI (ToI32 $addr), 0, (ValueMod Value:$val))>; 2656 2657let AddedComplexity = 140 in { 2658 def: Storexim_abs_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2659 def: Storexim_abs_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2660 def: Storexim_abs_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2661 2662 def: Storexi_abs_pat<truncstorei8, anyimm, S4_storeirb_io>; 2663 def: Storexi_abs_pat<truncstorei16, anyimm, S4_storeirh_io>; 2664 def: Storexi_abs_pat<store, anyimm, S4_storeiri_io>; 2665} 2666 2667// GP-relative address 2668let AddedComplexity = 120 in { 2669 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>; 2670 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>; 2671 def: Storea_pat<store, I32, addrgp, S2_storerigp>; 2672 def: Storea_pat<store, V4I8, addrgp, S2_storerigp>; 2673 def: Storea_pat<store, V2I16, addrgp, S2_storerigp>; 2674 def: Storea_pat<store, I64, addrgp, S2_storerdgp>; 2675 def: Storea_pat<store, V8I8, addrgp, S2_storerdgp>; 2676 def: Storea_pat<store, V4I16, addrgp, S2_storerdgp>; 2677 def: Storea_pat<store, V2I32, addrgp, S2_storerdgp>; 2678 def: Storea_pat<store, F32, addrgp, S2_storerigp>; 2679 def: Storea_pat<store, F64, addrgp, S2_storerdgp>; 2680 def: Storea_pat<AtomSt<atomic_store_8>, I32, addrgp, S2_storerbgp>; 2681 def: Storea_pat<AtomSt<atomic_store_16>, I32, addrgp, S2_storerhgp>; 2682 def: Storea_pat<AtomSt<atomic_store_32>, I32, addrgp, S2_storerigp>; 2683 def: Storea_pat<AtomSt<atomic_store_32>, V4I8, addrgp, S2_storerigp>; 2684 def: Storea_pat<AtomSt<atomic_store_32>, V2I16, addrgp, S2_storerigp>; 2685 def: Storea_pat<AtomSt<atomic_store_64>, I64, addrgp, S2_storerdgp>; 2686 def: Storea_pat<AtomSt<atomic_store_64>, V8I8, addrgp, S2_storerdgp>; 2687 def: Storea_pat<AtomSt<atomic_store_64>, V4I16, addrgp, S2_storerdgp>; 2688 def: Storea_pat<AtomSt<atomic_store_64>, V2I32, addrgp, S2_storerdgp>; 2689 2690 def: Stoream_pat<truncstorei8, I64, addrgp, LoReg, S2_storerbgp>; 2691 def: Stoream_pat<truncstorei16, I64, addrgp, LoReg, S2_storerhgp>; 2692 def: Stoream_pat<truncstorei32, I64, addrgp, LoReg, S2_storerigp>; 2693 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>; 2694} 2695 2696// Absolute address 2697let AddedComplexity = 110 in { 2698 def: Storea_pat<truncstorei8, I32, anyimm0, PS_storerbabs>; 2699 def: Storea_pat<truncstorei16, I32, anyimm1, PS_storerhabs>; 2700 def: Storea_pat<store, I32, anyimm2, PS_storeriabs>; 2701 def: Storea_pat<store, V4I8, anyimm2, PS_storeriabs>; 2702 def: Storea_pat<store, V2I16, anyimm2, PS_storeriabs>; 2703 def: Storea_pat<store, I64, anyimm3, PS_storerdabs>; 2704 def: Storea_pat<store, V8I8, anyimm3, PS_storerdabs>; 2705 def: Storea_pat<store, V4I16, anyimm3, PS_storerdabs>; 2706 def: Storea_pat<store, V2I32, anyimm3, PS_storerdabs>; 2707 def: Storea_pat<store, F32, anyimm2, PS_storeriabs>; 2708 def: Storea_pat<store, F64, anyimm3, PS_storerdabs>; 2709 def: Storea_pat<AtomSt<atomic_store_8>, I32, anyimm0, PS_storerbabs>; 2710 def: Storea_pat<AtomSt<atomic_store_16>, I32, anyimm1, PS_storerhabs>; 2711 def: Storea_pat<AtomSt<atomic_store_32>, I32, anyimm2, PS_storeriabs>; 2712 def: Storea_pat<AtomSt<atomic_store_32>, V4I8, anyimm2, PS_storeriabs>; 2713 def: Storea_pat<AtomSt<atomic_store_32>, V2I16, anyimm2, PS_storeriabs>; 2714 def: Storea_pat<AtomSt<atomic_store_64>, I64, anyimm3, PS_storerdabs>; 2715 def: Storea_pat<AtomSt<atomic_store_64>, V8I8, anyimm3, PS_storerdabs>; 2716 def: Storea_pat<AtomSt<atomic_store_64>, V4I16, anyimm3, PS_storerdabs>; 2717 def: Storea_pat<AtomSt<atomic_store_64>, V2I32, anyimm3, PS_storerdabs>; 2718 2719 def: Stoream_pat<truncstorei8, I64, anyimm0, LoReg, PS_storerbabs>; 2720 def: Stoream_pat<truncstorei16, I64, anyimm1, LoReg, PS_storerhabs>; 2721 def: Stoream_pat<truncstorei32, I64, anyimm2, LoReg, PS_storeriabs>; 2722 def: Stoream_pat<store, I1, anyimm0, I1toI32, PS_storerbabs>; 2723} 2724 2725// Reg<<S + Imm 2726let AddedComplexity = 100 in { 2727 def: Storexu_shl_pat<truncstorei8, I32, anyimm0, S4_storerb_ur>; 2728 def: Storexu_shl_pat<truncstorei16, I32, anyimm1, S4_storerh_ur>; 2729 def: Storexu_shl_pat<store, I32, anyimm2, S4_storeri_ur>; 2730 def: Storexu_shl_pat<store, V4I8, anyimm2, S4_storeri_ur>; 2731 def: Storexu_shl_pat<store, V2I16, anyimm2, S4_storeri_ur>; 2732 def: Storexu_shl_pat<store, I64, anyimm3, S4_storerd_ur>; 2733 def: Storexu_shl_pat<store, V8I8, anyimm3, S4_storerd_ur>; 2734 def: Storexu_shl_pat<store, V4I16, anyimm3, S4_storerd_ur>; 2735 def: Storexu_shl_pat<store, V2I32, anyimm3, S4_storerd_ur>; 2736 def: Storexu_shl_pat<store, F32, anyimm2, S4_storeri_ur>; 2737 def: Storexu_shl_pat<store, F64, anyimm3, S4_storerd_ur>; 2738 2739 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), anyimm:$A)), 2740 (S4_storerb_ur IntRegs:$Rs, imm:$u2, imm:$A, (I1toI32 I1:$Pu))>; 2741} 2742 2743// Reg<<S + Reg 2744let AddedComplexity = 90 in { 2745 def: Storexr_shl_pat<truncstorei8, I32, S4_storerb_rr>; 2746 def: Storexr_shl_pat<truncstorei16, I32, S4_storerh_rr>; 2747 def: Storexr_shl_pat<store, I32, S4_storeri_rr>; 2748 def: Storexr_shl_pat<store, V4I8, S4_storeri_rr>; 2749 def: Storexr_shl_pat<store, V2I16, S4_storeri_rr>; 2750 def: Storexr_shl_pat<store, I64, S4_storerd_rr>; 2751 def: Storexr_shl_pat<store, V8I8, S4_storerd_rr>; 2752 def: Storexr_shl_pat<store, V4I16, S4_storerd_rr>; 2753 def: Storexr_shl_pat<store, V2I32, S4_storerd_rr>; 2754 def: Storexr_shl_pat<store, F32, S4_storeri_rr>; 2755 def: Storexr_shl_pat<store, F64, S4_storerd_rr>; 2756 2757 def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), I32:$Rt)), 2758 (S4_storerb_ur IntRegs:$Rt, IntRegs:$Rs, imm:$u2, (I1toI32 I1:$Pu))>; 2759} 2760 2761class SS_<PatFrag F> : SmallStackStore<F>; 2762class LS_<PatFrag F> : LargeStackStore<F>; 2763 2764multiclass IMFA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2765 defm: Storexim_fi_add_pat<S, V, O, M, I>; 2766} 2767multiclass IFA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2768 defm: Storexi_fi_add_pat<S, V, O, I>; 2769} 2770 2771// Fi+Imm, store-immediate 2772let AddedComplexity = 80 in { 2773 defm: IMFA_<SS_<truncstorei8>, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2774 defm: IMFA_<SS_<truncstorei16>, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2775 defm: IMFA_<SS_<store>, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2776 2777 defm: IFA_<SS_<truncstorei8>, anyimm, u6_0ImmPred, S4_storeirb_io>; 2778 defm: IFA_<SS_<truncstorei16>, anyimm, u6_1ImmPred, S4_storeirh_io>; 2779 defm: IFA_<SS_<store>, anyimm, u6_2ImmPred, S4_storeiri_io>; 2780 2781 // For large-stack stores, generate store-register (prefer explicit Fi 2782 // in the address). 2783 defm: IMFA_<LS_<truncstorei8>, anyimm, u6_0ImmPred, ToI32, S2_storerb_io>; 2784 defm: IMFA_<LS_<truncstorei16>, anyimm, u6_1ImmPred, ToI32, S2_storerh_io>; 2785 defm: IMFA_<LS_<store>, anyimm, u6_2ImmPred, ToI32, S2_storeri_io>; 2786} 2787 2788// Fi, store-immediate 2789let AddedComplexity = 70 in { 2790 def: Storexim_fi_pat<SS_<truncstorei8>, anyint, ToImmByte, S4_storeirb_io>; 2791 def: Storexim_fi_pat<SS_<truncstorei16>, anyint, ToImmHalf, S4_storeirh_io>; 2792 def: Storexim_fi_pat<SS_<store>, anyint, ToImmWord, S4_storeiri_io>; 2793 2794 def: Storexi_fi_pat<SS_<truncstorei8>, anyimm, S4_storeirb_io>; 2795 def: Storexi_fi_pat<SS_<truncstorei16>, anyimm, S4_storeirh_io>; 2796 def: Storexi_fi_pat<SS_<store>, anyimm, S4_storeiri_io>; 2797 2798 // For large-stack stores, generate store-register (prefer explicit Fi 2799 // in the address). 2800 def: Storexim_fi_pat<LS_<truncstorei8>, anyimm, ToI32, S2_storerb_io>; 2801 def: Storexim_fi_pat<LS_<truncstorei16>, anyimm, ToI32, S2_storerh_io>; 2802 def: Storexim_fi_pat<LS_<store>, anyimm, ToI32, S2_storeri_io>; 2803} 2804 2805// Fi+Imm, Fi, store-register 2806let AddedComplexity = 60 in { 2807 defm: Storexi_fi_add_pat<truncstorei8, I32, anyimm, S2_storerb_io>; 2808 defm: Storexi_fi_add_pat<truncstorei16, I32, anyimm, S2_storerh_io>; 2809 defm: Storexi_fi_add_pat<store, I32, anyimm, S2_storeri_io>; 2810 defm: Storexi_fi_add_pat<store, V4I8, anyimm, S2_storeri_io>; 2811 defm: Storexi_fi_add_pat<store, V2I16, anyimm, S2_storeri_io>; 2812 defm: Storexi_fi_add_pat<store, I64, anyimm, S2_storerd_io>; 2813 defm: Storexi_fi_add_pat<store, V8I8, anyimm, S2_storerd_io>; 2814 defm: Storexi_fi_add_pat<store, V4I16, anyimm, S2_storerd_io>; 2815 defm: Storexi_fi_add_pat<store, V2I32, anyimm, S2_storerd_io>; 2816 defm: Storexi_fi_add_pat<store, F32, anyimm, S2_storeri_io>; 2817 defm: Storexi_fi_add_pat<store, F64, anyimm, S2_storerd_io>; 2818 defm: Storexim_fi_add_pat<store, I1, anyimm, I1toI32, S2_storerb_io>; 2819 2820 def: Storexi_fi_pat<truncstorei8, I32, S2_storerb_io>; 2821 def: Storexi_fi_pat<truncstorei16, I32, S2_storerh_io>; 2822 def: Storexi_fi_pat<store, I32, S2_storeri_io>; 2823 def: Storexi_fi_pat<store, V4I8, S2_storeri_io>; 2824 def: Storexi_fi_pat<store, V2I16, S2_storeri_io>; 2825 def: Storexi_fi_pat<store, I64, S2_storerd_io>; 2826 def: Storexi_fi_pat<store, V8I8, S2_storerd_io>; 2827 def: Storexi_fi_pat<store, V4I16, S2_storerd_io>; 2828 def: Storexi_fi_pat<store, V2I32, S2_storerd_io>; 2829 def: Storexi_fi_pat<store, F32, S2_storeri_io>; 2830 def: Storexi_fi_pat<store, F64, S2_storerd_io>; 2831 def: Storexim_fi_pat<store, I1, I1toI32, S2_storerb_io>; 2832} 2833 2834 2835multiclass IMRA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> { 2836 defm: Storexim_add_pat<S, V, O, M, I>; 2837} 2838multiclass IRA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> { 2839 defm: Storexi_add_pat<S, V, O, I>; 2840} 2841 2842// Reg+Imm, store-immediate 2843let AddedComplexity = 50 in { 2844 defm: IMRA_<truncstorei8, anyint, u6_0ImmPred, ToImmByte, S4_storeirb_io>; 2845 defm: IMRA_<truncstorei16, anyint, u6_1ImmPred, ToImmHalf, S4_storeirh_io>; 2846 defm: IMRA_<store, anyint, u6_2ImmPred, ToImmWord, S4_storeiri_io>; 2847 2848 defm: IRA_<truncstorei8, anyimm, u6_0ImmPred, S4_storeirb_io>; 2849 defm: IRA_<truncstorei16, anyimm, u6_1ImmPred, S4_storeirh_io>; 2850 defm: IRA_<store, anyimm, u6_2ImmPred, S4_storeiri_io>; 2851} 2852 2853// Reg+Imm, store-register 2854let AddedComplexity = 40 in { 2855 defm: Storexi_pat<truncstorei8, I32, anyimm0, S2_storerb_io>; 2856 defm: Storexi_pat<truncstorei16, I32, anyimm1, S2_storerh_io>; 2857 defm: Storexi_pat<store, I32, anyimm2, S2_storeri_io>; 2858 defm: Storexi_pat<store, V4I8, anyimm2, S2_storeri_io>; 2859 defm: Storexi_pat<store, V2I16, anyimm2, S2_storeri_io>; 2860 defm: Storexi_pat<store, I64, anyimm3, S2_storerd_io>; 2861 defm: Storexi_pat<store, V8I8, anyimm3, S2_storerd_io>; 2862 defm: Storexi_pat<store, V4I16, anyimm3, S2_storerd_io>; 2863 defm: Storexi_pat<store, V2I32, anyimm3, S2_storerd_io>; 2864 defm: Storexi_pat<store, F32, anyimm2, S2_storeri_io>; 2865 defm: Storexi_pat<store, F64, anyimm3, S2_storerd_io>; 2866 2867 defm: Storexim_pat<truncstorei8, I64, anyimm0, LoReg, S2_storerb_io>; 2868 defm: Storexim_pat<truncstorei16, I64, anyimm1, LoReg, S2_storerh_io>; 2869 defm: Storexim_pat<truncstorei32, I64, anyimm2, LoReg, S2_storeri_io>; 2870 defm: Storexim_pat<store, I1, anyimm0, I1toI32, S2_storerb_io>; 2871 2872 defm: Storexi_pat<AtomSt<atomic_store_8>, I32, anyimm0, S2_storerb_io>; 2873 defm: Storexi_pat<AtomSt<atomic_store_16>, I32, anyimm1, S2_storerh_io>; 2874 defm: Storexi_pat<AtomSt<atomic_store_32>, I32, anyimm2, S2_storeri_io>; 2875 defm: Storexi_pat<AtomSt<atomic_store_32>, V4I8, anyimm2, S2_storeri_io>; 2876 defm: Storexi_pat<AtomSt<atomic_store_32>, V2I16, anyimm2, S2_storeri_io>; 2877 defm: Storexi_pat<AtomSt<atomic_store_64>, I64, anyimm3, S2_storerd_io>; 2878 defm: Storexi_pat<AtomSt<atomic_store_64>, V8I8, anyimm3, S2_storerd_io>; 2879 defm: Storexi_pat<AtomSt<atomic_store_64>, V4I16, anyimm3, S2_storerd_io>; 2880 defm: Storexi_pat<AtomSt<atomic_store_64>, V2I32, anyimm3, S2_storerd_io>; 2881} 2882 2883// Reg+Reg 2884let AddedComplexity = 30 in { 2885 def: Storexr_add_pat<truncstorei8, I32, S4_storerb_rr>; 2886 def: Storexr_add_pat<truncstorei16, I32, S4_storerh_rr>; 2887 def: Storexr_add_pat<store, I32, S4_storeri_rr>; 2888 def: Storexr_add_pat<store, V4I8, S4_storeri_rr>; 2889 def: Storexr_add_pat<store, V2I16, S4_storeri_rr>; 2890 def: Storexr_add_pat<store, I64, S4_storerd_rr>; 2891 def: Storexr_add_pat<store, V8I8, S4_storerd_rr>; 2892 def: Storexr_add_pat<store, V4I16, S4_storerd_rr>; 2893 def: Storexr_add_pat<store, V2I32, S4_storerd_rr>; 2894 def: Storexr_add_pat<store, F32, S4_storeri_rr>; 2895 def: Storexr_add_pat<store, F64, S4_storerd_rr>; 2896 2897 def: Pat<(store I1:$Pu, (add I32:$Rs, I32:$Rt)), 2898 (S4_storerb_rr IntRegs:$Rs, IntRegs:$Rt, 0, (I1toI32 I1:$Pu))>; 2899} 2900 2901// Reg, store-immediate 2902let AddedComplexity = 20 in { 2903 def: Storexim_base_pat<truncstorei8, anyint, ToImmByte, S4_storeirb_io>; 2904 def: Storexim_base_pat<truncstorei16, anyint, ToImmHalf, S4_storeirh_io>; 2905 def: Storexim_base_pat<store, anyint, ToImmWord, S4_storeiri_io>; 2906 2907 def: Storexi_base_pat<truncstorei8, anyimm, S4_storeirb_io>; 2908 def: Storexi_base_pat<truncstorei16, anyimm, S4_storeirh_io>; 2909 def: Storexi_base_pat<store, anyimm, S4_storeiri_io>; 2910} 2911 2912// Reg, store-register 2913let AddedComplexity = 10 in { 2914 def: Storexi_base_pat<truncstorei8, I32, S2_storerb_io>; 2915 def: Storexi_base_pat<truncstorei16, I32, S2_storerh_io>; 2916 def: Storexi_base_pat<store, I32, S2_storeri_io>; 2917 def: Storexi_base_pat<store, V4I8, S2_storeri_io>; 2918 def: Storexi_base_pat<store, V2I16, S2_storeri_io>; 2919 def: Storexi_base_pat<store, I64, S2_storerd_io>; 2920 def: Storexi_base_pat<store, V8I8, S2_storerd_io>; 2921 def: Storexi_base_pat<store, V4I16, S2_storerd_io>; 2922 def: Storexi_base_pat<store, V2I32, S2_storerd_io>; 2923 def: Storexi_base_pat<store, F32, S2_storeri_io>; 2924 def: Storexi_base_pat<store, F64, S2_storerd_io>; 2925 2926 def: Storexim_base_pat<truncstorei8, I64, LoReg, S2_storerb_io>; 2927 def: Storexim_base_pat<truncstorei16, I64, LoReg, S2_storerh_io>; 2928 def: Storexim_base_pat<truncstorei32, I64, LoReg, S2_storeri_io>; 2929 def: Storexim_base_pat<store, I1, I1toI32, S2_storerb_io>; 2930 2931 def: Storexi_base_pat<AtomSt<atomic_store_8>, I32, S2_storerb_io>; 2932 def: Storexi_base_pat<AtomSt<atomic_store_16>, I32, S2_storerh_io>; 2933 def: Storexi_base_pat<AtomSt<atomic_store_32>, I32, S2_storeri_io>; 2934 def: Storexi_base_pat<AtomSt<atomic_store_32>, V4I8, S2_storeri_io>; 2935 def: Storexi_base_pat<AtomSt<atomic_store_32>, V2I16, S2_storeri_io>; 2936 def: Storexi_base_pat<AtomSt<atomic_store_64>, I64, S2_storerd_io>; 2937 def: Storexi_base_pat<AtomSt<atomic_store_64>, V8I8, S2_storerd_io>; 2938 def: Storexi_base_pat<AtomSt<atomic_store_64>, V4I16, S2_storerd_io>; 2939 def: Storexi_base_pat<AtomSt<atomic_store_64>, V2I32, S2_storerd_io>; 2940} 2941 2942 2943// --(14) Memop ---------------------------------------------------------- 2944// 2945 2946def m5_0Imm8Pred : PatLeaf<(i32 imm), [{ 2947 int8_t V = N->getSExtValue(); 2948 return -32 < V && V <= -1; 2949}]>; 2950 2951def m5_0Imm16Pred : PatLeaf<(i32 imm), [{ 2952 int16_t V = N->getSExtValue(); 2953 return -32 < V && V <= -1; 2954}]>; 2955 2956def m5_0ImmPred : PatLeaf<(i32 imm), [{ 2957 int64_t V = N->getSExtValue(); 2958 return -31 <= V && V <= -1; 2959}]>; 2960 2961def IsNPow2_8 : PatLeaf<(i32 imm), [{ 2962 uint8_t NV = ~N->getZExtValue(); 2963 return isPowerOf2_32(NV); 2964}]>; 2965 2966def IsNPow2_16 : PatLeaf<(i32 imm), [{ 2967 uint16_t NV = ~N->getZExtValue(); 2968 return isPowerOf2_32(NV); 2969}]>; 2970 2971def Log2_8 : SDNodeXForm<imm, [{ 2972 uint8_t V = N->getZExtValue(); 2973 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 2974}]>; 2975 2976def Log2_16 : SDNodeXForm<imm, [{ 2977 uint16_t V = N->getZExtValue(); 2978 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32); 2979}]>; 2980 2981def LogN2_8 : SDNodeXForm<imm, [{ 2982 uint8_t NV = ~N->getZExtValue(); 2983 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 2984}]>; 2985 2986def LogN2_16 : SDNodeXForm<imm, [{ 2987 uint16_t NV = ~N->getZExtValue(); 2988 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32); 2989}]>; 2990 2991def IdImm : SDNodeXForm<imm, [{ return SDValue(N, 0); }]>; 2992 2993multiclass Memopxr_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 2994 InstHexagon MI> { 2995 // Addr: i32 2996 def: Pat<(Store (Oper (Load I32:$Rs), I32:$A), I32:$Rs), 2997 (MI I32:$Rs, 0, I32:$A)>; 2998 // Addr: fi 2999 def: Pat<(Store (Oper (Load AddrFI:$Rs), I32:$A), AddrFI:$Rs), 3000 (MI AddrFI:$Rs, 0, I32:$A)>; 3001} 3002 3003multiclass Memopxr_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3004 SDNode Oper, InstHexagon MI> { 3005 // Addr: i32 3006 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), I32:$A), 3007 (add I32:$Rs, ImmPred:$Off)), 3008 (MI I32:$Rs, imm:$Off, I32:$A)>; 3009 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), I32:$A), 3010 (IsOrAdd I32:$Rs, ImmPred:$Off)), 3011 (MI I32:$Rs, imm:$Off, I32:$A)>; 3012 // Addr: fi 3013 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), I32:$A), 3014 (add AddrFI:$Rs, ImmPred:$Off)), 3015 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 3016 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), I32:$A), 3017 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 3018 (MI AddrFI:$Rs, imm:$Off, I32:$A)>; 3019} 3020 3021multiclass Memopxr_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3022 SDNode Oper, InstHexagon MI> { 3023 let Predicates = [UseMEMOPS] in { 3024 defm: Memopxr_base_pat <Load, Store, Oper, MI>; 3025 defm: Memopxr_add_pat <Load, Store, ImmPred, Oper, MI>; 3026 } 3027} 3028 3029let AddedComplexity = 200 in { 3030 // add reg 3031 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, add, 3032 /*anyext*/ L4_add_memopb_io>; 3033 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, 3034 /*sext*/ L4_add_memopb_io>; 3035 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, 3036 /*zext*/ L4_add_memopb_io>; 3037 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, add, 3038 /*anyext*/ L4_add_memoph_io>; 3039 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, 3040 /*sext*/ L4_add_memoph_io>; 3041 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, 3042 /*zext*/ L4_add_memoph_io>; 3043 defm: Memopxr_pat<load, store, u6_2ImmPred, add, L4_add_memopw_io>; 3044 3045 // sub reg 3046 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, 3047 /*anyext*/ L4_sub_memopb_io>; 3048 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, 3049 /*sext*/ L4_sub_memopb_io>; 3050 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, 3051 /*zext*/ L4_sub_memopb_io>; 3052 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, 3053 /*anyext*/ L4_sub_memoph_io>; 3054 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, 3055 /*sext*/ L4_sub_memoph_io>; 3056 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, 3057 /*zext*/ L4_sub_memoph_io>; 3058 defm: Memopxr_pat<load, store, u6_2ImmPred, sub, L4_sub_memopw_io>; 3059 3060 // and reg 3061 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, and, 3062 /*anyext*/ L4_and_memopb_io>; 3063 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, 3064 /*sext*/ L4_and_memopb_io>; 3065 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, 3066 /*zext*/ L4_and_memopb_io>; 3067 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, and, 3068 /*anyext*/ L4_and_memoph_io>; 3069 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, 3070 /*sext*/ L4_and_memoph_io>; 3071 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, 3072 /*zext*/ L4_and_memoph_io>; 3073 defm: Memopxr_pat<load, store, u6_2ImmPred, and, L4_and_memopw_io>; 3074 3075 // or reg 3076 defm: Memopxr_pat<extloadi8, truncstorei8, u6_0ImmPred, or, 3077 /*anyext*/ L4_or_memopb_io>; 3078 defm: Memopxr_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, 3079 /*sext*/ L4_or_memopb_io>; 3080 defm: Memopxr_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, 3081 /*zext*/ L4_or_memopb_io>; 3082 defm: Memopxr_pat<extloadi16, truncstorei16, u6_1ImmPred, or, 3083 /*anyext*/ L4_or_memoph_io>; 3084 defm: Memopxr_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, 3085 /*sext*/ L4_or_memoph_io>; 3086 defm: Memopxr_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, 3087 /*zext*/ L4_or_memoph_io>; 3088 defm: Memopxr_pat<load, store, u6_2ImmPred, or, L4_or_memopw_io>; 3089} 3090 3091 3092multiclass Memopxi_base_pat<PatFrag Load, PatFrag Store, SDNode Oper, 3093 PatFrag Arg, SDNodeXForm ArgMod, InstHexagon MI> { 3094 // Addr: i32 3095 def: Pat<(Store (Oper (Load I32:$Rs), Arg:$A), I32:$Rs), 3096 (MI I32:$Rs, 0, (ArgMod Arg:$A))>; 3097 // Addr: fi 3098 def: Pat<(Store (Oper (Load AddrFI:$Rs), Arg:$A), AddrFI:$Rs), 3099 (MI AddrFI:$Rs, 0, (ArgMod Arg:$A))>; 3100} 3101 3102multiclass Memopxi_add_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3103 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 3104 InstHexagon MI> { 3105 // Addr: i32 3106 def: Pat<(Store (Oper (Load (add I32:$Rs, ImmPred:$Off)), Arg:$A), 3107 (add I32:$Rs, ImmPred:$Off)), 3108 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3109 def: Pat<(Store (Oper (Load (IsOrAdd I32:$Rs, ImmPred:$Off)), Arg:$A), 3110 (IsOrAdd I32:$Rs, ImmPred:$Off)), 3111 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3112 // Addr: fi 3113 def: Pat<(Store (Oper (Load (add AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 3114 (add AddrFI:$Rs, ImmPred:$Off)), 3115 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3116 def: Pat<(Store (Oper (Load (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), Arg:$A), 3117 (IsOrAdd AddrFI:$Rs, ImmPred:$Off)), 3118 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>; 3119} 3120 3121multiclass Memopxi_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred, 3122 SDNode Oper, PatFrag Arg, SDNodeXForm ArgMod, 3123 InstHexagon MI> { 3124 let Predicates = [UseMEMOPS] in { 3125 defm: Memopxi_base_pat <Load, Store, Oper, Arg, ArgMod, MI>; 3126 defm: Memopxi_add_pat <Load, Store, ImmPred, Oper, Arg, ArgMod, MI>; 3127 } 3128} 3129 3130let AddedComplexity = 220 in { 3131 // add imm 3132 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3133 /*anyext*/ IdImm, L4_iadd_memopb_io>; 3134 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3135 /*sext*/ IdImm, L4_iadd_memopb_io>; 3136 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred, 3137 /*zext*/ IdImm, L4_iadd_memopb_io>; 3138 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3139 /*anyext*/ IdImm, L4_iadd_memoph_io>; 3140 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3141 /*sext*/ IdImm, L4_iadd_memoph_io>; 3142 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred, 3143 /*zext*/ IdImm, L4_iadd_memoph_io>; 3144 defm: Memopxi_pat<load, store, u6_2ImmPred, add, u5_0ImmPred, IdImm, 3145 L4_iadd_memopw_io>; 3146 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3147 /*anyext*/ NegImm8, L4_iadd_memopb_io>; 3148 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3149 /*sext*/ NegImm8, L4_iadd_memopb_io>; 3150 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred, 3151 /*zext*/ NegImm8, L4_iadd_memopb_io>; 3152 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3153 /*anyext*/ NegImm16, L4_iadd_memoph_io>; 3154 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3155 /*sext*/ NegImm16, L4_iadd_memoph_io>; 3156 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred, 3157 /*zext*/ NegImm16, L4_iadd_memoph_io>; 3158 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, m5_0ImmPred, NegImm32, 3159 L4_iadd_memopw_io>; 3160 3161 // sub imm 3162 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3163 /*anyext*/ IdImm, L4_isub_memopb_io>; 3164 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3165 /*sext*/ IdImm, L4_isub_memopb_io>; 3166 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred, 3167 /*zext*/ IdImm, L4_isub_memopb_io>; 3168 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3169 /*anyext*/ IdImm, L4_isub_memoph_io>; 3170 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3171 /*sext*/ IdImm, L4_isub_memoph_io>; 3172 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred, 3173 /*zext*/ IdImm, L4_isub_memoph_io>; 3174 defm: Memopxi_pat<load, store, u6_2ImmPred, sub, u5_0ImmPred, IdImm, 3175 L4_isub_memopw_io>; 3176 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3177 /*anyext*/ NegImm8, L4_isub_memopb_io>; 3178 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3179 /*sext*/ NegImm8, L4_isub_memopb_io>; 3180 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred, 3181 /*zext*/ NegImm8, L4_isub_memopb_io>; 3182 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3183 /*anyext*/ NegImm16, L4_isub_memoph_io>; 3184 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3185 /*sext*/ NegImm16, L4_isub_memoph_io>; 3186 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred, 3187 /*zext*/ NegImm16, L4_isub_memoph_io>; 3188 defm: Memopxi_pat<load, store, u6_2ImmPred, add, m5_0ImmPred, NegImm32, 3189 L4_isub_memopw_io>; 3190 3191 // clrbit imm 3192 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3193 /*anyext*/ LogN2_8, L4_iand_memopb_io>; 3194 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3195 /*sext*/ LogN2_8, L4_iand_memopb_io>; 3196 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, and, IsNPow2_8, 3197 /*zext*/ LogN2_8, L4_iand_memopb_io>; 3198 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3199 /*anyext*/ LogN2_16, L4_iand_memoph_io>; 3200 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3201 /*sext*/ LogN2_16, L4_iand_memoph_io>; 3202 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, IsNPow2_16, 3203 /*zext*/ LogN2_16, L4_iand_memoph_io>; 3204 defm: Memopxi_pat<load, store, u6_2ImmPred, and, IsNPow2_32, 3205 LogN2_32, L4_iand_memopw_io>; 3206 3207 // setbit imm 3208 defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3209 /*anyext*/ Log2_8, L4_ior_memopb_io>; 3210 defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3211 /*sext*/ Log2_8, L4_ior_memopb_io>; 3212 defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, or, IsPow2_32, 3213 /*zext*/ Log2_8, L4_ior_memopb_io>; 3214 defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3215 /*anyext*/ Log2_16, L4_ior_memoph_io>; 3216 defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3217 /*sext*/ Log2_16, L4_ior_memoph_io>; 3218 defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, or, IsPow2_32, 3219 /*zext*/ Log2_16, L4_ior_memoph_io>; 3220 defm: Memopxi_pat<load, store, u6_2ImmPred, or, IsPow2_32, 3221 Log2_32, L4_ior_memopw_io>; 3222} 3223 3224 3225// --(15) Call ----------------------------------------------------------- 3226// 3227 3228// Pseudo instructions. 3229def SDT_SPCallSeqStart 3230 : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3231def SDT_SPCallSeqEnd 3232 : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3233 3234def callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 3235 [SDNPHasChain, SDNPOutGlue]>; 3236def callseq_end: SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 3237 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 3238 3239def SDT_SPCall: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 3240 3241def HexagonTCRet: SDNode<"HexagonISD::TC_RETURN", SDT_SPCall, 3242 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3243def callv3: SDNode<"HexagonISD::CALL", SDT_SPCall, 3244 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3245def callv3nr: SDNode<"HexagonISD::CALLnr", SDT_SPCall, 3246 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 3247 3248def: Pat<(callseq_start timm:$amt, timm:$amt2), 3249 (ADJCALLSTACKDOWN imm:$amt, imm:$amt2)>; 3250def: Pat<(callseq_end timm:$amt1, timm:$amt2), 3251 (ADJCALLSTACKUP imm:$amt1, imm:$amt2)>; 3252 3253def: Pat<(HexagonTCRet tglobaladdr:$dst), (PS_tailcall_i tglobaladdr:$dst)>; 3254def: Pat<(HexagonTCRet texternalsym:$dst), (PS_tailcall_i texternalsym:$dst)>; 3255def: Pat<(HexagonTCRet I32:$dst), (PS_tailcall_r I32:$dst)>; 3256 3257def: Pat<(callv3 I32:$dst), (J2_callr I32:$dst)>; 3258def: Pat<(callv3 tglobaladdr:$dst), (J2_call tglobaladdr:$dst)>; 3259def: Pat<(callv3 texternalsym:$dst), (J2_call texternalsym:$dst)>; 3260def: Pat<(callv3 tglobaltlsaddr:$dst), (J2_call tglobaltlsaddr:$dst)>; 3261 3262def: Pat<(callv3nr I32:$dst), (PS_callr_nr I32:$dst)>; 3263def: Pat<(callv3nr tglobaladdr:$dst), (PS_call_nr tglobaladdr:$dst)>; 3264def: Pat<(callv3nr texternalsym:$dst), (PS_call_nr texternalsym:$dst)>; 3265 3266def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone, 3267 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 3268def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>; 3269 3270def: Pat<(retflag), (PS_jmpret (i32 R31))>; 3271def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>; 3272 3273 3274// --(16) Branch --------------------------------------------------------- 3275// 3276 3277def: Pat<(br bb:$dst), (J2_jump b30_2Imm:$dst)>; 3278def: Pat<(brind I32:$dst), (J2_jumpr I32:$dst)>; 3279 3280def: Pat<(brcond I1:$Pu, bb:$dst), 3281 (J2_jumpt I1:$Pu, bb:$dst)>; 3282def: Pat<(brcond (not I1:$Pu), bb:$dst), 3283 (J2_jumpf I1:$Pu, bb:$dst)>; 3284def: Pat<(brcond (i1 (setne I1:$Pu, -1)), bb:$dst), 3285 (J2_jumpf I1:$Pu, bb:$dst)>; 3286def: Pat<(brcond (i1 (seteq I1:$Pu, 0)), bb:$dst), 3287 (J2_jumpf I1:$Pu, bb:$dst)>; 3288def: Pat<(brcond (i1 (setne I1:$Pu, 0)), bb:$dst), 3289 (J2_jumpt I1:$Pu, bb:$dst)>; 3290 3291 3292// --(17) Misc ----------------------------------------------------------- 3293 3294 3295// Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)' 3296// for C code of the form r = (c>='0' && c<='9') ? 1 : 0. 3297// The isdigit transformation relies on two 'clever' aspects: 3298// 1) The data type is unsigned which allows us to eliminate a zero test after 3299// biasing the expression by 48. We are depending on the representation of 3300// the unsigned types, and semantics. 3301// 2) The front end has converted <= 9 into < 10 on entry to LLVM. 3302// 3303// For the C code: 3304// retval = (c >= '0' && c <= '9') ? 1 : 0; 3305// The code is transformed upstream of llvm into 3306// retval = (c-48) < 10 ? 1 : 0; 3307 3308def u7_0PosImmPred : ImmLeaf<i32, [{ 3309 // True if the immediate fits in an 7-bit unsigned field and is positive. 3310 return Imm > 0 && isUInt<7>(Imm); 3311}]>; 3312 3313let AddedComplexity = 139 in 3314def: Pat<(i32 (zext (i1 (setult (and I32:$Rs, 255), u7_0PosImmPred:$u7)))), 3315 (C2_muxii (A4_cmpbgtui IntRegs:$Rs, (UDEC1 imm:$u7)), 0, 1)>; 3316 3317let AddedComplexity = 100 in 3318def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))), 3319 (i32 (extloadi8 (add I32:$b, 3))), 3320 24, 8), 3321 (i32 16)), 3322 (shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))), 3323 (zextloadi8 I32:$b)), 3324 (A2_swiz (L2_loadri_io I32:$b, 0))>; 3325 3326 3327// We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH 3328// because the SDNode ISD::PREFETCH has properties MayLoad and MayStore. 3329// We don't really want either one here. 3330def SDTHexagonDCFETCH: SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>; 3331def HexagonDCFETCH: SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH, 3332 [SDNPHasChain]>; 3333 3334def: Pat<(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3), 3335 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3336def: Pat<(HexagonDCFETCH (i32 (add IntRegs:$Rs, u11_3ImmPred:$u11_3)), (i32 0)), 3337 (Y2_dcfetchbo IntRegs:$Rs, imm:$u11_3)>; 3338 3339def SDTHexagonALLOCA 3340 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 3341def HexagonALLOCA 3342 : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, [SDNPHasChain]>; 3343 3344def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)), 3345 (PS_alloca IntRegs:$Rs, imm:$A)>; 3346 3347def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>; 3348def: Pat<(HexagonBARRIER), (Y2_barrier)>; 3349 3350def: Pat<(trap), (PS_crash)>; 3351 3352// Read cycle counter. 3353def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 3354def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf, 3355 [SDNPHasChain]>; 3356 3357def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>; 3358 3359// The declared return value of the store-locked intrinsics is i32, but 3360// the instructions actually define i1. To avoid register copies from 3361// IntRegs to PredRegs and back, fold the entire pattern checking the 3362// result against true/false. 3363let AddedComplexity = 100 in { 3364 def: Pat<(i1 (setne (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3365 (S2_storew_locked I32:$Rs, I32:$Rt)>; 3366 def: Pat<(i1 (seteq (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)), 3367 (C2_not (S2_storew_locked I32:$Rs, I32:$Rt))>; 3368 def: Pat<(i1 (setne (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3369 (S4_stored_locked I32:$Rs, I64:$Rt)>; 3370 def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), 3371 (C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>; 3372} 3373 3374def: Pat<(int_hexagon_instrprof_custom (HexagonAtPcrel tglobaladdr:$addr), u32_0ImmPred:$I), 3375 (PS_call_instrprof_custom tglobaladdr:$addr, imm:$I)>; 3376 3377def: Pat<(int_hexagon_instrprof_custom (HexagonCONST32 tglobaladdr:$addr), u32_0ImmPred:$I), 3378 (PS_call_instrprof_custom tglobaladdr:$addr, imm:$I)>; 3379