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Searched refs:v8i8 (Results 1 – 25 of 52) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonCallingConv.td17 CCIfType<[i64,v2i32,v4i16,v8i8],
43 CCIfType<[i64,v2i32,v4i16,v8i8],
45 CCIfType<[i64,v2i32,v4i16,v8i8],
73 CCIfType<[i64,v2i32,v4i16,v8i8],
75 CCIfType<[i64,v2i32,v4i16,v8i8],
99 CCIfType<[i64,v2i32,v4i16,v8i8],
H A DHexagonPatterns.td86 def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>;
483 defm: NopCast_pat<i64, v8i8, DoubleRegs>;
485 defm: NopCast_pat<v2i32, v8i8, DoubleRegs>;
486 defm: NopCast_pat<v4i16, v8i8, DoubleRegs>;
535 def: Pat<(v8i8 (azext V8I1:$Pu)),
997 def: OpR_RR_pat<A2_vminb, Smin, v8i8, V8I8>;
1049 def: Pat<(v8i8 (splat_vector anyint:$V)),
1066 def: Pat<(v8i8 (splat_vector I32:$Rs)),
1590 (LoReg (Mulhsb8 (v8i8 (ToAext64 $Rs)), (v8i8 (ToAext64 $Rt))))>;
1826 // Multiplies two v8i8 vectors.
[all …]
H A DHexagonISelLowering.cpp639 VT == MVT::v4i16 || VT == MVT::v8i8 || in getPostIndexedAddressParts()
1473 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1689 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1711 for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1722 for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8, in HexagonTargetLowering()
1734 for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16, in HexagonTargetLowering()
1752 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in HexagonTargetLowering()
1791 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) { in HexagonTargetLowering()
2850 SDValue A = DAG.getBitcast(MVT::v8i8, Vec64); in contractPredicate()
2851 SDValue S = DAG.getVectorShuffle(MVT::v8i8, dl, A, DAG.getUNDEF(MVT::v8i8), in contractPredicate()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td658 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^ADD(v1i64|v2i32|v4i16|v8i8)$")>;
660 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v8i8$")>;
662 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^NEG(v1i64|v2i32|v4i16|v8i8)$")>;
663 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^SUB(v1i64|v2i32|v4i16|v8i8)$")>;
672 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CMTST(v1i64|v2i32|v4i16|v8i8)$")>;
674 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^SHL(v2i32|v4i16|v8i8)_shift$")>;
677 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v2i32|v4i16|v8i8)$")>;
686 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)RHADD(v2i32|v4i16|v8i8)$")>;
715 def : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^(S|U)ABA(v2i32|v4i16|v8i8)$")>;
738 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^PMULL(v8i8|v16i8)$")>;
[all …]
H A DAArch64SchedKryoDetails.td33 (instregex "(S|U)ABA(v8i8|v4i16|v2i32)")>;
57 (instregex "(S|U)(ABD|RHADD)(v8i8|v4i16|v2i32)")>;
69 (instregex "(S|U)ADALP(v8i8|v4i16|v2i32)_v.*")>;
201 (instregex "^(S|U)QADD(v8i8|v4i16|v2i32)")>;
435 …(instregex "((AND|ORN|EOR|EON)S?(Wr[rsi]|v8i8|v4i16|v2i32)|(ORR|BIC)S?(Wr[rs]|v8i8|v4i16|v2i32))")…
507 (instregex "(CLS|CLZ|CNT)(v2i32|v4i16|v8i8)")>;
573 (instregex "DUP(v8i8|v4i16|v2i32)(gpr|lane)")>;
1668 (instregex "NEG(v8i8|v4i16|v2i32|v1i64)")>;
1830 (instregex "SQ(ABS|NEG)(v8i8|v4i16|v2i32)")>;
2177 (instregex "^(SU|US)QADD(v8i8|v4i16|v2i32)")>;
[all …]
H A DAArch64TargetTransformInfo.cpp385 {Intrinsic::bitreverse, MVT::v8i8, 1}, in getIntrinsicInstrCost()
421 {ISD::CTPOP, MVT::v8i8, 1}, in getIntrinsicInstrCost()
2090 {ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f16, 2}, in getCastInstrCost()
3014 {ISD::ADD, MVT::v8i8, 2}, in getArithmeticReductionCost()
3020 {ISD::OR, MVT::v8i8, 15}, in getArithmeticReductionCost()
3027 {ISD::XOR, MVT::v8i8, 15}, in getArithmeticReductionCost()
3034 {ISD::AND, MVT::v8i8, 15}, in getArithmeticReductionCost()
3227 {TTI::SK_Broadcast, MVT::v8i8, 1}, in getShuffleCost()
3239 {TTI::SK_Transpose, MVT::v8i8, 1}, in getShuffleCost()
3284 {TTI::SK_Reverse, MVT::v8i8, 1}, // REV64 in getShuffleCost()
[all …]
H A DAArch64ISelDAGToDAG.cpp5078 if (VT == MVT::v8i8) { in Select()
5106 if (VT == MVT::v8i8) { in Select()
5134 if (VT == MVT::v8i8) { in Select()
5162 if (VT == MVT::v8i8) { in Select()
5190 if (VT == MVT::v8i8) { in Select()
5218 if (VT == MVT::v8i8) { in Select()
5246 if (VT == MVT::v8i8) { in Select()
5274 if (VT == MVT::v8i8) { in Select()
5302 if (VT == MVT::v8i8) { in Select()
5330 if (VT == MVT::v8i8) { in Select()
[all …]
H A DAArch64CallingConvention.td33 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8],
106 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
114 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16],
131 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8],
143 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
172 CCIfType<[f64, v1f64, v1i64, v2f32, v2i32, v4i16, v4f16, v4bf16, v8i8, iPTR],
257 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
273 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16],
294 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
316 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
[all …]
H A DAArch64InstrInfo.td1127 def v8i8 : BaseSIMDSUDOTIndex<0, ".2s", ".8b", ".4b", V64, v2i32, v8i8>;
4498 def : Pat<(v8i8 (AArch64vashr (v8i8 V64:$Rn), (i32 7))),
5448 (vecopnode (v8i8 V64:$Rn),(v8i8 V64:$Rm)),
5629 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
7877 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
7878 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
7879 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
7880 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
7881 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
7882 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
[all …]
H A DAArch64SchedA57.td350 // D form - v8i8, v4i16, v2i32
362 def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)…
369 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
378 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
384 def : InstRW<[A57Write_5cyc_1W_Mul_Forward], (instregex "^MUL(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i…
386 def : InstRW<[A57Write_5cyc_1W], (instregex "^(PMUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1…
399 def : InstRW<[A57Write_5cyc_1W_Mul_Forward, A57ReadIVMA4], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_i…
411 def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>;
428 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
521 // D form - v8i8, v4i16, v2i32
H A DAArch64InstrFormats.td5601 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5639 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5683 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
5706 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5734 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5862 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
6110 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
6135 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
6396 v8i8, v8i8, OpNode>;
6707 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))))]>;
[all …]
H A DAArch64SchedTSV110.td549 // D form - v8i8, v4i16, v2i32
581 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v8i8|v4i16|v2i32|v1i8|v1i…
587 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v8i8|v16i8)")>;
602 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16…
608 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
617 def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
H A DAArch64SchedThunderX2T99.td1281 def : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^PMULL(v8i8|v16i8)")>;
1286 (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>;
1295 (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
1307 (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
1314 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1321 (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>;
1343 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
1350 (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;
H A DAArch64SchedThunderX3T110.td1389 def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^PMULL(v8i8|v16i8)")>;
1394 (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>;
1403 (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
1415 (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
1422 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1429 (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>;
1451 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
1458 (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;
H A DAArch64SchedA55.td423 def : InstRW<[CortexA55WriteAluVd_1], (instregex "(AND|EOR|NOT|ORN)v8i8",
460 def : InstRW<[CortexA55WriteAluVd_3], (instregex "[SU]SRA(d|v2i32|v4i16|v8i8)")>;
471 def : InstRW<[CortexA55WriteAluVd_3], (instregex "[SU]RSHR(d|v2i32|v4i16|v8i8)",
H A DAArch64SchedA64FX.td1406 def : InstRW<[A64FXWrite_8Cyc_GI03], (instregex "^PMULL(v8i8|v16i8)")>;
1411 (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>;
1420 (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
1432 (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
1439 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1452 (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>;
1480 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
1487 (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstrNEON.td5930 def : Pat<(v8i8 (ARMvshls (v8i8 DPR:$Dn), (v8i8 DPR:$Dm))),
5947 def : Pat<(v8i8 (ARMvshlu (v8i8 DPR:$Dn), (v8i8 DPR:$Dm))),
7230 def : Pat<(v8i8 (NEONvtbl2 v8i8:$Vn0, v8i8:$Vn1, v8i8:$Vm)),
7234 def : Pat<(v8i8 (int_arm_neon_vtbx2 v8i8:$orig, v8i8:$Vn0, v8i8:$Vn1,
7236 (v8i8 (VTBX2 v8i8:$orig,
7241 def : Pat<(v8i8 (int_arm_neon_vtbl3 v8i8:$Vn0, v8i8:$Vn1,
7248 def : Pat<(v8i8 (int_arm_neon_vtbx3 v8i8:$orig, v8i8:$Vn0, v8i8:$Vn1,
7257 def : Pat<(v8i8 (int_arm_neon_vtbl4 v8i8:$Vn0, v8i8:$Vn1,
7258 v8i8:$Vn2, v8i8:$Vn3, v8i8:$Vm)),
7264 def : Pat<(v8i8 (int_arm_neon_vtbx4 v8i8:$orig, v8i8:$Vn0, v8i8:$Vn1,
[all …]
H A DARMCallingConv.td33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
186 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
213 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
236 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
H A DARMTargetTransformInfo.cpp574 {ISD::TRUNCATE, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost()
576 {ISD::TRUNCATE, MVT::v8i32, MVT::v8i8, 1}, in getCastInstrCost()
605 { ISD::ADD, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
608 { ISD::SUB, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
611 { ISD::MUL, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
614 { ISD::SHL, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
665 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
666 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
667 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
1224 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, in getShuffleCost()
[all …]
H A DARMScheduleA57.td977 (instregex "VABA(s|u)(v8i8|v4i16|v2i32)")>;
1020 "VMUL(v8i8|v4i16|v2i32|pd)", "VMULsl(v4i16|v2i32)",
1042 (instregex "VMLA(sl)?(v8i8|v4i16|v2i32)", "VMLS(sl)?(v8i8|v4i16|v2i32)")>;
1119 "VSLI(v8i8|v4i16|v2i32|v1i64)", "VSRI(v8i8|v4i16|v2i32|v1i64)")>;
1127 "VSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;
1136 "VQRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)", "VQSHL(s|u)(v8i8|v4i16|v2i32|v1i64)",
1137 "VRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;
1212 "VMOV(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v1i64|v2i64|v2f32|v4f32)",
H A DARMScheduleR52.td764 def : InstRW<[R52WriteFPALU_F5, R52Read_F1, R52Read_F1, R52Read_F1], (instregex "VABA(u|s)(v8i8|v4i…
768 def : InstRW<[R52WriteFPALU_F4, R52Read_F1, R52Read_F1], (instregex "VABD(u|s)(v8i8|v4i16|v2i32)")>;
775 (instregex "(VADD|VSUB)(v8i8|v4i16|v2i32|v1i64)")>;
779 (instregex "(VADDHN|VRADDHN|VSUBHN|VRSUBHN)(v8i8|v4i16|v2i32)")>;
809 def : InstRW<[R52WriteFPALU_F4, R52Read_F2, R52Read_F2], (instregex "(VHADD|VHSUB)(u|s)(v8i8|v4i16|…
819 def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VQABS(v8i8|v4i16|v2i32|v1i64)")>;
822 (instregex "(VQADD|VQSUB)(u|s)(v8i8|v4i16|v2i32|v1i64)")>;
/openbsd/gnu/llvm/llvm/include/llvm/Support/
H A DMachineValueType.h88 v8i8 = 36, // 8 x i8 enumerator
419 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 || in is64BitVector()
573 case v8i8: in getVectorElementType()
814 case v8i8: in getVectorMinNumElements()
987 case v8i8: in getSizeInBits()
1294 if (NumElements == 8) return MVT::v8i8; in getVectorVT()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp510 {Intrinsic::vp_fshl, MVT::v8i8, 7},
548 {Intrinsic::vp_fshr, MVT::v8i8, 7},
586 {Intrinsic::bitreverse, MVT::v8i8, 17},
621 {Intrinsic::vp_bitreverse, MVT::v8i8, 17},
656 {Intrinsic::ctpop, MVT::v8i8, 12},
691 {Intrinsic::vp_ctpop, MVT::v8i8, 12},
726 {Intrinsic::vp_ctlz, MVT::v8i8, 19},
764 {Intrinsic::vp_cttz, MVT::v8i8, 16},
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2091 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, in getCastInstrCost()
2110 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, in getCastInstrCost()
2128 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, in getCastInstrCost()
2241 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, in getCastInstrCost()
2242 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, in getCastInstrCost()
2277 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, in getCastInstrCost()
2278 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, in getCastInstrCost()
2321 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, in getCastInstrCost()
4957 { ISD::ADD, MVT::v8i8, 2 }, in getArithmeticReductionCost()
5344 {ISD::SMIN, MVT::v8i8, 7}, // pminsb in getMinMaxReductionCost()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td151 [i64, f64, v8i8, v4i16, v2i32, v2f32], 64,
275 defm VR64 : SystemZRegClass<"VR64", [f64, v8i8, v4i16, v2i32, v2f32], 64,

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