/qemu/target/mips/tcg/ |
H A D | tx79_translate.c | 259 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen); in trans_parallel_compare() 434 tcg_gen_deposit_i64(cpu_gpr[a->rd], b0, t0, 32, 32); in trans_PPACW() 437 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32); in trans_PPACW() 443 tcg_gen_deposit_i64(dl, b, a, 32, 32); in gen_pextw() 445 tcg_gen_deposit_i64(dh, a, b, 0, 32); in gen_pextw() 465 tcg_gen_deposit_i64(cpu_gpr[a->rd], in trans_PEXTLx() 467 tcg_gen_deposit_i64(cpu_gpr[a->rd], in trans_PEXTLx() 474 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], in trans_PEXTLx() 476 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], in trans_PEXTLx() 637 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, cpu_gpr[a->rt], 0, 32); in trans_PROT3W() [all …]
|
H A D | translate.c | 1393 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32); in gen_store_fpr32() 1410 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32); in gen_store_fpr32h() 1431 tcg_gen_deposit_i64(fpu_f64[reg & ~1], fpu_f64[reg & ~1], t, 0, 32); in gen_store_fpr64() 1434 tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32); in gen_store_fpr64() 3977 tcg_gen_deposit_i64(t0, t0, t1, 0, 16); in gen_loongson_multimedia() 3980 tcg_gen_deposit_i64(t0, t0, t1, 16, 16); in gen_loongson_multimedia() 3983 tcg_gen_deposit_i64(t0, t0, t1, 32, 16); in gen_loongson_multimedia() 3986 tcg_gen_deposit_i64(t0, t0, t1, 48, 16); in gen_loongson_multimedia() 5057 tcg_gen_deposit_i64(t1, t1, t0, 30, 32); in gen_mthc0_entrylo()
|
/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_farith.c.inc | 76 tcg_gen_deposit_i64(dest, src1, src2, 0, 31); 94 tcg_gen_deposit_i64(dest, src1, src2, 0, 63);
|
H A D | trans_fmov.c.inc | 139 tcg_gen_deposit_i64(dest, dest, src, 0, 32); 144 tcg_gen_deposit_i64(dest, dest, src, 32, 32);
|
/qemu/target/ppc/translate/ |
H A D | vsx-impl.c.inc | 93 tcg_gen_deposit_i64(xth, t1, t0, 32, 32); 97 tcg_gen_deposit_i64(xtl, t1, t0, 32, 32); 185 tcg_gen_deposit_i64(outh, outh, hi, 32, 32); 187 tcg_gen_deposit_i64(outl, outl, lo, 32, 32); 334 tcg_gen_deposit_i64(t1, t0, xsh, 32, 32); 338 tcg_gen_deposit_i64(t1, t0, xsl, 32, 32); 2006 tcg_gen_deposit_i64(rt, t0, t1, 0, 52); 2036 tcg_gen_deposit_i64(xth, t0, xbh, 0, 48); 2105 tcg_gen_deposit_i64(xth, xah, xbh, 52, 11); 2203 tcg_gen_deposit_i64(xth, t0, xbh, 0, 52); [all …]
|
H A D | fp-impl.c.inc | 412 tcg_gen_deposit_i64(t2, t0, t1, 0, 63); 434 tcg_gen_deposit_i64(t1, t0, b0, 0, 32); 452 tcg_gen_deposit_i64(t2, t0, t1, 32, 32);
|
H A D | vmx-impl.c.inc | 363 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32); 369 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32); 384 tcg_gen_deposit_i64(avr, t0, t1, 32, 32); 389 tcg_gen_deposit_i64(avr, t0, t1, 32, 32); 3014 tcg_gen_deposit_i64(t, hh, lh, 0, 32);
|
/qemu/target/s390x/tcg/ |
H A D | translate.c | 180 tcg_gen_deposit_i64(out, out, tcg_constant_i64(pc), 0, 32); in pc_to_link_info() 325 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32); in store_reg32_i64() 330 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32); in store_reg32h_i64() 2111 tcg_gen_deposit_i64(o->out, o->out, old, 0, 32); in op_csp() 2323 tcg_gen_deposit_i64(t, t, t_cc, 12, 2); in op_epsw() 2444 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len); in op_icm() 2493 tcg_gen_deposit_i64(t1, t1, t2, 4, 60); in op_ipm() 2494 tcg_gen_deposit_i64(o->out, o->out, t1, 24, 8); in op_ipm() 3812 tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2); in op_sam() 3997 tcg_gen_deposit_i64(tmp, tmp, o->addr1, 4, 3); in op_srnmt() [all …]
|
/qemu/target/riscv/insn_trans/ |
H A D | trans_rvzfh.c.inc | 258 tcg_gen_deposit_i64(dest, rs2, rs1, 0, 15); 260 tcg_gen_deposit_i64(dest, src2, src1, 0, 15);
|
H A D | trans_rvd.c.inc | 250 tcg_gen_deposit_i64(dest, src2, src1, 0, 63); 272 tcg_gen_deposit_i64(dest, t0, src1, 0, 63);
|
H A D | trans_rvf.c.inc | 256 tcg_gen_deposit_i64(dest, rs2, rs1, 0, 31); 258 tcg_gen_deposit_i64(dest, src2, src1, 0, 31);
|
H A D | trans_xthead.c.inc | 454 tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32);
|
/qemu/target/hexagon/ |
H A D | genptr.c | 327 tcg_gen_deposit_i64(result, result, src64, N * 16, 16); in gen_set_half_i64() 334 tcg_gen_deposit_i64(result, result, src64, N * 8, 8); in gen_set_byte_i64() 1310 tcg_gen_deposit_i64(mask, mask, bits, j, size); in vec_to_qvec()
|
H A D | gen_tcg.h | 268 tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 48, 16); \ 297 tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 56, 8); \
|
/qemu/include/tcg/ |
H A D | tcg-op.h | 246 #define tcg_gen_deposit_tl tcg_gen_deposit_i64
|
H A D | tcg-op-common.h | 215 void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
|
/qemu/target/hppa/ |
H A D | translate.c | 2587 tcg_gen_deposit_i64(addr, addr, load_gpr(ctx, a->b), 0, 4); in do_pxtlb() 3246 tcg_gen_deposit_i64(dst, r1, tmp, 0, 32); in gen_mixw_l() 3256 tcg_gen_deposit_i64(dst, r2, r1, 32, 32); in gen_mixw_r() 3285 tcg_gen_deposit_i64(t0, t1, t0, 16, 48); in trans_permh() 3286 tcg_gen_deposit_i64(t2, t3, t2, 16, 48); in trans_permh() 3287 tcg_gen_deposit_i64(t0, t2, t0, 32, 32); in trans_permh() 3888 tcg_gen_deposit_i64(dest, cpu_gr[rs], val, a->cpos, len); in trans_dep_imm()
|
/qemu/tcg/ |
H A D | tcg-op.c | 2611 void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, in tcg_gen_deposit_i64() function 2975 tcg_gen_deposit_i64(ret, t0, ah, 64 - ofs, ofs); in tcg_gen_extract2_i64() 3213 tcg_gen_deposit_i64(dest, dest, tmp, 32, 32); in tcg_gen_concat_i32_i64() 3240 tcg_gen_deposit_i64(ret, lo, hi, 32, 32); in tcg_gen_concat32_i64()
|
H A D | tcg-op-gvec.c | 419 tcg_gen_deposit_i64(out, in, in, 32, 32); in tcg_gen_dup_i64() 1912 tcg_gen_deposit_i64(d, t1, t2, 0, 32); in tcg_gen_vec_add32_i64() 2095 tcg_gen_deposit_i64(d, t1, t2, 0, 32); in tcg_gen_vec_sub32_i64() 2483 tcg_gen_deposit_i64(d, t1, t2, 0, 32); in tcg_gen_vec_neg32_i64()
|
/qemu/target/rx/ |
H A D | translate.c | 1783 tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 32, 32); in trans_MVTACHI() 1793 tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 0, 32); in trans_MVTACLO()
|
/qemu/target/arm/tcg/ |
H A D | gengvec.c | 682 tcg_gen_deposit_i64(d, d, a, 0, 64 - shift); in gen_shr64_ins_i64() 770 tcg_gen_deposit_i64(d, d, a, shift, 64 - shift); in gen_shl64_ins_i64()
|
H A D | translate-a64.c | 4514 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_im, pos, 16); in trans_MOVK() 4613 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); in trans_BFM() 8892 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, 0, esize - shift); in handle_scalar_simd_shri() 8926 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, shift, 64 - shift); in handle_scalar_simd_shli() 9008 tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); in handle_vec_simd_sqshrn() 10378 tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); in handle_vec_simd_shrn() 11168 tcg_gen_deposit_i64(tcg_rd[w], tcg_rd[w], tcg_rn, o, esize); in handle_rev()
|
H A D | translate-sve.c | 4117 tcg_gen_deposit_i64(t0, t0, t1, 32, 32); in gen_sve_ldr() 6574 tcg_gen_deposit_i64(d, d, n, 32, 32); in gen_shrnt64_i64()
|
/qemu/target/ppc/ |
H A D | translate.c | 2010 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); in gen_rlwimi() 2066 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); in gen_rlwinm() 2113 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); in gen_rlwnm()
|
/qemu/target/alpha/ |
H A D | translate.c | 686 tcg_gen_deposit_i64(vc, vc, tmp, 0, 30); in gen_cvtlq()
|