/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitTracker.cpp | 119 if (RC.contains(Reg)) in getPhysRegBitWidth() 248 RegisterRefs Reg(MI); in evaluate() local 254 if (Reg.size() == 0) in evaluate() 311 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; in evaluate() 314 unsigned Reg0 = Reg[0].Reg; in evaluate() 333 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() 356 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); in evaluate() 438 RegisterCell RPC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() 758 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate() 770 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32); in evaluate() [all …]
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H A D | HexagonGenMux.cpp | 123 bool isRegPair(unsigned Reg) const { in isRegPair() 124 return Hexagon::DoubleRegsRegClass.contains(Reg); in isRegPair() 127 void getSubRegs(unsigned Reg, BitVector &SRs) const; 128 void expandReg(unsigned Reg, BitVector &Set) const; 147 for (MCPhysReg I : HRI->subregs(Reg)) in getSubRegs() 151 void HexagonGenMux::expandReg(unsigned Reg, BitVector &Set) const { in expandReg() argument 152 if (isRegPair(Reg)) in expandReg() 153 getSubRegs(Reg, Set); in expandReg() 155 Set[Reg] = true; in expandReg() 351 auto IsLive = [&LPR, this](unsigned Reg) -> bool { in genMuxInBlock() argument [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 422 markSuperRegs(Reserved, Reg); in getReservedRegs() 429 if (Reg == 0) in getReservedRegs() 431 markSuperRegs(Reserved, Reg); in getReservedRegs() 487 Register Reg = CSI.getReg(); in requiresFrameIndexScavenging() local 980 Register Reg1 = Reg; in lowerCRSpilling() 1025 Register Reg1 = Reg; in lowerCRRestore() 1139 Register Reg1 = Reg; in lowerCRBitSpilling() 1194 .addReg(Reg, RegState::Kill) in lowerCRBitRestore() 1325 Register Reg = in lowerACCSpilling() local 1370 Register Reg = in lowerACCRestore() local [all …]
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H A D | PPCVSXSwapRemoval.cpp | 161 if (Register::isVirtualRegister(Reg)) in isRegInClass() 163 return RC->contains(Reg); in isRegInClass() 167 bool isVecReg(unsigned Reg) { in isVecReg() 173 bool isScalarVecReg(unsigned Reg) { in isScalarVecReg() 182 if (isScalarVecReg(Reg)) in isAnyVecReg() 184 return isScalarVecReg(Reg) || isVecReg(Reg); in isAnyVecReg() 256 Register Reg = MO.getReg(); in gatherVectorInstructions() local 260 if (isAnyVecReg(Reg, Partial)) in gatherVectorInstructions() 607 Register Reg = MO.getReg(); in formWebs() local 608 if (!isVecReg(Reg) && !isScalarVecReg(Reg)) in formWebs() [all …]
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H A D | PPCCallingConv.cpp | 154 unsigned Reg = State.AllocateReg(HiRegList); in CC_PPC32_SPE_CustomSplitFP64() local 155 if (!Reg) in CC_PPC32_SPE_CustomSplitFP64() 160 if (HiRegList[i] == Reg) in CC_PPC32_SPE_CustomSplitFP64() 167 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in CC_PPC32_SPE_CustomSplitFP64() 183 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in CC_PPC32_SPE_RetF64() local 184 if (!Reg) in CC_PPC32_SPE_RetF64() 189 if (HiRegList[i] == Reg) in CC_PPC32_SPE_RetF64() 192 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); in CC_PPC32_SPE_RetF64()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86CompressEVEX.cpp | 95 auto isHiRegIdx = [](unsigned Reg) { in usesExtendedRegister() argument 97 if (Reg >= X86::XMM16 && Reg <= X86::XMM31) in usesExtendedRegister() 100 if (Reg >= X86::YMM16 && Reg <= X86::YMM31) in usesExtendedRegister() 103 if (X86II::isApxExtendedReg(Reg)) in usesExtendedRegister() 114 Register Reg = MO.getReg(); in usesExtendedRegister() local 115 assert(!X86II::isZMMReg(Reg) && in usesExtendedRegister() 117 if (isHiRegIdx(Reg)) in usesExtendedRegister()
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H A D | X86MachineFunctionInfo.h | 193 void setSRetReturnReg(Register Reg) { SRetReturnReg = Reg; } in setSRetReturnReg() argument 196 void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; } in setGlobalBaseReg() argument 247 bool isCandidateForPush2Pop2(Register Reg) const { in isCandidateForPush2Pop2() argument 248 return CandidatesForPush2Pop2.find(Reg) != CandidatesForPush2Pop2.end(); in isCandidateForPush2Pop2() 250 void addCandidateForPush2Pop2(Register Reg) { in addCandidateForPush2Pop2() argument 251 CandidatesForPush2Pop2.insert(Reg); in addCandidateForPush2Pop2()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kFrameLowering.cpp | 160 Register Reg = MO.getReg(); in findDeadCallerSavedReg() local 161 if (!Reg) in findDeadCallerSavedReg() 211 .addReg(Reg) in BuildStackAlignAND() 350 Register Reg; in emitSPUpdate() local 353 Reg = M68k::D0; in emitSPUpdate() 357 if (Reg) { in emitSPUpdate() 466 Register Reg = I.getReg(); in emitPrologueCalleeSavedFrameMoves() local 843 Register Reg = Info.getReg(); in spillCalleeSavedRegisters() local 857 Register Reg = Info.getReg(); in spillCalleeSavedRegisters() local 860 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters() [all …]
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H A D | M68kInstrInfo.cpp | 317 unsigned R = Reg; in AddSExt() 327 BuildMI(MBB, I, DL, get(M68k::EXT32), Reg).addReg(Reg); in AddSExt() 346 BuildMI(MBB, I, DL, get(And), Reg).addReg(Reg).addImm(Mask); in AddZExt() 510 int Reg = 0, Offset = 0, Base = 0; in ExpandMOVEM() local 517 Reg = MIB->getOperand(0).getReg(); in ExpandMOVEM() 523 Reg = MIB->getOperand(2).getReg(); in ExpandMOVEM() 528 if (!XR32->contains(Reg)) { in ExpandMOVEM() 529 Reg = RI.getMatchingMegaReg(Reg, XR32); in ExpandMOVEM() 546 .addReg(Reg, RegState::Implicit) in ExpandMOVEM() 565 Register Reg = MIB->getOperand(0).getReg(); in Expand2AddrUndef() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFrameLowering.cpp | 38 if (!MRI.isPhysRegUsed(Reg) && LiveUnits.available(Reg) && in findUnusedRegister() 40 return Reg; in findUnusedRegister() 63 if (LiveUnits.available(Reg) && !MRI.isReserved(Reg)) in findScratchNonCalleeSaveRegister() 64 return Reg; in findScratchNonCalleeSaveRegister() 418 if (LiveUnits.available(Reg) && !MRI.isReserved(Reg) && in emitEntryFunctionFlatScratchInit() 579 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg) && in getEntryFunctionReservedScratchRsrcReg() 583 return Reg; in getEntryFunctionReservedScratchRsrcReg() 674 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg) && in emitEntryFunctionPrologue() 973 Register Reg = in emitCSRSpillStores() local 975 if (!Reg) in emitCSRSpillStores() [all …]
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H A D | AMDGPUArgumentUsageInfo.h | 30 MCRegister Reg; member 43 : Reg(Val), Mask(Mask), IsStack(IsStack), IsSet(IsSet) {} in Reg() function 45 static ArgDescriptor createRegister(Register Reg, unsigned Mask = ~0u) { 46 return ArgDescriptor(Reg, Mask, false, true); 54 return ArgDescriptor(Arg.Reg, Mask, Arg.IsStack, Arg.IsSet); in createArg() 71 return Reg; in getRegister()
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H A D | R600OptimizeVectorRegisters.cpp | 40 static bool isImplicitlyDef(MachineRegisterInfo &MRI, Register Reg) { in isImplicitlyDef() argument 41 if (Reg.isPhysical()) in isImplicitlyDef() 43 const MachineInstr *MI = MRI.getUniqueVRegDef(Reg); in isImplicitlyDef() 85 bool areAllUsesSwizzeable(Register Reg) const; 184 Register Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector() local 214 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec); in RebuildVector() 263 bool R600VectorRegMerger::areAllUsesSwizzeable(Register Reg) const { in areAllUsesSwizzeable() 332 Register Reg = MI.getOperand(1).getReg(); in runOnMachineFunction() local 334 It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end(); in runOnMachineFunction() 345 Register Reg = MI.getOperand(0).getReg(); in runOnMachineFunction() local [all …]
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ScheduleDAG.h | 87 unsigned Reg; member 104 SDep(SUnit *S, Kind kind, unsigned Reg) in SDep() argument 111 assert(Reg != 0 && in SDep() 113 Contents.Reg = Reg; in SDep() 117 Contents.Reg = Reg; in SDep() 221 return Contents.Reg; in getReg() 228 void setReg(unsigned Reg) { in setReg() argument 231 assert((getKind() != Anti || Reg != 0) && in setReg() 233 assert((getKind() != Output || Reg != 0) && in setReg() 235 Contents.Reg = Reg; in setReg() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineLoopInfo.cpp | 213 Register Reg = MO.getReg(); in isLoopInvariant() local 214 if (Reg == 0) continue; in isLoopInvariant() 218 if (Reg.isPhysical()) { in isLoopInvariant() 225 if (!MRI->isConstantPhysReg(Reg) && in isLoopInvariant() 226 !(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF())) && in isLoopInvariant() 234 } else if (getHeader()->isLiveIn(Reg)) { in isLoopInvariant() 244 assert(MRI->getVRegDef(Reg) && in isLoopInvariant() 249 if (contains(MRI->getVRegDef(Reg))) in isLoopInvariant()
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H A D | RegAllocGreedy.cpp | 465 for (MCRegister Reg : in canReassign() local 467 if (Reg == FromReg) in canReassign() 1257 if (OtherReg == Reg) { in trySplitAroundHintReg() 1259 if (OtherReg == Reg) in trySplitAroundHintReg() 2150 MCRegister Reg = in selectOrSplit() local 2167 return Reg; in selectOrSplit() 2250 if (OtherReg == Reg) { in collectHintInfo() 2252 if (OtherReg == Reg) in collectHintInfo() 2296 Visited.insert(Reg); in tryHintRecoloring() 2306 if (Reg.isPhysical()) in tryHintRecoloring() [all …]
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H A D | BranchFolding.cpp | 867 Reg); in mergeCommonTails() 1798 if (Reg.isPhysical()) { in addRegAndItsAliases() 1802 Set.insert(Reg); in addRegAndItsAliases() 1827 if (!Reg) in findHoistingInsertPosAndDeps() 1864 if (!Reg) in findHoistingInsertPosAndDeps() 1866 if (Uses.count(Reg)) { in findHoistingInsertPosAndDeps() 1892 if (!Reg) in findHoistingInsertPosAndDeps() 1897 if (Uses.erase(Reg)) { in findHoistingInsertPosAndDeps() 1965 if (!Reg) in HoistCommonCodeInSuccs() 2015 if (!Reg) in HoistCommonCodeInSuccs() [all …]
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H A D | AllocationOrder.h | 114 bool isHint(Register Reg) const { in isHint() argument 115 assert(!Reg.isPhysical() || in isHint() 116 Reg.id() < in isHint() 118 return Reg.isPhysical() && is_contained(Hints, Reg.id()); in isHint()
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H A D | MachineOperand.cpp | 62 if (getReg() == Reg) in setReg() 74 SmallContents.RegNo = Reg; in setReg() 80 SmallContents.RegNo = Reg; in setReg() 85 assert(Reg.isVirtual()); in substVirtReg() 88 setReg(Reg); in substVirtReg() 96 Reg = TRI.getSubReg(Reg, getSubReg()); in substPhysReg() 103 setReg(Reg); in substPhysReg() 827 if (Reg.isVirtual()) { in print() 842 if (Reg.isVirtual()) { in print() 964 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) { in print() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVMachineFunctionInfo.cpp | 39 void RISCVMachineFunctionInfo::addSExt32Register(Register Reg) { in addSExt32Register() argument 40 SExt32Registers.push_back(Reg); in addSExt32Register() 43 bool RISCVMachineFunctionInfo::isSExt32Register(Register Reg) const { in isSExt32Register() 44 return is_contained(SExt32Registers, Reg); in isSExt32Register()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcMachineFunctionInfo.h | 47 void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; } in setGlobalBaseReg() argument 53 void setSRetReturnReg(Register Reg) { SRetReturnReg = Reg; } in setSRetReturnReg() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SpeculationHardening.cpp | 434 unsigned Reg) { in makeGPRSpeculationSafe() argument 435 assert(AArch64::GPR32allRegClass.contains(Reg) || in makeGPRSpeculationSafe() 436 AArch64::GPR64allRegClass.contains(Reg)); in makeGPRSpeculationSafe() 443 if (Reg == AArch64::SP || Reg == AArch64::WSP) in makeGPRSpeculationSafe() 447 if (RegsAlreadyMasked[Reg]) in makeGPRSpeculationSafe() 455 .addDef(Reg) in makeGPRSpeculationSafe() 456 .addUse(Reg); in makeGPRSpeculationSafe() 457 RegsAlreadyMasked.set(Reg); in makeGPRSpeculationSafe() 527 Register Reg = Use.getReg(); in slhLoads() local 538 if (!(AArch64::GPR32allRegClass.contains(Reg) || in slhLoads() [all …]
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H A D | AArch64AdvSIMDScalarPass.cpp | 104 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument 108 if (Register::isVirtualRegister(Reg)) in isGPR64() 109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64() 110 return AArch64::GPR64RegClass.contains(Reg); in isGPR64() 113 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument 115 if (Register::isVirtualRegister(Reg)) in isFPR64() 116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64() 118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64() 121 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64() 122 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
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/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
H A D | VirtualCallChecker.cpp | 114 const MemRegion *Reg = MC->getCXXThisVal().getAsRegion(); in checkPreCall() local 115 const ObjectState *ObState = State->get<CtorDtorMap>(Reg); in checkPreCall() 179 const MemRegion *Reg = ThiSVal.getAsRegion(); in registerCtorDtorCallInState() local 181 State = State->set<CtorDtorMap>(Reg, ObjectState::CtorCalled); in registerCtorDtorCallInState() 183 State = State->remove<CtorDtorMap>(Reg); in registerCtorDtorCallInState() 193 const MemRegion *Reg = ThiSVal.getAsRegion(); in registerCtorDtorCallInState() local 195 State = State->set<CtorDtorMap>(Reg, ObjectState::DtorCalled); in registerCtorDtorCallInState() 197 State = State->remove<CtorDtorMap>(Reg); in registerCtorDtorCallInState()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGFast.cpp | 401 SDep FromDep(SU, SDep::Data, Reg); in InsertCopiesAndMoveSuccs() 417 static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, in getPhysicalRegisterVT() argument 429 if (Reg == ImpDef) in getPhysicalRegisterVT() 439 static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg, in CheckForLiveRegDef() argument 505 if (Register::isPhysicalRegister(Reg)) in DelayForLiveRegsBottomUp() 516 if (Reg.isPhysical()) { in DelayForLiveRegsBottomUp() 525 for (MCPhysReg Reg : MCID.implicit_defs()) in DelayForLiveRegsBottomUp() local 580 unsigned Reg = LRegs[0]; in ListScheduleBottomUp() local 581 SUnit *LRDef = LiveRegDefs[Reg]; in ListScheduleBottomUp() 584 TRI->getMinimalPhysRegClass(Reg, VT); in ListScheduleBottomUp() [all …]
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | PseudoLoweringEmitter.cpp | 27 enum MapKind { Operand, Imm, Reg }; enumerator 32 Record *Reg; // Physical register. member 82 OperandMap[BaseIdx + i].Kind = OpData::Reg; in addDagOperandMapping() 83 OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); in addDagOperandMapping() 266 case OpData::Reg: { in emitLoweringEmitter() 267 Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg; in emitLoweringEmitter() local 270 if (Reg->getName() == "zero_reg") in emitLoweringEmitter() 273 o << Reg->getValueAsString("Namespace") << "::" in emitLoweringEmitter() 274 << Reg->getName(); in emitLoweringEmitter()
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