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Searched refs:R11 (Results 1 – 25 of 94) sorted by relevance

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/openbsd/gnu/llvm/compiler-rt/lib/builtins/hexagon/
H A Dfastmath_dlib_asm.S77 #define minmin R11:10 // exactly 0x800000000000000000LL
78 #define minminh R11
212 #define minmin R11:10 // exactly 0x800000000000000000LL
213 #define minminh R11
331 #define lmantc R11:10
332 #define mantch R11
H A Dfastmath2_dlib_asm.S70 #define minmin R11:10 // exactly 0x000000000000008001LL
171 #define minmin R11:10 // exactly 0x000000000000008001LL
269 #define lmantc R11:10
271 #define guard R11
/openbsd/gnu/llvm/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td36 def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
50 R11)>;
56 R11, CP, DP, SP, LR)> {
H A DXCoreCallingConv.td30 // The 'nest' parameter, if any, is passed in R11.
31 CCIfNest<CCAssignToReg<[R11]>>,
H A DXCoreInstrInfo.td629 let Uses = [R11], isCall=1 in
647 let Defs = [R11], isReMaterializable = 1 in
651 let Defs = [R11] in
676 let Defs = [R11], isReMaterializable = 1 in {
699 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
980 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
994 let Uses=[R11] in {
1040 let Defs = [R11] in {
1043 [(set R11, (int_xcore_getid))]>;
1047 [(set R11, (int_xcore_geted))]>;
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td36 def RR2 : LanaiReg<11, "rr2", [R11]>, DwarfRegAlias<R11>;
50 R10, RR1, R11, RR2, // programmer controlled registers
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMCallingConv.td122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
270 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
275 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
289 R11, R10, R9, R8,
294 LR, R11)>;
304 // When enforcing an AAPCS compliant frame chain, R11 is used as the frame
308 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R11,
317 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
344 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
363 // FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and
[all …]
H A DARMBaseRegisterInfo.h54 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
66 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
94 case R11: case LR: in isSplitFPArea2Register()
H A DARMSLSHardening.cpp145 {"__llvm_slsblr_thunk_arm_r11", ARM::R11, false},
159 {"__llvm_slsblr_thunk_thumb_r11", ARM::R11, true},
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86IndirectThunks.cpp102 BuildMI(&MF.front(), DebugLoc(), TII->get(X86::JMP64r)).addReg(X86::R11); in populateThunk()
103 MF.front().addLiveIn(X86::R11); in populateThunk()
168 ThunkReg = X86::R11; in populateThunk()
H A DX86KCFI.cpp76 if (!TII->unfoldMemoryOperand(MF, *OrigCall, X86::R11, /*UnfoldLoad=*/true, in emitCheck()
113 Check->addOperand(MachineOperand::CreateReg(X86::R11, false)); in emitCheck()
H A DX86FixupGadgets.cpp395 case X86::R11: in getWidestRegForReg()
396 return X86::R11; in getWidestRegForReg()
437 case X86::R11: in getEquivalentRegForReg()
487 case X86::R11: in getEquivalentRegForReg()
520 case X86::R11: in getEquivalentRegForReg()
533 case X86::R11: in getEquivalentRegForReg()
H A DX86ReturnProtectorLowering.cpp95 TempRegs.push_back(X86::R11); in fillTempRegisters()
/openbsd/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td47 def R11 : AVRReg<11, "r11">, DwarfRegNum<[11]>;
90 def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>;
105 def R12R11 : AVRReg<11, "r12:r11", [R11, R12]>, DwarfRegNum<[11]>;
121 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
126 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/openbsd/gnu/llvm/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.td66 def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
H A DMSP430RegisterInfo.cpp53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
/openbsd/gnu/llvm/lldb/source/Plugins/Process/Windows/Common/x64/
H A DRegisterContextWindows_x64.cpp363 GPR_CASE(64, lldb_r11_x86_64, m_context.R11); in ReadRegister()
383 GPR_CASE(32, lldb_r11d_x86_64, static_cast<uint32_t>(m_context.R11)); in ReadRegister()
399 GPR_CASE(16, lldb_r11w_x86_64, static_cast<uint16_t>(m_context.R11)); in ReadRegister()
419 GPR_CASE(8, lldb_r11l_x86_64, static_cast<uint8_t>(m_context.R11)); in ReadRegister()
531 m_context.R11 = reg_value.GetAsUInt64(); in WriteRegister()
/openbsd/gnu/usr.bin/binutils/gdb/
H A Dvax-nat.c57 R6, R7, R8, R9, R10, R11,
/openbsd/gnu/llvm/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h69 case Lanai::R11: in getLanaiRegisterNumbering()
/openbsd/gnu/usr.bin/binutils/gdb/gdbserver/
H A Dlinux-x86-64-low.c62 R8 * 8, R9 * 8, R10 * 8, R11 * 8,
/openbsd/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td49 R11, // Stack Ptr
/openbsd/gnu/llvm/lldb/source/Plugins/Process/Windows/Common/arm/
H A DRegisterContextWindows_arm.cpp148 reg_value.SetUInt32(m_context.R11); in ReadRegister()
313 m_context.R11 = reg_value.GetAsUInt32(); in WriteRegister()
/openbsd/gnu/llvm/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCTargetDesc.cpp44 InitBPFMCRegisterInfo(X, BPF::R11 /* RAReg doesn't exist */); in createBPFMCRegisterInfo()
/openbsd/gnu/llvm/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp280 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in getMaskedTypeForICmpPair()
281 A = R11; in getMaskedTypeForICmpPair()
285 D = R11; in getMaskedTypeForICmpPair()
296 R11 = R1; in getMaskedTypeForICmpPair()
300 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in getMaskedTypeForICmpPair()
301 A = R11; in getMaskedTypeForICmpPair()
307 D = R11; in getMaskedTypeForICmpPair()
320 R11 = R2; in getMaskedTypeForICmpPair()
324 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in getMaskedTypeForICmpPair()
325 A = R11; in getMaskedTypeForICmpPair()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp267 {codeview::RegisterId::R11, X86::R11}, in initLLVMToSEHAndCVRegMapping()
795 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: in getX86SubSuperRegisterOrZero()
832 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: in getX86SubSuperRegisterOrZero()
868 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: in getX86SubSuperRegisterOrZero()
904 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: in getX86SubSuperRegisterOrZero()
905 return X86::R11; in getX86SubSuperRegisterOrZero()

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