1//===-- XCoreRegisterInfo.td - XCore Register defs ---------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10//  Declarations that describe the XCore register file
11//===----------------------------------------------------------------------===//
12
13class XCoreReg<string n> : Register<n> {
14  field bits<4> Num;
15  let Namespace = "XCore";
16}
17
18// Registers are identified with 4-bit ID numbers.
19// Ri - 32-bit integer registers
20class Ri<bits<4> num, string n> : XCoreReg<n> {
21  let Num = num;
22}
23
24// CPU registers
25def R0  : Ri< 0, "r0">, DwarfRegNum<[0]>;
26def R1  : Ri< 1, "r1">, DwarfRegNum<[1]>;
27def R2  : Ri< 2, "r2">, DwarfRegNum<[2]>;
28def R3  : Ri< 3, "r3">, DwarfRegNum<[3]>;
29def R4  : Ri< 4, "r4">, DwarfRegNum<[4]>;
30def R5  : Ri< 5, "r5">, DwarfRegNum<[5]>;
31def R6  : Ri< 6, "r6">, DwarfRegNum<[6]>;
32def R7  : Ri< 7, "r7">, DwarfRegNum<[7]>;
33def R8  : Ri< 8, "r8">, DwarfRegNum<[8]>;
34def R9  : Ri< 9, "r9">, DwarfRegNum<[9]>;
35def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
36def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
37def CP : Ri<12, "cp">, DwarfRegNum<[12]>;
38def DP : Ri<13, "dp">, DwarfRegNum<[13]>;
39def SP : Ri<14, "sp">, DwarfRegNum<[14]>;
40def LR : Ri<15, "lr">, DwarfRegNum<[15]>;
41
42// Register classes.
43//
44def GRRegs : RegisterClass<"XCore", [i32], 32,
45  // Return values and arguments
46  (add R0, R1, R2, R3,
47  // Callee save
48  R4, R5, R6, R7, R8, R9, R10,
49  // Not preserved across procedure calls
50  R11)>;
51
52// Reserved
53def RRegs : RegisterClass<"XCore", [i32], 32,
54  (add R0, R1, R2, R3,
55   R4, R5, R6, R7, R8, R9, R10,
56   R11, CP, DP, SP, LR)> {
57  let isAllocatable = 0;
58}
59