1 /* @(#)scsicdb.h 2.20 06/09/13 Copyright 1986 J. Schilling */ 2 /* 3 * Definitions for the SCSI Command Descriptor Block 4 * 5 * Copyright (c) 1986 J. Schilling 6 */ 7 /* 8 * The contents of this file are subject to the terms of the 9 * Common Development and Distribution License, Version 1.0 only 10 * (the "License"). You may not use this file except in compliance 11 * with the License. 12 * 13 * See the file CDDL.Schily.txt in this distribution for details. 14 * A copy of the CDDL is also available via the Internet at 15 * http://www.opensource.org/licenses/cddl1.txt 16 * 17 * The following exceptions apply: 18 * CDDL �3.6 needs to be replaced by: "You may create a Larger Work by 19 * combining Covered Software with other code if all other code is governed by 20 * the terms of a license that is OSI approved (see www.opensource.org) and 21 * you may distribute the Larger Work as a single product. In such a case, 22 * You must make sure the requirements of this License are fulfilled for 23 * the Covered Software." 24 * 25 * When distributing Covered Code, include this CDDL HEADER in each 26 * file and include the License file CDDL.Schily.txt from this distribution. 27 */ 28 29 #ifndef _SCG_SCSICDB_H 30 #define _SCG_SCSICDB_H 31 32 #ifndef _SCHILY_UTYPES_H 33 #include <schily/utypes.h> 34 #endif 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 /* 40 * SCSI Operation codes. 41 */ 42 #define SC_TEST_UNIT_READY 0x00 43 #define SC_REZERO_UNIT 0x01 44 #define SC_REQUEST_SENSE 0x03 45 #define SC_FORMAT 0x04 46 #define SC_FORMAT_TRACK 0x06 47 #define SC_REASSIGN_BLOCK 0x07 /* CCS only */ 48 #define SC_SEEK 0x0b 49 #define SC_TRANSLATE 0x0f /* ACB4000 only */ 50 #define SC_INQUIRY 0x12 /* CCS only */ 51 #define SC_MODE_SELECT 0x15 52 #define SC_RESERVE 0x16 53 #define SC_RELEASE 0x17 54 #define SC_MODE_SENSE 0x1a 55 #define SC_START 0x1b 56 #define SC_READ_DEFECT_LIST 0x37 /* CCS only, group 1 */ 57 #define SC_READ_BUFFER 0x3c /* CCS only, group 1 */ 58 /* 59 * Note, these two commands use identical command blocks for all 60 * controllers except the Adaptec ACB 4000 which sets bit 1 of byte 1. 61 */ 62 #define SC_READ 0x08 63 #define SC_WRITE 0x0a 64 #define SC_EREAD 0x28 /* 10 byte read */ 65 #define SC_EWRITE 0x2a /* 10 byte write */ 66 #define SC_WRITE_VERIFY 0x2e /* 10 byte write+verify */ 67 #define SC_WRITE_FILE_MARK 0x10 68 #define SC_UNKNOWN 0xff /* cmd list terminator */ 69 70 71 /* 72 * Standard SCSI control blocks. 73 * These go in or out over the SCSI bus. 74 */ 75 76 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 77 78 struct scsi_g0cdb { /* scsi group 0 command description block */ 79 Uchar cmd; /* command code */ 80 Ucbit high_addr : 5; /* high part of block address */ 81 Ucbit lun : 3; /* logical unit number */ 82 Uchar mid_addr; /* middle part of block address */ 83 Uchar low_addr; /* low part of block address */ 84 Uchar count; /* transfer length */ 85 Ucbit link : 1; /* link (another command follows) */ 86 Ucbit fr : 1; /* flag request (interrupt at completion) */ 87 Ucbit naca : 1; /* Normal ACA (Auto Contingent Allegiance) */ 88 Ucbit rsvd : 3; /* reserved */ 89 Ucbit vu_56 : 1; /* vendor unique (byte 5 bit 6) */ 90 Ucbit vu_57 : 1; /* vendor unique (byte 5 bit 7) */ 91 }; 92 93 #else /* Motorola byteorder */ 94 95 struct scsi_g0cdb { /* scsi group 0 command description block */ 96 Uchar cmd; /* command code */ 97 Ucbit lun : 3; /* logical unit number */ 98 Ucbit high_addr : 5; /* high part of block address */ 99 Uchar mid_addr; /* middle part of block address */ 100 Uchar low_addr; /* low part of block address */ 101 Uchar count; /* transfer length */ 102 Ucbit vu_57 : 1; /* vendor unique (byte 5 bit 7) */ 103 Ucbit vu_56 : 1; /* vendor unique (byte 5 bit 6) */ 104 Ucbit rsvd : 3; /* reserved */ 105 Ucbit naca : 1; /* Normal ACA (Auto Contingent Allegiance) */ 106 Ucbit fr : 1; /* flag request (interrupt at completion) */ 107 Ucbit link : 1; /* link (another command follows) */ 108 }; 109 #endif 110 111 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 112 113 struct scsi_g1cdb { /* scsi group 1 command description block */ 114 Uchar cmd; /* command code */ 115 Ucbit reladr : 1; /* address is relative */ 116 Ucbit res : 4; /* reserved bits 1-4 of byte 1 */ 117 Ucbit lun : 3; /* logical unit number */ 118 Uchar addr[4]; /* logical block address */ 119 Uchar res6; /* reserved byte 6 */ 120 Uchar count[2]; /* transfer length */ 121 Ucbit link : 1; /* link (another command follows) */ 122 Ucbit fr : 1; /* flag request (interrupt at completion) */ 123 Ucbit naca : 1; /* Normal ACA (Auto Contingent Allegiance) */ 124 Ucbit rsvd : 3; /* reserved */ 125 Ucbit vu_96 : 1; /* vendor unique (byte 5 bit 6) */ 126 Ucbit vu_97 : 1; /* vendor unique (byte 5 bit 7) */ 127 }; 128 129 #else /* Motorola byteorder */ 130 131 struct scsi_g1cdb { /* scsi group 1 command description block */ 132 Uchar cmd; /* command code */ 133 Ucbit lun : 3; /* logical unit number */ 134 Ucbit res : 4; /* reserved bits 1-4 of byte 1 */ 135 Ucbit reladr : 1; /* address is relative */ 136 Uchar addr[4]; /* logical block address */ 137 Uchar res6; /* reserved byte 6 */ 138 Uchar count[2]; /* transfer length */ 139 Ucbit vu_97 : 1; /* vendor unique (byte 5 bit 7) */ 140 Ucbit vu_96 : 1; /* vendor unique (byte 5 bit 6) */ 141 Ucbit rsvd : 3; /* reserved */ 142 Ucbit naca : 1; /* Normal ACA (Auto Contingent Allegiance) */ 143 Ucbit fr : 1; /* flag request (interrupt at completion) */ 144 Ucbit link : 1; /* link (another command follows) */ 145 }; 146 #endif 147 148 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 149 150 struct scsi_g5cdb { /* scsi group 5 command description block */ 151 Uchar cmd; /* command code */ 152 Ucbit reladr : 1; /* address is relative */ 153 Ucbit res : 4; /* reserved bits 1-4 of byte 1 */ 154 Ucbit lun : 3; /* logical unit number */ 155 Uchar addr[4]; /* logical block address */ 156 Uchar count[4]; /* transfer length */ 157 Uchar res10; /* reserved byte 10 */ 158 Ucbit link : 1; /* link (another command follows) */ 159 Ucbit fr : 1; /* flag request (interrupt at completion) */ 160 Ucbit naca : 1; /* Normal ACA (Auto Contingent Allegiance) */ 161 Ucbit rsvd : 3; /* reserved */ 162 Ucbit vu_B6 : 1; /* vendor unique (byte B bit 6) */ 163 Ucbit vu_B7 : 1; /* vendor unique (byte B bit 7) */ 164 }; 165 166 #else /* Motorola byteorder */ 167 168 struct scsi_g5cdb { /* scsi group 5 command description block */ 169 Uchar cmd; /* command code */ 170 Ucbit lun : 3; /* logical unit number */ 171 Ucbit res : 4; /* reserved bits 1-4 of byte 1 */ 172 Ucbit reladr : 1; /* address is relative */ 173 Uchar addr[4]; /* logical block address */ 174 Uchar count[4]; /* transfer length */ 175 Uchar res10; /* reserved byte 10 */ 176 Ucbit vu_B7 : 1; /* vendor unique (byte B bit 7) */ 177 Ucbit vu_B6 : 1; /* vendor unique (byte B bit 6) */ 178 Ucbit rsvd : 3; /* reserved */ 179 Ucbit naca : 1; /* Normal ACA (Auto Contingent Allegiance) */ 180 Ucbit fr : 1; /* flag request (interrupt at completion) */ 181 Ucbit link : 1; /* link (another command follows) */ 182 }; 183 #endif 184 185 #define g0_cdbaddr(cdb, a) ((cdb)->high_addr = (a) >> 16,\ 186 (cdb)->mid_addr = ((a) >> 8) & 0xFF,\ 187 (cdb)->low_addr = (a) & 0xFF) 188 189 #define g1_cdbaddr(cdb, a) ((cdb)->addr[0] = (a) >> 24,\ 190 (cdb)->addr[1] = ((a) >> 16)& 0xFF,\ 191 (cdb)->addr[2] = ((a) >> 8) & 0xFF,\ 192 (cdb)->addr[3] = (a) & 0xFF) 193 194 #define g5_cdbaddr(cdb, a) g1_cdbaddr(cdb, a) 195 196 197 #define g0_cdblen(cdb, len) ((cdb)->count = (len)) 198 199 #define g1_cdblen(cdb, len) ((cdb)->count[0] = ((len) >> 8) & 0xFF,\ 200 (cdb)->count[1] = (len) & 0xFF) 201 202 #define g5_cdblen(cdb, len) ((cdb)->count[0] = (len) >> 24L,\ 203 (cdb)->count[1] = ((len) >> 16L)& 0xFF,\ 204 (cdb)->count[2] = ((len) >> 8L) & 0xFF,\ 205 (cdb)->count[3] = (len) & 0xFF) 206 207 /*#define XXXXX*/ 208 #ifdef XXXXX 209 #define i_to_long(a, i) (((Uchar *)(a))[0] = ((i) >> 24)& 0xFF,\ 210 ((Uchar *)(a))[1] = ((i) >> 16)& 0xFF,\ 211 ((Uchar *)(a))[2] = ((i) >> 8) & 0xFF,\ 212 ((Uchar *)(a))[3] = (i) & 0xFF) 213 214 #define i_to_3_byte(a, i) (((Uchar *)(a))[0] = ((i) >> 16)& 0xFF,\ 215 ((Uchar *)(a))[1] = ((i) >> 8) & 0xFF,\ 216 ((Uchar *)(a))[2] = (i) & 0xFF) 217 218 #define i_to_4_byte(a, i) (((Uchar *)(a))[0] = ((i) >> 24)& 0xFF,\ 219 ((Uchar *)(a))[1] = ((i) >> 16)& 0xFF,\ 220 ((Uchar *)(a))[2] = ((i) >> 8) & 0xFF,\ 221 ((Uchar *)(a))[3] = (i) & 0xFF) 222 223 #define i_to_short(a, i) (((Uchar *)(a))[0] = ((i) >> 8) & 0xFF,\ 224 ((Uchar *)(a))[1] = (i) & 0xFF) 225 226 #define a_to_u_short(a) ((unsigned short) \ 227 ((((Uchar*) a)[1] & 0xFF) | \ 228 (((Uchar*) a)[0] << 8 & 0xFF00))) 229 230 #define a_to_3_byte(a) ((Ulong) \ 231 ((((Uchar*) a)[2] & 0xFF) | \ 232 (((Uchar*) a)[1] << 8 & 0xFF00) | \ 233 (((Uchar*) a)[0] << 16 & 0xFF0000))) 234 235 #ifdef __STDC__ 236 #define a_to_u_long(a) ((Ulong) \ 237 ((((Uchar*) a)[3] & 0xFF) | \ 238 (((Uchar*) a)[2] << 8 & 0xFF00) | \ 239 (((Uchar*) a)[1] << 16 & 0xFF0000) | \ 240 (((Uchar*) a)[0] << 24 & 0xFF000000UL))) 241 #else 242 #define a_to_u_long(a) ((Ulong) \ 243 ((((Uchar*) a)[3] & 0xFF) | \ 244 (((Uchar*) a)[2] << 8 & 0xFF00) | \ 245 (((Uchar*) a)[1] << 16 & 0xFF0000) | \ 246 (((Uchar*) a)[0] << 24 & 0xFF000000))) 247 #endif 248 #endif /* XXXX */ 249 250 251 #ifdef __cplusplus 252 } 253 #endif 254 255 #endif /* _SCG_SCSICDB_H */ 256