1 /**
2 ******************************************************************************
3 * @file system_stm32f4xx.c
4 * @author MCD Application Team
5 * @version V1.0.1
6 * @date 10-July-2012
7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
8 * This file contains the system clock configuration for STM32F4xx devices,
9 * and is generated by the clock configuration tool
10 * stm32f4xx_Clock_Configuration_V1.0.1.xls
11 *
12 * 1. This file provides two functions and one global variable to be called from
13 * user application:
14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
15 * and Divider factors, AHB/APBx prescalers and Flash settings),
16 * depending on the configuration made in the clock xls tool.
17 * This function is called at startup just after reset and
18 * before branch to main program. This call is made inside
19 * the "startup_stm32f4xx.s" file.
20 *
21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
22 * by the user application to setup the SysTick
23 * timer or configure other parameters.
24 *
25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
26 * be called whenever the core clock is changed
27 * during program execution.
28 *
29 * 2. After each device reset the HSI (16 MHz) is used as system clock source.
30 * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
31 * configure the system clock before to branch to main program.
32 *
33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
34 * function will do nothing and HSI still used as system clock source. User can
35 * add some code to deal with this issue inside the SetSysClock() function.
36 *
37 * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
38 * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
39 * through PLL, and you are using different crystal you have to adapt the HSE
40 * value to your own configuration.
41 *
42 * 5. This file configures the system clock as follows:
43 *=============================================================================
44 *=============================================================================
45 * Supported STM32F4xx device revision | Rev A
46 *-----------------------------------------------------------------------------
47 * System Clock source | PLL (HSE)
48 *-----------------------------------------------------------------------------
49 * SYSCLK(Hz) | 168000000
50 *-----------------------------------------------------------------------------
51 * HCLK(Hz) | 168000000
52 *-----------------------------------------------------------------------------
53 * AHB Prescaler | 1
54 *-----------------------------------------------------------------------------
55 * APB1 Prescaler | 4
56 *-----------------------------------------------------------------------------
57 * APB2 Prescaler | 2
58 *-----------------------------------------------------------------------------
59 * HSE Frequency(Hz) | 8000000
60 *-----------------------------------------------------------------------------
61 * PLL_M | 8
62 *-----------------------------------------------------------------------------
63 * PLL_N | 336
64 *-----------------------------------------------------------------------------
65 * PLL_P | 2
66 *-----------------------------------------------------------------------------
67 * PLL_Q | 7
68 *-----------------------------------------------------------------------------
69 * PLLI2S_N | 352
70 *-----------------------------------------------------------------------------
71 * PLLI2S_R | 2
72 *-----------------------------------------------------------------------------
73 * I2S input clock(Hz) | 176000000
74 * |
75 * To achieve the following I2S config: |
76 * - Master clock output (MCKO): OFF |
77 * - Frame wide : 16bit |
78 * - Error % : 0,0000 |
79 * - Prescaler Odd factor (ODD): 1 |
80 * - Linear prescaler (DIV) : 14 |
81 *-----------------------------------------------------------------------------
82 * VDD(V) | 3,3
83 *-----------------------------------------------------------------------------
84 * Main regulator output voltage | Scale1 mode
85 *-----------------------------------------------------------------------------
86 * Flash Latency(WS) | 5
87 *-----------------------------------------------------------------------------
88 * Prefetch Buffer | OFF
89 *-----------------------------------------------------------------------------
90 * Instruction cache | ON
91 *-----------------------------------------------------------------------------
92 * Data cache | ON
93 *-----------------------------------------------------------------------------
94 * Require 48MHz for USB OTG FS, | Enabled
95 * SDIO and RNG clock |
96 *-----------------------------------------------------------------------------
97 *=============================================================================
98 ******************************************************************************
99 * @attention
100 *
101 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
102 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
103 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
104 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
105 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
106 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
107 *
108 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
109 ******************************************************************************
110 */
111
112 /** @addtogroup CMSIS
113 * @{
114 */
115
116 /** @addtogroup stm32f4xx_system
117 * @{
118 */
119
120 /** @addtogroup STM32F4xx_System_Private_Includes
121 * @{
122 */
123
124 #include "stm32f4xx.h"
125
126 /**
127 * @}
128 */
129
130 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
131 * @{
132 */
133
134 /**
135 * @}
136 */
137
138 /** @addtogroup STM32F4xx_System_Private_Defines
139 * @{
140 */
141
142 /************************* Miscellaneous Configuration ************************/
143 /*!< Uncomment the following line if you need to use external SRAM mounted
144 on STM324xG_EVAL board as data memory */
145 /* #define DATA_IN_ExtSRAM */
146
147 /*!< Uncomment the following line if you need to relocate your vector Table in
148 Internal SRAM. */
149 /* #define VECT_TAB_SRAM */
150 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
151 This value must be a multiple of 0x200. */
152 /******************************************************************************/
153
154 /************************* PLL Parameters *************************************/
155 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
156 #define PLL_M 8
157 #define PLL_N 336
158
159 /* SYSCLK = PLL_VCO / PLL_P */
160 #define PLL_P 2
161
162 /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
163 #define PLL_Q 7
164
165 /* PLLI2S_VCO = (HSE_VALUE Or HSI_VALUE / PLL_M) * PLLI2S_N
166 I2SCLK = PLLI2S_VCO / PLLI2S_R */
167 #define START_I2SCLOCK 0
168 #define PLLI2S_N 352
169 #define PLLI2S_R 2
170
171 /******************************************************************************/
172
173 /**
174 * @}
175 */
176
177 /** @addtogroup STM32F4xx_System_Private_Macros
178 * @{
179 */
180
181 /**
182 * @}
183 */
184
185 /** @addtogroup STM32F4xx_System_Private_Variables
186 * @{
187 */
188
189 uint32_t SystemCoreClock = 168000000;
190
191 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
192
193 /**
194 * @}
195 */
196
197 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
198 * @{
199 */
200
201 static void SetSysClock(void);
202 #ifdef DATA_IN_ExtSRAM
203 static void SystemInit_ExtMemCtl(void);
204 #endif /* DATA_IN_ExtSRAM */
205
206 /**
207 * @}
208 */
209
210 /** @addtogroup STM32F4xx_System_Private_Functions
211 * @{
212 */
213
214 /**
215 * @brief Setup the microcontroller system
216 * Initialize the Embedded Flash Interface, the PLL and update the
217 * SystemFrequency variable.
218 * @param None
219 * @retval None
220 */
SystemInit(void)221 void SystemInit(void)
222 {
223 /* FPU settings ------------------------------------------------------------*/
224 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
225 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
226 #endif
227 /* Reset the RCC clock configuration to the default reset state ------------*/
228 /* Set HSION bit */
229 RCC->CR |= (uint32_t)0x00000001;
230
231 /* Reset CFGR register */
232 RCC->CFGR = 0x00000000;
233
234 /* Reset HSEON, CSSON and PLLON bits */
235 RCC->CR &= (uint32_t)0xFEF6FFFF;
236
237 /* Reset PLLCFGR register */
238 RCC->PLLCFGR = 0x24003010;
239
240 /* Reset HSEBYP bit */
241 RCC->CR &= (uint32_t)0xFFFBFFFF;
242
243 /* Disable all interrupts */
244 RCC->CIR = 0x00000000;
245
246 #ifdef DATA_IN_ExtSRAM
247 SystemInit_ExtMemCtl();
248 #endif /* DATA_IN_ExtSRAM */
249
250 /* Configure the System clock source, PLL Multiplier and Divider factors,
251 AHB/APBx prescalers and Flash settings ----------------------------------*/
252 SetSysClock();
253
254 /* Configure the Vector Table location add offset address ------------------*/
255 #ifdef VECT_TAB_SRAM
256 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
257 #else
258 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
259 #endif
260 }
261
262 /**
263 * @brief Update SystemCoreClock variable according to Clock Register Values.
264 * The SystemCoreClock variable contains the core clock (HCLK), it can
265 * be used by the user application to setup the SysTick timer or configure
266 * other parameters.
267 *
268 * @note Each time the core clock (HCLK) changes, this function must be called
269 * to update SystemCoreClock variable value. Otherwise, any configuration
270 * based on this variable will be incorrect.
271 *
272 * @note - The system frequency computed by this function is not the real
273 * frequency in the chip. It is calculated based on the predefined
274 * constant and the selected clock source:
275 *
276 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
277 *
278 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
279 *
280 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
281 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
282 *
283 * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
284 * 16 MHz) but the real value may vary depending on the variations
285 * in voltage and temperature.
286 *
287 * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
288 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
289 * frequency of the crystal used. Otherwise, this function may
290 * have wrong result.
291 *
292 * - The result of this function could be not correct when using fractional
293 * value for HSE crystal.
294 *
295 * @param None
296 * @retval None
297 */
SystemCoreClockUpdate(void)298 void SystemCoreClockUpdate(void)
299 {
300 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
301
302 /* Get SYSCLK source -------------------------------------------------------*/
303 tmp = RCC->CFGR & RCC_CFGR_SWS;
304
305 switch (tmp)
306 {
307 case 0x00: /* HSI used as system clock source */
308 SystemCoreClock = HSI_VALUE;
309 break;
310 case 0x04: /* HSE used as system clock source */
311 SystemCoreClock = HSE_VALUE;
312 break;
313 case 0x08: /* PLL used as system clock source */
314
315 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
316 SYSCLK = PLL_VCO / PLL_P
317 */
318 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
319 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
320
321 if (pllsource != 0)
322 {
323 /* HSE used as PLL clock source */
324 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
325 }
326 else
327 {
328 /* HSI used as PLL clock source */
329 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
330 }
331
332 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
333 SystemCoreClock = pllvco/pllp;
334 break;
335 default:
336 SystemCoreClock = HSI_VALUE;
337 break;
338 }
339 /* Compute HCLK frequency --------------------------------------------------*/
340 /* Get HCLK prescaler */
341 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
342 /* HCLK frequency */
343 SystemCoreClock >>= tmp;
344 }
345
346 /**
347 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
348 * AHB/APBx prescalers and Flash settings
349 * @Note This function should be called only once the RCC clock configuration
350 * is reset to the default reset state (done in SystemInit() function).
351 * @param None
352 * @retval None
353 */
SetSysClock(void)354 static void SetSysClock(void)
355 {
356 /******************************************************************************/
357 /* PLL (clocked by HSE) used as System clock source */
358 /******************************************************************************/
359 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
360
361 /* Enable HSE */
362 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
363
364 /* Wait till HSE is ready and if Time out is reached exit */
365 do
366 {
367 HSEStatus = RCC->CR & RCC_CR_HSERDY;
368 StartUpCounter++;
369 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
370
371 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
372 {
373 HSEStatus = (uint32_t)0x01;
374 }
375 else
376 {
377 HSEStatus = (uint32_t)0x00;
378 }
379
380 if (HSEStatus == (uint32_t)0x01)
381 {
382 /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
383 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
384 PWR->CR |= PWR_CR_VOS;
385
386 /* HCLK = SYSCLK / 1*/
387 RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
388
389 /* PCLK2 = HCLK / 2*/
390 RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
391
392 /* PCLK1 = HCLK / 4*/
393 RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
394
395 /* Configure the main PLL */
396 RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
397 (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
398
399 /* Enable the main PLL */
400 RCC->CR |= RCC_CR_PLLON;
401
402 /* Wait till the main PLL is ready */
403 while((RCC->CR & RCC_CR_PLLRDY) == 0)
404 {
405 }
406
407 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
408 FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
409
410 /* Select the main PLL as system clock source */
411 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
412 RCC->CFGR |= RCC_CFGR_SW_PLL;
413
414 /* Wait till the main PLL is used as system clock source */
415 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL)
416 {
417 asm("nop");
418 }
419 }
420 else
421 { /* If HSE fails to start-up, the application will have wrong clock
422 configuration. User can add here some code to deal with this error */
423 }
424
425
426 /******************************************************************************/
427 /* I2S clock configuration */
428 /******************************************************************************/
429
430 #if START_I2SCLOCK
431 /* PLLI2S clock used as I2S clock source */
432 RCC->CFGR &= ~RCC_CFGR_I2SSRC;
433
434 /* Configure PLLI2S */
435 RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);
436
437 /* Enable PLLI2S */
438 RCC->CR |= ((uint32_t)RCC_CR_PLLI2SON);
439
440 /* Wait till PLLI2S is ready */
441 while((RCC->CR & RCC_CR_PLLI2SRDY) == 0)
442 {
443 }
444 #endif
445 }
446
447 /**
448 * @brief Setup the external memory controller. Called in startup_stm32f4xx.s
449 * before jump to __main
450 * @param None
451 * @retval None
452 */
453 #ifdef DATA_IN_ExtSRAM
454 /**
455 * @brief Setup the external memory controller.
456 * Called in startup_stm32f4xx.s before jump to main.
457 * This function configures the external SRAM mounted on STM324xG_EVAL board
458 * This SRAM will be used as program data memory (including heap and stack).
459 * @param None
460 * @retval None
461 */
SystemInit_ExtMemCtl(void)462 void SystemInit_ExtMemCtl(void)
463 {
464 /*-- GPIOs Configuration -----------------------------------------------------*/
465 /*
466 +-------------------+--------------------+------------------+------------------+
467 + SRAM pins assignment +
468 +-------------------+--------------------+------------------+------------------+
469 | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
470 | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
471 | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
472 | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
473 | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
474 | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
475 | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
476 | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+
477 | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 |
478 | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 |
479 | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+
480 | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |
481 | | PE15 <-> FSMC_D12 |
482 +-------------------+--------------------+
483 */
484 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
485 RCC->AHB1ENR = 0x00000078;
486
487 /* Connect PDx pins to FSMC Alternate function */
488 GPIOD->AFR[0] = 0x00cc00cc;
489 GPIOD->AFR[1] = 0xcc0ccccc;
490 /* Configure PDx pins in Alternate function mode */
491 GPIOD->MODER = 0xaaaa0a0a;
492 /* Configure PDx pins speed to 100 MHz */
493 GPIOD->OSPEEDR = 0xffff0f0f;
494 /* Configure PDx pins Output type to push-pull */
495 GPIOD->OTYPER = 0x00000000;
496 /* No pull-up, pull-down for PDx pins */
497 GPIOD->PUPDR = 0x00000000;
498
499 /* Connect PEx pins to FSMC Alternate function */
500 GPIOE->AFR[0] = 0xc00cc0cc;
501 GPIOE->AFR[1] = 0xcccccccc;
502 /* Configure PEx pins in Alternate function mode */
503 GPIOE->MODER = 0xaaaa828a;
504 /* Configure PEx pins speed to 100 MHz */
505 GPIOE->OSPEEDR = 0xffffc3cf;
506 /* Configure PEx pins Output type to push-pull */
507 GPIOE->OTYPER = 0x00000000;
508 /* No pull-up, pull-down for PEx pins */
509 GPIOE->PUPDR = 0x00000000;
510
511 /* Connect PFx pins to FSMC Alternate function */
512 GPIOF->AFR[0] = 0x00cccccc;
513 GPIOF->AFR[1] = 0xcccc0000;
514 /* Configure PFx pins in Alternate function mode */
515 GPIOF->MODER = 0xaa000aaa;
516 /* Configure PFx pins speed to 100 MHz */
517 GPIOF->OSPEEDR = 0xff000fff;
518 /* Configure PFx pins Output type to push-pull */
519 GPIOF->OTYPER = 0x00000000;
520 /* No pull-up, pull-down for PFx pins */
521 GPIOF->PUPDR = 0x00000000;
522
523 /* Connect PGx pins to FSMC Alternate function */
524 GPIOG->AFR[0] = 0x00cccccc;
525 GPIOG->AFR[1] = 0x000000c0;
526 /* Configure PGx pins in Alternate function mode */
527 GPIOG->MODER = 0x00080aaa;
528 /* Configure PGx pins speed to 100 MHz */
529 GPIOG->OSPEEDR = 0x000c0fff;
530 /* Configure PGx pins Output type to push-pull */
531 GPIOG->OTYPER = 0x00000000;
532 /* No pull-up, pull-down for PGx pins */
533 GPIOG->PUPDR = 0x00000000;
534
535 /*-- FSMC Configuration ------------------------------------------------------*/
536 /* Enable the FSMC interface clock */
537 RCC->AHB3ENR = 0x00000001;
538
539 /* Configure and enable Bank1_SRAM2 */
540 FSMC_Bank1->BTCR[2] = 0x00001015;
541 FSMC_Bank1->BTCR[3] = 0x00010603;
542 FSMC_Bank1E->BWTR[2] = 0x0fffffff;
543 /*
544 Bank1_SRAM2 is configured as follow:
545
546 p.FSMC_AddressSetupTime = 3;
547 p.FSMC_AddressHoldTime = 0;
548 p.FSMC_DataSetupTime = 6;
549 p.FSMC_BusTurnAroundDuration = 1;
550 p.FSMC_CLKDivision = 0;
551 p.FSMC_DataLatency = 0;
552 p.FSMC_AccessMode = FSMC_AccessMode_A;
553
554 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
555 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
556 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
557 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
558 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
559 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
560 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
561 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
562 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
563 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
564 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
565 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
566 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
567 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
568 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
569 */
570 }
571 #endif /* DATA_IN_ExtSRAM */
572
573
574 /**
575 * @}
576 */
577
578 /**
579 * @}
580 */
581
582 /**
583 * @}
584 */
585 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
586