1 // 2 // ARM7 processor emulator 3 // version 1.6 / 2008-02-16 4 // (c) Radoslaw Balcewicz 5 // 6 7 #ifndef _ARM7_h_ 8 #define _ARM7_h_ 9 10 #include "cpuintrf.h" 11 #include "aica.h" 12 13 //-------------------------------------------------------------------------- 14 // definitions and macros 15 16 /** If defined, will turn on specific behavior emulation, as well as some 17 optimizations that are valid only for Dreamcast AICA. */ 18 #define ARM7_DREAMCAST 19 20 /** Define to enable Thumb support for ARM7. */ 21 //#define ARM7_THUMB 22 23 // sanity tests 24 #ifdef ARM7_DREAMCAST 25 #ifdef ARM7_THUMB 26 #warning "Dreamcast ARM7 is a -DI type, it doesn't support Thumb mode." 27 #endif 28 #else 29 // #warning "Instructions cycle counts might not be correct." 30 #endif 31 32 //-------------------------------------------------------------------------- 33 34 //-------------------------------------------------------------------------- 35 // CPU definitions 36 37 /** Status flags in CPSR register. */ 38 #define ARM7_CPSR_N (1 << 31) 39 #define ARM7_CPSR_Z (1 << 30) 40 #define ARM7_CPSR_C (1 << 29) 41 #define ARM7_CPSR_V (1 << 28) 42 #define ARM7_CPSR_I (1 << 7) 43 #define ARM7_CPSR_F (1 << 6) 44 #define ARM7_CPSR_T (1 << 5) 45 /** CPSR bit mask for current operating mode. */ 46 #define ARM7_CPSR_M(x) ((x) & 0x1f) 47 #define ARM7_CPSR_MX(sr,x) (((sr) & ~0x1f) | ((x) & 0x1f)) 48 /** Bit combinations for each operating mode. */ 49 #define ARM7_CPSR_M_usr 0x10 50 #define ARM7_CPSR_M_fiq 0x11 51 #define ARM7_CPSR_M_irq 0x12 52 #define ARM7_CPSR_M_svc 0x13 53 #define ARM7_CPSR_M_abt 0x17 54 #define ARM7_CPSR_M_und 0x11 55 #define ARM7_CPSR_M_sys 0x1f 56 57 /** Control flags for ARM7 core. */ 58 #define ARM7_FL_FIQ (1 << 0) 59 #define ARM7_FL_IRQ (1 << 1) 60 61 /** Operating modes. */ 62 #define ARM7_MODE_usr 0 63 #define ARM7_MODE_fiq 1 64 #define ARM7_MODE_irq 2 65 #define ARM7_MODE_svc 3 66 #define ARM7_MODE_abt 4 67 #define ARM7_MODE_und 5 68 #define ARM7_MODE_sys 0 69 //-------------------------------------------------------------------------- 70 71 //-------------------------------------------------------------------------- 72 // register definitions 73 74 /** ARM7 register type (all are 32-bit). */ 75 typedef INT32 ARM7_REG; 76 77 enum 78 { 79 ARM7_R0 = 0, ARM7_R1, ARM7_R2, ARM7_R3, ARM7_R4, ARM7_R5, ARM7_R6, ARM7_R7, 80 ARM7_R8, ARM7_R9, ARM7_R10, ARM7_R11, ARM7_R12, ARM7_R13, ARM7_R14, ARM7_R15 81 }; 82 83 /** R13 is stack pointer. */ 84 #define ARM7_SP 13 85 /** R14 is link/return address. */ 86 #define ARM7_LR 14 87 /** R15 is program counter. */ 88 #define ARM7_PC 15 89 /** CPSR control register. */ 90 #define ARM7_CPSR 16 91 /** SPSR control register. */ 92 #define ARM7_SPSR 17 93 //-------------------------------------------------------------------------- 94 95 //-------------------------------------------------------------------------- 96 /** ARM7 CPU state structure. */ 97 struct sARM7 98 { 99 /** All-purpose and control registers (for current mode). */ 100 ARM7_REG Rx [18]; 101 /** Banked registers for all operating modes. */ 102 ARM7_REG Rx_bank [6][10]; 103 104 /** FIQ and IRQ interrupt requests. */ 105 int fiq, irq; 106 107 /** Carry flag for barrel shifter and ALU operations. */ 108 int carry; 109 /** Overflow flag for arithmetic instructions. */ 110 int overflow; 111 112 /** Emulation control flags. */ 113 int flagi; 114 115 /** Instruction code. */ 116 UINT32 kod; 117 /** Cycle counter. */ 118 int cykle; 119 120 uint8 dc_ram[8*1024*1024]; 121 122 struct AICAinterface aica_interface; 123 struct _AICA *AICA; 124 }; 125 //-------------------------------------------------------------------------- 126 127 //-------------------------------------------------------------------------- 128 // public procedures 129 130 /** ARM7 allocate spu state. */ 131 struct sARM7* ARM7_Alloc (void); 132 133 void ARM7_Free (struct sARM7 *cpu); 134 135 /** ARM7 emulator init. */ 136 void ARM7_Init (struct sARM7 *cpu); 137 138 /** Power-ON reset. */ 139 void ARM7_HardReset (struct sARM7 *cpu); 140 /** Hardware reset via /RESET line. */ 141 void ARM7_SoftReset (struct sARM7 *cpu); 142 143 /** CPSR update, possibly changing operating mode. */ 144 void ARM7_SetCPSR (struct sARM7 *cpu, ARM7_REG sr); 145 146 /** Sets FIQ line state. */ 147 void ARM7_SetFIQ (struct sARM7 *cpu, int stan); 148 /** Sets IRQ line state. */ 149 void ARM7_SetIRQ (struct sARM7 *cpu, int stan); 150 151 /** Tests for pending interrupts, switches to one if possible. */ 152 void ARM7_CheckIRQ (struct sARM7 *cpu); 153 154 /** Single step. */ 155 void ARM7_Step (struct sARM7 *cpu); 156 /** Runs emulation for at least n cycles, returns actual amount of cycles 157 burned - normal interpreter. */ 158 int ARM7_Execute (struct sARM7 *cpu, int n); 159 //-------------------------------------------------------------------------- 160 161 enum 162 { 163 ARM7_IRQ_LINE=0, ARM7_FIRQ_LINE, 164 ARM7_NUM_LINES 165 }; 166 167 #ifdef ENABLE_DEBUGGER 168 extern UINT32 arm7_disasm( struct sARM7 *cpu, char *pBuf, UINT32 pc, UINT32 opcode ); 169 extern UINT32 thumb_disasm( struct sARM7 *cpu, char *pBuf, UINT32 pc, UINT16 opcode ); 170 #endif 171 #endif 172