1 // ---------------------------------------------------------------------------
2 // This file is part of reSID, a MOS6581 SID emulator engine.
3 // Copyright (C) 2002 Dag Lem <resid@nimrod.no>
4 //
5 // This program is free software; you can redistribute it and/or modify
6 // it under the terms of the GNU General Public License as published by
7 // the Free Software Foundation; either version 2 of the License, or
8 // (at your option) any later version.
9 //
10 // This program is distributed in the hope that it will be useful,
11 // but WITHOUT ANY WARRANTY; without even the implied warranty of
12 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 // GNU General Public License for more details.
14 //
15 // You should have received a copy of the GNU General Public License
16 // along with this program; if not, write to the Free Software
17 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 // ---------------------------------------------------------------------------
19
20 #define __ENVELOPE_CC__
21 #include "envelope.h"
22
23 RESID_NAMESPACE_START
24
25 // ----------------------------------------------------------------------------
26 // Constructor.
27 // ----------------------------------------------------------------------------
EnvelopeGenerator()28 EnvelopeGenerator::EnvelopeGenerator()
29 {
30 reset();
31 }
32
33 // ----------------------------------------------------------------------------
34 // SID reset.
35 // ----------------------------------------------------------------------------
reset()36 void EnvelopeGenerator::reset()
37 {
38 envelope_counter = 0;
39
40 attack = 0;
41 decay = 0;
42 sustain = 0;
43 release = 0;
44
45 gate = 0;
46
47 rate_counter = 0;
48 exponential_counter = 0;
49
50 state = RELEASE;
51 rate_period = rate_counter_period[release];
52 hold_zero = true;
53 }
54
55
56 // Rate counter periods are calculated from the Envelope Rates table in
57 // the Programmer's Reference Guide. The rate counter period is the number of
58 // cycles between each increment of the envelope counter.
59 // The rates have been verified by sampling ENV3.
60 //
61 // The rate counter is a 16 bit register which is incremented each cycle.
62 // When the counter reaches a specific comparison value, the envelope counter
63 // is incremented (attack) or decremented (decay/release) and the
64 // counter is zeroed.
65 //
66 // NB! Sampling ENV3 shows that the calculated values are not exact.
67 // It may seem like most calculated values have been rounded (.5 is rounded
68 // down) and 1 has beed added to the result. A possible explanation for this
69 // is that the SID designers have used the calculated values directly
70 // as rate counter comparison values, not considering a one cycle delay to
71 // zero the counter. This would yield an actual period of comparison value + 1.
72 //
73 // The exact rate counter periods can be determined e.g. by counting the number
74 // of cycles from envelope level 1 to envelope level 255, and dividing the
75 // number of cycles by 254. CIA1 timer A and B in linked mode can perform
76 // the cycle count. This is the method used to find the rates below.
77 // Making a full sample from 8 cycle shifted samples is also possible, however
78 // it is then necessary to wait exactly the same cycle tuned interval between
79 // each sample. This is because it is not possible to reset the rate counter
80 // (the test bit has no influence on the envelope generator whatsoever).
81 // The time of the first count of the envelope counter can not be exactly
82 // controlled except possibly by resetting the chip.
83 //
84 // To avoid the ADSR delay bug, sampling of ENV3 should be done using
85 // sustain = release = 0. This ensures that the attack state will not lower
86 // the current rate counter period. The maximum error from the SID chip is now
87 // 9 cycles. The code below adds a maximum error of 14 cycles:
88 //
89 // lda #$01
90 // l1: cmp $d41c
91 // bne l1
92 // ...
93 // lda #$ff
94 // l2: cmp $d41c
95 // bne l2
96 //
97 // The maximum timing error is thus 23 cycles, which yields a maximum error
98 // for the calculated rate period of 23/254 cycles. The described method is
99 // thus sufficient for exact calculation of rate periods.
100 //
101 reg16 EnvelopeGenerator::rate_counter_period[] = {
102 9, // 2ms*1.0MHz/256 = 7.81
103 32, // 8ms*1.0MHz/256 = 31.25
104 63, // 16ms*1.0MHz/256 = 62.50
105 95, // 24ms*1.0MHz/256 = 93.75
106 149, // 38ms*1.0MHz/256 = 148.44
107 220, // 56ms*1.0MHz/256 = 218.75
108 267, // 68ms*1.0MHz/256 = 265.63
109 313, // 80ms*1.0MHz/256 = 312.50
110 392, // 100ms*1.0MHz/256 = 390.63
111 977, // 250ms*1.0MHz/256 = 976.56
112 1954, // 500ms*1.0MHz/256 = 1953.13
113 3126, // 800ms*1.0MHz/256 = 3125.00
114 3907, // 1 s*1.0MHz/256 = 3906.25
115 11720, // 3 s*1.0MHz/256 = 11718.75
116 19532, // 5 s*1.0MHz/256 = 19531.25
117 31251 // 8 s*1.0MHz/256 = 31250.00
118 };
119
120
121 // For decay and release, the clock to the envelope counter is sequentially
122 // divided by 1, 2, 4, 8, 16, 30 to create a piece-wise linear approximation
123 // of an exponential at the envelope counter values 93, 54, 26, 14, 6.
124 // As a special case the period at zero level is 1; this only influences the
125 // ADSR boundary bug.
126 // All values have been verified by sampling ENV3.
127 //
128 // One extra cycle is spent at envelope level 0x5d in decay and release.
129 // This is a delay caused by the comparison with the exponential counter,
130 // and does not affect the rate counter. This has been verified by timing
131 // 256 consecutive complete envelopes with A = D = R = 1, S = 0, using CIA1
132 // timer A and B in linked mode. If the rate counter is not affected the
133 // period of each complete envelope is
134 // (255 + 162 + 39*2 + 28*4 + 12*8 + 8*16 + 6*30)*32 = 756*32 = 32352
135 // which corresponds exactly to the timed value divided by the number of
136 // complete envelopes.
137 // NB! This one cycle delay is not modeled.
138 //
139 // Lookup table to directly, from the envelope counter, find the current
140 // exponential counter period.
141 //
142 reg8 EnvelopeGenerator::exponential_counter_period[] = {
143 /* 0x00: */ 1, 30, 30, 30, 30, 30, 30, 16, // 0x06
144 /* 0x08: */ 16, 16, 16, 16, 16, 16, 16, 8, // 0x0e
145 /* 0x10: */ 8, 8, 8, 8, 8, 8, 8, 8,
146 /* 0x18: */ 8, 8, 8, 4, 4, 4, 4, 4, // 0x1a
147 /* 0x20: */ 4, 4, 4, 4, 4, 4, 4, 4,
148 /* 0x28: */ 4, 4, 4, 4, 4, 4, 4, 4,
149 /* 0x30: */ 4, 4, 4, 4, 4, 4, 4, 2, // 0x36
150 /* 0x38: */ 2, 2, 2, 2, 2, 2, 2, 2,
151 /* 0x40: */ 2, 2, 2, 2, 2, 2, 2, 2,
152 /* 0x48: */ 2, 2, 2, 2, 2, 2, 2, 2,
153 /* 0x50: */ 2, 2, 2, 2, 2, 2, 2, 2,
154 /* 0x58: */ 2, 2, 2, 2, 2, 2, 1, 1, // 0x5d
155 /* 0x60: */ 1, 1, 1, 1, 1, 1, 1, 1,
156 /* 0x68: */ 1, 1, 1, 1, 1, 1, 1, 1,
157 /* 0x70: */ 1, 1, 1, 1, 1, 1, 1, 1,
158 /* 0x78: */ 1, 1, 1, 1, 1, 1, 1, 1,
159 /* 0x80: */ 1, 1, 1, 1, 1, 1, 1, 1,
160 /* 0x88: */ 1, 1, 1, 1, 1, 1, 1, 1,
161 /* 0x90: */ 1, 1, 1, 1, 1, 1, 1, 1,
162 /* 0x98: */ 1, 1, 1, 1, 1, 1, 1, 1,
163 /* 0xa0: */ 1, 1, 1, 1, 1, 1, 1, 1,
164 /* 0xa8: */ 1, 1, 1, 1, 1, 1, 1, 1,
165 /* 0xb0: */ 1, 1, 1, 1, 1, 1, 1, 1,
166 /* 0xb8: */ 1, 1, 1, 1, 1, 1, 1, 1,
167 /* 0xc0: */ 1, 1, 1, 1, 1, 1, 1, 1,
168 /* 0xc8: */ 1, 1, 1, 1, 1, 1, 1, 1,
169 /* 0xd0: */ 1, 1, 1, 1, 1, 1, 1, 1,
170 /* 0xd8: */ 1, 1, 1, 1, 1, 1, 1, 1,
171 /* 0xe0: */ 1, 1, 1, 1, 1, 1, 1, 1,
172 /* 0xe8: */ 1, 1, 1, 1, 1, 1, 1, 1,
173 /* 0xf0: */ 1, 1, 1, 1, 1, 1, 1, 1,
174 /* 0xf8: */ 1, 1, 1, 1, 1, 1, 1, 1
175 };
176
177
178 // From the sustain levels it follows that both the low and high 4 bits of the
179 // envelope counter are compared to the 4-bit sustain value.
180 // This has been verified by sampling ENV3.
181 //
182 reg8 EnvelopeGenerator::sustain_level[] = {
183 0x00,
184 0x11,
185 0x22,
186 0x33,
187 0x44,
188 0x55,
189 0x66,
190 0x77,
191 0x88,
192 0x99,
193 0xaa,
194 0xbb,
195 0xcc,
196 0xdd,
197 0xee,
198 0xff,
199 };
200
201
202 // ----------------------------------------------------------------------------
203 // Register functions.
204 // ----------------------------------------------------------------------------
writeCONTROL_REG(reg8 control)205 void EnvelopeGenerator::writeCONTROL_REG(reg8 control)
206 {
207 reg8 gate_next = control & 0x01;
208
209 // The rate counter is never reset, thus there will be a delay before the
210 // envelope counter starts counting up (attack) or down (release).
211
212 // Gate bit on: Start attack, decay, sustain.
213 if (!gate && gate_next) {
214 state = ATTACK;
215 rate_period = rate_counter_period[attack];
216
217 // Switching to attack state unlocks the zero freeze.
218 hold_zero = false;
219 }
220 // Gate bit off: Start release.
221 else if (gate && !gate_next) {
222 state = RELEASE;
223 rate_period = rate_counter_period[release];
224 }
225
226 gate = gate_next;
227 }
228
writeATTACK_DECAY(reg8 attack_decay)229 void EnvelopeGenerator::writeATTACK_DECAY(reg8 attack_decay)
230 {
231 attack = (attack_decay >> 4) & 0x0f;
232 decay = attack_decay & 0x0f;
233 if (state == ATTACK) {
234 rate_period = rate_counter_period[attack];
235 }
236 else if (state == DECAY_SUSTAIN) {
237 rate_period = rate_counter_period[decay];
238 }
239 }
240
writeSUSTAIN_RELEASE(reg8 sustain_release)241 void EnvelopeGenerator::writeSUSTAIN_RELEASE(reg8 sustain_release)
242 {
243 sustain = (sustain_release >> 4) & 0x0f;
244 release = sustain_release & 0x0f;
245 if (state == RELEASE) {
246 rate_period = rate_counter_period[release];
247 }
248 }
249
readENV()250 reg8 EnvelopeGenerator::readENV()
251 {
252 return output();
253 }
254
255 RESID_NAMESPACE_STOP
256