1;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** 2;* File Name : startup_stm32f042.s 3;* Author : MCD Application Team 4;* Version : V1.5.0 5;* Date : 05-December-2014 6;* Description : STM32F042 Devices vector table for 7;* for MDK-ARM toolchain. 8;* This module performs: 9;* - Set the initial SP 10;* - Set the initial PC == Reset_Handler 11;* - Set the vector table entries with the exceptions ISR address 12;* - Configure the system clock 13;* - Branches to __main in the C library (which eventually 14;* calls main()). 15;* After Reset the CortexM0 processor is in Thread mode, 16;* priority is Privileged, and the Stack is set to Main. 17;* <<< Use Configuration Wizard in Context Menu >>> 18;******************************************************************************* 19; @attention 20; 21; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 22; You may not use this file except in compliance with the License. 23; You may obtain a copy of the License at: 24; 25; http://www.st.com/software_license_agreement_liberty_v2 26; 27; Unless required by applicable law or agreed to in writing, software 28; distributed under the License is distributed on an "AS IS" BASIS, 29; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 30; See the License for the specific language governing permissions and 31; limitations under the License. 32; 33;******************************************************************************* 34; 35; Amount of memory (in bytes) allocated for Stack 36; Tailor this value to your application needs 37; <h> Stack Configuration 38; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 39; </h> 40 41Stack_Size EQU 0x00000400 42 43 AREA STACK, NOINIT, READWRITE, ALIGN=3 44Stack_Mem SPACE Stack_Size 45__initial_sp 46 47 48; <h> Heap Configuration 49; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 50; </h> 51 52Heap_Size EQU 0x00000200 53 54 AREA HEAP, NOINIT, READWRITE, ALIGN=3 55__heap_base 56Heap_Mem SPACE Heap_Size 57__heap_limit 58 59 PRESERVE8 60 THUMB 61 62 63; Vector Table Mapped to Address 0 at Reset 64 AREA RESET, DATA, READONLY 65 EXPORT __Vectors 66 EXPORT __Vectors_End 67 EXPORT __Vectors_Size 68 69__Vectors DCD __initial_sp ; Top of Stack 70 DCD Reset_Handler ; Reset Handler 71 DCD NMI_Handler ; NMI Handler 72 DCD HardFault_Handler ; Hard Fault Handler 73 DCD 0 ; Reserved 74 DCD 0 ; Reserved 75 DCD 0 ; Reserved 76 DCD 0 ; Reserved 77 DCD 0 ; Reserved 78 DCD 0 ; Reserved 79 DCD 0 ; Reserved 80 DCD SVC_Handler ; SVCall Handler 81 DCD 0 ; Reserved 82 DCD 0 ; Reserved 83 DCD PendSV_Handler ; PendSV Handler 84 DCD SysTick_Handler ; SysTick Handler 85 86 ; External Interrupts 87 DCD WWDG_IRQHandler ; Window Watchdog 88 DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect 89 DCD RTC_IRQHandler ; RTC through EXTI Line 90 DCD FLASH_IRQHandler ; FLASH 91 DCD RCC_CRS_IRQHandler ; RCC and CRS 92 DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 93 DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 94 DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 95 DCD TSC_IRQHandler ; TS 96 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 97 DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 98 DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4, Channel 5 99 DCD ADC1_IRQHandler ; ADC1 100 DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation 101 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 102 DCD TIM2_IRQHandler ; TIM2 103 DCD TIM3_IRQHandler ; TIM3 104 DCD 0 ; Reserved 105 DCD 0 ; Reserved 106 DCD TIM14_IRQHandler ; TIM14 107 DCD 0 ; Reserved 108 DCD TIM16_IRQHandler ; TIM16 109 DCD TIM17_IRQHandler ; TIM17 110 DCD I2C1_IRQHandler ; I2C1 111 DCD 0 ; Reserved 112 DCD SPI1_IRQHandler ; SPI1 113 DCD SPI2_IRQHandler ; SPI2 114 DCD USART1_IRQHandler ; USART1 115 DCD USART2_IRQHandler ; USART2 116 DCD 0 ; Reserved 117 DCD CEC_CAN_IRQHandler ; CEC and CAN 118 DCD USB_IRQHandler ; USB 119 120__Vectors_End 121 122__Vectors_Size EQU __Vectors_End - __Vectors 123 124 AREA |.text|, CODE, READONLY 125 126; Reset handler routine 127Reset_Handler PROC 128 EXPORT Reset_Handler [WEAK] 129 IMPORT __main 130 IMPORT SystemInit 131 132 133 134 LDR R0, =__initial_sp ; set stack pointer 135 MSR MSP, R0 136 137;;Check if boot space corresponds to test memory 138 139 LDR R0,=0x00000004 140 LDR R1, [R0] 141 LSRS R1, R1, #24 142 LDR R2,=0x1F 143 CMP R1, R2 144 145 BNE ApplicationStart 146 147;; SYSCFG clock enable 148 149 LDR R0,=0x40021018 150 LDR R1,=0x00000001 151 STR R1, [R0] 152 153;; Set CFGR1 register with flash memory remap at address 0 154 155 LDR R0,=0x40010000 156 LDR R1,=0x00000000 157 STR R1, [R0] 158ApplicationStart 159 LDR R0, =SystemInit 160 BLX R0 161 LDR R0, =__main 162 BX R0 163 ENDP 164 165; Dummy Exception Handlers (infinite loops which can be modified) 166 167NMI_Handler PROC 168 EXPORT NMI_Handler [WEAK] 169 B . 170 ENDP 171HardFault_Handler\ 172 PROC 173 EXPORT HardFault_Handler [WEAK] 174 B . 175 ENDP 176SVC_Handler PROC 177 EXPORT SVC_Handler [WEAK] 178 B . 179 ENDP 180PendSV_Handler PROC 181 EXPORT PendSV_Handler [WEAK] 182 B . 183 ENDP 184SysTick_Handler PROC 185 EXPORT SysTick_Handler [WEAK] 186 B . 187 ENDP 188 189Default_Handler PROC 190 191 EXPORT WWDG_IRQHandler [WEAK] 192 EXPORT PVD_VDDIO2_IRQHandler [WEAK] 193 EXPORT RTC_IRQHandler [WEAK] 194 EXPORT FLASH_IRQHandler [WEAK] 195 EXPORT RCC_CRS_IRQHandler [WEAK] 196 EXPORT EXTI0_1_IRQHandler [WEAK] 197 EXPORT EXTI2_3_IRQHandler [WEAK] 198 EXPORT EXTI4_15_IRQHandler [WEAK] 199 EXPORT TSC_IRQHandler [WEAK] 200 EXPORT DMA1_Channel1_IRQHandler [WEAK] 201 EXPORT DMA1_Channel2_3_IRQHandler [WEAK] 202 EXPORT DMA1_Channel4_5_IRQHandler [WEAK] 203 EXPORT ADC1_IRQHandler [WEAK] 204 EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] 205 EXPORT TIM1_CC_IRQHandler [WEAK] 206 EXPORT TIM2_IRQHandler [WEAK] 207 EXPORT TIM3_IRQHandler [WEAK] 208 EXPORT TIM14_IRQHandler [WEAK] 209 EXPORT TIM16_IRQHandler [WEAK] 210 EXPORT TIM17_IRQHandler [WEAK] 211 EXPORT I2C1_IRQHandler [WEAK] 212 EXPORT SPI1_IRQHandler [WEAK] 213 EXPORT SPI2_IRQHandler [WEAK] 214 EXPORT USART1_IRQHandler [WEAK] 215 EXPORT USART2_IRQHandler [WEAK] 216 EXPORT CEC_CAN_IRQHandler [WEAK] 217 EXPORT USB_IRQHandler [WEAK] 218 219 220WWDG_IRQHandler 221PVD_VDDIO2_IRQHandler 222RTC_IRQHandler 223FLASH_IRQHandler 224RCC_CRS_IRQHandler 225EXTI0_1_IRQHandler 226EXTI2_3_IRQHandler 227EXTI4_15_IRQHandler 228TSC_IRQHandler 229DMA1_Channel1_IRQHandler 230DMA1_Channel2_3_IRQHandler 231DMA1_Channel4_5_IRQHandler 232ADC1_IRQHandler 233TIM1_BRK_UP_TRG_COM_IRQHandler 234TIM1_CC_IRQHandler 235TIM2_IRQHandler 236TIM3_IRQHandler 237TIM14_IRQHandler 238TIM16_IRQHandler 239TIM17_IRQHandler 240I2C1_IRQHandler 241SPI1_IRQHandler 242SPI2_IRQHandler 243USART1_IRQHandler 244USART2_IRQHandler 245CEC_CAN_IRQHandler 246USB_IRQHandler 247 248 B . 249 250 ENDP 251 252 ALIGN 253 254;******************************************************************************* 255; User Stack and Heap initialization 256;******************************************************************************* 257 IF :DEF:__MICROLIB 258 259 EXPORT __initial_sp 260 EXPORT __heap_base 261 EXPORT __heap_limit 262 263 ELSE 264 265 IMPORT __use_two_region_memory 266 EXPORT __user_initial_stackheap 267 268__user_initial_stackheap 269 270 LDR R0, = Heap_Mem 271 LDR R1, =(Stack_Mem + Stack_Size) 272 LDR R2, = (Heap_Mem + Heap_Size) 273 LDR R3, = Stack_Mem 274 BX LR 275 276 ALIGN 277 278 ENDIF 279 280 END 281 282;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** 283