1;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** 2;* File Name : startup_stm32f070xb.s 3;* Author : MCD Application Team 4;* Version : V1.5.0 5;* Date : 05-December-2014 6;* Description : STM32F070CB/STM32F070RB devices vector table for MDK-ARM toolchain. 7;* This module performs: 8;* - Set the initial SP 9;* - Set the initial PC == Reset_Handler 10;* - Set the vector table entries with the exceptions ISR address 11;* - Configure the system clock 12;* - Branches to __main in the C library (which eventually 13;* calls main()). 14;* After Reset the CortexM0 processor is in Thread mode, 15;* priority is Privileged, and the Stack is set to Main. 16;* <<< Use Configuration Wizard in Context Menu >>> 17;******************************************************************************* 18; @attention 19; 20; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 21; You may not use this file except in compliance with the License. 22; You may obtain a copy of the License at: 23; 24; http://www.st.com/software_license_agreement_liberty_v2 25; 26; Unless required by applicable law or agreed to in writing, software 27; distributed under the License is distributed on an "AS IS" BASIS, 28; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 29; See the License for the specific language governing permissions and 30; limitations under the License. 31; 32;******************************************************************************* 33; 34; Amount of memory (in bytes) allocated for Stack 35; Tailor this value to your application needs 36; <h> Stack Configuration 37; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 38; </h> 39 40Stack_Size EQU 0x00000400 41 42 AREA STACK, NOINIT, READWRITE, ALIGN=3 43Stack_Mem SPACE Stack_Size 44__initial_sp 45 46 47; <h> Heap Configuration 48; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 49; </h> 50 51Heap_Size EQU 0x00000200 52 53 AREA HEAP, NOINIT, READWRITE, ALIGN=3 54__heap_base 55Heap_Mem SPACE Heap_Size 56__heap_limit 57 58 PRESERVE8 59 THUMB 60 61 62; Vector Table Mapped to Address 0 at Reset 63 AREA RESET, DATA, READONLY 64 EXPORT __Vectors 65 EXPORT __Vectors_End 66 EXPORT __Vectors_Size 67 68__Vectors DCD __initial_sp ; Top of Stack 69 DCD Reset_Handler ; Reset Handler 70 DCD NMI_Handler ; NMI Handler 71 DCD HardFault_Handler ; Hard Fault Handler 72 DCD 0 ; Reserved 73 DCD 0 ; Reserved 74 DCD 0 ; Reserved 75 DCD 0 ; Reserved 76 DCD 0 ; Reserved 77 DCD 0 ; Reserved 78 DCD 0 ; Reserved 79 DCD SVC_Handler ; SVCall Handler 80 DCD 0 ; Reserved 81 DCD 0 ; Reserved 82 DCD PendSV_Handler ; PendSV Handler 83 DCD SysTick_Handler ; SysTick Handler 84 85 ; External Interrupts 86 DCD WWDG_IRQHandler ; Window Watchdog 87 DCD 0 ; Reserved 88 DCD RTC_IRQHandler ; RTC through EXTI Line 89 DCD FLASH_IRQHandler ; FLASH 90 DCD RCC_IRQHandler ; RCC 91 DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 92 DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 93 DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 94 DCD 0 ; Reserved 95 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 96 DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 97 DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 98 DCD ADC1_IRQHandler ; ADC1 99 DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation 100 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 101 DCD 0 ; Reserved 102 DCD TIM3_IRQHandler ; TIM3 103 DCD TIM6_IRQHandler ; TIM6 104 DCD TIM7_IRQHandler ; TIM7 105 DCD TIM14_IRQHandler ; TIM14 106 DCD TIM15_IRQHandler ; TIM15 107 DCD TIM16_IRQHandler ; TIM16 108 DCD TIM17_IRQHandler ; TIM17 109 DCD I2C1_IRQHandler ; I2C1 110 DCD I2C2_IRQHandler ; I2C2 111 DCD SPI1_IRQHandler ; SPI1 112 DCD SPI2_IRQHandler ; SPI2 113 DCD USART1_IRQHandler ; USART1 114 DCD USART2_IRQHandler ; USART2 115 DCD USART3_4_IRQHandler ; USART3 & USART4 116 DCD 0 ; Reserved 117 DCD USB_IRQHandler ; USB 118 119__Vectors_End 120 121__Vectors_Size EQU __Vectors_End - __Vectors 122 123 AREA |.text|, CODE, READONLY 124 125; Reset handler routine 126Reset_Handler PROC 127 EXPORT Reset_Handler [WEAK] 128 IMPORT __main 129 IMPORT SystemInit 130 131 132 133 LDR R0, =__initial_sp ; set stack pointer 134 MSR MSP, R0 135 136;;Check if boot space corresponds to test memory 137 138 LDR R0,=0x00000004 139 LDR R1, [R0] 140 LSRS R1, R1, #24 141 LDR R2,=0x1F 142 CMP R1, R2 143 144 BNE ApplicationStart 145 146;; SYSCFG clock enable 147 148 LDR R0,=0x40021018 149 LDR R1,=0x00000001 150 STR R1, [R0] 151 152;; Set CFGR1 register with flash memory remap at address 0 153 154 LDR R0,=0x40010000 155 LDR R1,=0x00000000 156 STR R1, [R0] 157ApplicationStart 158 LDR R0, =SystemInit 159 BLX R0 160 LDR R0, =__main 161 BX R0 162 ENDP 163 164; Dummy Exception Handlers (infinite loops which can be modified) 165 166NMI_Handler PROC 167 EXPORT NMI_Handler [WEAK] 168 B . 169 ENDP 170HardFault_Handler\ 171 PROC 172 EXPORT HardFault_Handler [WEAK] 173 B . 174 ENDP 175SVC_Handler PROC 176 EXPORT SVC_Handler [WEAK] 177 B . 178 ENDP 179PendSV_Handler PROC 180 EXPORT PendSV_Handler [WEAK] 181 B . 182 ENDP 183SysTick_Handler PROC 184 EXPORT SysTick_Handler [WEAK] 185 B . 186 ENDP 187 188Default_Handler PROC 189 190 EXPORT WWDG_IRQHandler [WEAK] 191 EXPORT RTC_IRQHandler [WEAK] 192 EXPORT FLASH_IRQHandler [WEAK] 193 EXPORT RCC_IRQHandler [WEAK] 194 EXPORT EXTI0_1_IRQHandler [WEAK] 195 EXPORT EXTI2_3_IRQHandler [WEAK] 196 EXPORT EXTI4_15_IRQHandler [WEAK] 197 EXPORT DMA1_Channel1_IRQHandler [WEAK] 198 EXPORT DMA1_Channel2_3_IRQHandler [WEAK] 199 EXPORT DMA1_Channel4_5_IRQHandler [WEAK] 200 EXPORT ADC1_IRQHandler [WEAK] 201 EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] 202 EXPORT TIM1_CC_IRQHandler [WEAK] 203 EXPORT TIM3_IRQHandler [WEAK] 204 EXPORT TIM6_IRQHandler [WEAK] 205 EXPORT TIM7_IRQHandler [WEAK] 206 EXPORT TIM14_IRQHandler [WEAK] 207 EXPORT TIM15_IRQHandler [WEAK] 208 EXPORT TIM16_IRQHandler [WEAK] 209 EXPORT TIM17_IRQHandler [WEAK] 210 EXPORT I2C1_IRQHandler [WEAK] 211 EXPORT I2C2_IRQHandler [WEAK] 212 EXPORT SPI1_IRQHandler [WEAK] 213 EXPORT SPI2_IRQHandler [WEAK] 214 EXPORT USART1_IRQHandler [WEAK] 215 EXPORT USART2_IRQHandler [WEAK] 216 EXPORT USART3_4_IRQHandler [WEAK] 217 EXPORT USB_IRQHandler [WEAK] 218 219 220WWDG_IRQHandler 221RTC_IRQHandler 222FLASH_IRQHandler 223RCC_IRQHandler 224EXTI0_1_IRQHandler 225EXTI2_3_IRQHandler 226EXTI4_15_IRQHandler 227DMA1_Channel1_IRQHandler 228DMA1_Channel2_3_IRQHandler 229DMA1_Channel4_5_IRQHandler 230ADC1_IRQHandler 231TIM1_BRK_UP_TRG_COM_IRQHandler 232TIM1_CC_IRQHandler 233TIM3_IRQHandler 234TIM6_IRQHandler 235TIM7_IRQHandler 236TIM14_IRQHandler 237TIM15_IRQHandler 238TIM16_IRQHandler 239TIM17_IRQHandler 240I2C1_IRQHandler 241I2C2_IRQHandler 242SPI1_IRQHandler 243SPI2_IRQHandler 244USART1_IRQHandler 245USART2_IRQHandler 246USART3_4_IRQHandler 247USB_IRQHandler 248 249 B . 250 251 ENDP 252 253 ALIGN 254 255;******************************************************************************* 256; User Stack and Heap initialization 257;******************************************************************************* 258 IF :DEF:__MICROLIB 259 260 EXPORT __initial_sp 261 EXPORT __heap_base 262 EXPORT __heap_limit 263 264 ELSE 265 266 IMPORT __use_two_region_memory 267 EXPORT __user_initial_stackheap 268 269__user_initial_stackheap 270 271 LDR R0, = Heap_Mem 272 LDR R1, =(Stack_Mem + Stack_Size) 273 LDR R2, = (Heap_Mem + Heap_Size) 274 LDR R3, = Stack_Mem 275 BX LR 276 277 ALIGN 278 279 ENDIF 280 281 END 282 283;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** 284