1;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** 2;* File Name : startup_stm32f031.s 3;* Author : MCD Application Team 4;* Version : V1.5.0 5;* Date : 24-December-2014 6;* Description : STM32F031 devices vector table for EWARM toolchain. 7;* This module performs: 8;* - Set the initial SP 9;* - Set the initial PC == iar_program_start, 10;* - Set the vector table entries with the exceptions ISR 11;* address 12;* - Configure the system clock 13;* - Branches to main in the C library (which eventually 14;* calls main()). 15;* After Reset the Cortex-M0 processor is in Thread mode, 16;* priority is Privileged, and the Stack is set to Main. 17;******************************************************************************* 18; @attention 19; 20; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 21; You may not use this file except in compliance with the License. 22; You may obtain a copy of the License at: 23; 24; http://www.st.com/software_license_agreement_liberty_v2 25; 26; Unless required by applicable law or agreed to in writing, software 27; distributed under the License is distributed on an "AS IS" BASIS, 28; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 29; See the License for the specific language governing permissions and 30; limitations under the License. 31; 32;******************************************************************************* 33; 34; 35; The modules in this file are included in the libraries, and may be replaced 36; by any user-defined modules that define the PUBLIC symbol _program_start or 37; a user defined start symbol. 38; To override the cstartup defined in the library, simply add your modified 39; version to the workbench project. 40; 41; The vector table is normally located at address 0. 42; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. 43; The name "__vector_table" has special meaning for C-SPY: 44; it is where the SP start value is found, and the NVIC vector 45; table register (VTOR) is initialized to this address if != 0. 46; 47; Cortex-M version 48; 49 50 MODULE ?cstartup 51 52 ;; Forward declaration of sections. 53 SECTION CSTACK:DATA:NOROOT(3) 54 55 SECTION .intvec:CODE:NOROOT(2) 56 57 EXTERN __iar_program_start 58 EXTERN SystemInit 59 PUBLIC __vector_table 60 61 DATA 62__vector_table 63 DCD sfe(CSTACK) 64 DCD Reset_Handler ; Reset Handler 65 66 DCD NMI_Handler ; NMI Handler 67 DCD HardFault_Handler ; Hard Fault Handler 68 DCD 0 ; Reserved 69 DCD 0 ; Reserved 70 DCD 0 ; Reserved 71 DCD 0 ; Reserved 72 DCD 0 ; Reserved 73 DCD 0 ; Reserved 74 DCD 0 ; Reserved 75 DCD SVC_Handler ; SVCall Handler 76 DCD 0 ; Reserved 77 DCD 0 ; Reserved 78 DCD PendSV_Handler ; PendSV Handler 79 DCD SysTick_Handler ; SysTick Handler 80 81 ; External Interrupts 82 DCD WWDG_IRQHandler ; Window Watchdog 83 DCD PVD_IRQHandler ; PVD through EXTI Line detect 84 DCD RTC_IRQHandler ; RTC through EXTI Line 85 DCD FLASH_IRQHandler ; FLASH 86 DCD RCC_IRQHandler ; RCC 87 DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 88 DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 89 DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 90 DCD 0 ; Reserved 91 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 92 DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 93 DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 94 DCD ADC1_IRQHandler ; ADC1 95 DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation 96 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 97 DCD TIM2_IRQHandler ; TIM2 98 DCD TIM3_IRQHandler ; TIM3 99 DCD 0 ; Reserved 100 DCD 0 ; Reserved 101 DCD TIM14_IRQHandler ; TIM14 102 DCD 0 ; Reserved 103 DCD TIM16_IRQHandler ; TIM16 104 DCD TIM17_IRQHandler ; TIM17 105 DCD I2C1_IRQHandler ; I2C1 106 DCD 0 ; Reserved 107 DCD SPI1_IRQHandler ; SPI1 108 DCD 0 ; Reserved 109 DCD USART1_IRQHandler ; USART1 110 111;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 112;; 113;; Default interrupt handlers. 114;; 115 THUMB 116 117 PUBWEAK Reset_Handler 118 SECTION .text:CODE:NOROOT:REORDER(2) 119Reset_Handler 120 121 LDR R0, =sfe(CSTACK) ; set stack pointer 122 MSR MSP, R0 123 124;;Check if boot space corresponds to test memory 125 LDR R0,=0x00000004 126 LDR R1, [R0] 127 LSRS R1, R1, #24 128 LDR R2,=0x1F 129 CMP R1, R2 130 131 BNE ApplicationStart 132;; SYSCFG clock enable 133 LDR R0,=0x40021018 134 LDR R1,=0x00000001 135 STR R1, [R0] 136 137;; Set CFGR1 register with flash memory remap at address 0 138 139 LDR R0,=0x40010000 140 LDR R1,=0x00000000 141 STR R1, [R0] 142ApplicationStart 143 LDR R0, =SystemInit 144 BLX R0 145 LDR R0, =__iar_program_start 146 BX R0 147 148 PUBWEAK NMI_Handler 149 SECTION .text:CODE:NOROOT:REORDER(1) 150NMI_Handler 151 B NMI_Handler 152 153 154 PUBWEAK HardFault_Handler 155 SECTION .text:CODE:NOROOT:REORDER(1) 156HardFault_Handler 157 B HardFault_Handler 158 159 160 PUBWEAK SVC_Handler 161 SECTION .text:CODE:NOROOT:REORDER(1) 162SVC_Handler 163 B SVC_Handler 164 165 166 PUBWEAK PendSV_Handler 167 SECTION .text:CODE:NOROOT:REORDER(1) 168PendSV_Handler 169 B PendSV_Handler 170 171 172 PUBWEAK SysTick_Handler 173 SECTION .text:CODE:NOROOT:REORDER(1) 174SysTick_Handler 175 B SysTick_Handler 176 177 178 PUBWEAK WWDG_IRQHandler 179 SECTION .text:CODE:NOROOT:REORDER(1) 180WWDG_IRQHandler 181 B WWDG_IRQHandler 182 183 184 PUBWEAK PVD_IRQHandler 185 SECTION .text:CODE:NOROOT:REORDER(1) 186PVD_IRQHandler 187 B PVD_IRQHandler 188 189 190 PUBWEAK RTC_IRQHandler 191 SECTION .text:CODE:NOROOT:REORDER(1) 192RTC_IRQHandler 193 B RTC_IRQHandler 194 195 196 PUBWEAK FLASH_IRQHandler 197 SECTION .text:CODE:NOROOT:REORDER(1) 198FLASH_IRQHandler 199 B FLASH_IRQHandler 200 201 202 PUBWEAK RCC_IRQHandler 203 SECTION .text:CODE:NOROOT:REORDER(1) 204RCC_IRQHandler 205 B RCC_IRQHandler 206 207 208 PUBWEAK EXTI0_1_IRQHandler 209 SECTION .text:CODE:NOROOT:REORDER(1) 210EXTI0_1_IRQHandler 211 B EXTI0_1_IRQHandler 212 213 214 PUBWEAK EXTI2_3_IRQHandler 215 SECTION .text:CODE:NOROOT:REORDER(1) 216EXTI2_3_IRQHandler 217 B EXTI2_3_IRQHandler 218 219 220 PUBWEAK EXTI4_15_IRQHandler 221 SECTION .text:CODE:NOROOT:REORDER(1) 222EXTI4_15_IRQHandler 223 B EXTI4_15_IRQHandler 224 225 226 PUBWEAK DMA1_Channel1_IRQHandler 227 SECTION .text:CODE:NOROOT:REORDER(1) 228DMA1_Channel1_IRQHandler 229 B DMA1_Channel1_IRQHandler 230 231 232 PUBWEAK DMA1_Channel2_3_IRQHandler 233 SECTION .text:CODE:NOROOT:REORDER(1) 234DMA1_Channel2_3_IRQHandler 235 B DMA1_Channel2_3_IRQHandler 236 237 238 PUBWEAK DMA1_Channel4_5_IRQHandler 239 SECTION .text:CODE:NOROOT:REORDER(1) 240DMA1_Channel4_5_IRQHandler 241 B DMA1_Channel4_5_IRQHandler 242 243 244 PUBWEAK ADC1_IRQHandler 245 SECTION .text:CODE:NOROOT:REORDER(1) 246ADC1_IRQHandler 247 B ADC1_IRQHandler 248 249 250 PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler 251 SECTION .text:CODE:NOROOT:REORDER(1) 252TIM1_BRK_UP_TRG_COM_IRQHandler 253 B TIM1_BRK_UP_TRG_COM_IRQHandler 254 255 256 PUBWEAK TIM1_CC_IRQHandler 257 SECTION .text:CODE:NOROOT:REORDER(1) 258TIM1_CC_IRQHandler 259 B TIM1_CC_IRQHandler 260 261 262 PUBWEAK TIM2_IRQHandler 263 SECTION .text:CODE:NOROOT:REORDER(1) 264TIM2_IRQHandler 265 B TIM2_IRQHandler 266 267 268 PUBWEAK TIM3_IRQHandler 269 SECTION .text:CODE:NOROOT:REORDER(1) 270TIM3_IRQHandler 271 B TIM3_IRQHandler 272 273 274 PUBWEAK TIM14_IRQHandler 275 SECTION .text:CODE:NOROOT:REORDER(1) 276TIM14_IRQHandler 277 B TIM14_IRQHandler 278 279 280 PUBWEAK TIM16_IRQHandler 281 SECTION .text:CODE:NOROOT:REORDER(1) 282TIM16_IRQHandler 283 B TIM16_IRQHandler 284 285 286 PUBWEAK TIM17_IRQHandler 287 SECTION .text:CODE:NOROOT:REORDER(1) 288TIM17_IRQHandler 289 B TIM17_IRQHandler 290 291 292 PUBWEAK I2C1_IRQHandler 293 SECTION .text:CODE:NOROOT:REORDER(1) 294I2C1_IRQHandler 295 B I2C1_IRQHandler 296 297 298 PUBWEAK SPI1_IRQHandler 299 SECTION .text:CODE:NOROOT:REORDER(1) 300SPI1_IRQHandler 301 B SPI1_IRQHandler 302 303 304 PUBWEAK USART1_IRQHandler 305 SECTION .text:CODE:NOROOT:REORDER(1) 306USART1_IRQHandler 307 B USART1_IRQHandler 308 309 310 END 311;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** 312