1 /** 2 ****************************************************************************** 3 * @file stm32f10x_dma.h 4 * @author MCD Application Team 5 * @version V3.1.2 6 * @date 09/28/2009 7 * @brief This file contains all the functions prototypes for the DMA firmware 8 * library. 9 ****************************************************************************** 10 * @copy 11 * 12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 * 19 * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2> 20 */ 21 22 /* Define to prevent recursive inclusion -------------------------------------*/ 23 #ifndef __STM32F10x_DMA_H 24 #define __STM32F10x_DMA_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /* Includes ------------------------------------------------------------------*/ 31 #include "stm32f10x.h" 32 33 /** @addtogroup STM32F10x_StdPeriph_Driver 34 * @{ 35 */ 36 37 /** @addtogroup DMA 38 * @{ 39 */ 40 41 /** @defgroup DMA_Exported_Types 42 * @{ 43 */ 44 45 /** 46 * @brief DMA Init structure definition 47 */ 48 49 typedef struct 50 { 51 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ 52 53 uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ 54 55 uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. 56 This parameter can be a value of @ref DMA_data_transfer_direction */ 57 58 uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. 59 The data unit is equal to the configuration set in DMA_PeripheralDataSize 60 or DMA_MemoryDataSize members depending in the transfer direction. */ 61 62 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. 63 This parameter can be a value of @ref DMA_peripheral_incremented_mode */ 64 65 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. 66 This parameter can be a value of @ref DMA_memory_incremented_mode */ 67 68 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. 69 This parameter can be a value of @ref DMA_peripheral_data_size */ 70 71 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. 72 This parameter can be a value of @ref DMA_memory_data_size */ 73 74 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. 75 This parameter can be a value of @ref DMA_circular_normal_mode. 76 @note: The circular buffer mode cannot be used if the memory-to-memory 77 data transfer is configured on the selected Channel */ 78 79 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. 80 This parameter can be a value of @ref DMA_priority_level */ 81 82 uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. 83 This parameter can be a value of @ref DMA_memory_to_memory */ 84 }DMA_InitTypeDef; 85 86 /** 87 * @} 88 */ 89 90 /** @defgroup DMA_Exported_Constants 91 * @{ 92 */ 93 94 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ 95 ((PERIPH) == DMA1_Channel2) || \ 96 ((PERIPH) == DMA1_Channel3) || \ 97 ((PERIPH) == DMA1_Channel4) || \ 98 ((PERIPH) == DMA1_Channel5) || \ 99 ((PERIPH) == DMA1_Channel6) || \ 100 ((PERIPH) == DMA1_Channel7) || \ 101 ((PERIPH) == DMA2_Channel1) || \ 102 ((PERIPH) == DMA2_Channel2) || \ 103 ((PERIPH) == DMA2_Channel3) || \ 104 ((PERIPH) == DMA2_Channel4) || \ 105 ((PERIPH) == DMA2_Channel5)) 106 107 /** @defgroup DMA_data_transfer_direction 108 * @{ 109 */ 110 111 #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) 112 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) 113 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ 114 ((DIR) == DMA_DIR_PeripheralSRC)) 115 /** 116 * @} 117 */ 118 119 /** @defgroup DMA_peripheral_incremented_mode 120 * @{ 121 */ 122 123 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) 124 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) 125 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ 126 ((STATE) == DMA_PeripheralInc_Disable)) 127 /** 128 * @} 129 */ 130 131 /** @defgroup DMA_memory_incremented_mode 132 * @{ 133 */ 134 135 #define DMA_MemoryInc_Enable ((uint32_t)0x00000080) 136 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) 137 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ 138 ((STATE) == DMA_MemoryInc_Disable)) 139 /** 140 * @} 141 */ 142 143 /** @defgroup DMA_peripheral_data_size 144 * @{ 145 */ 146 147 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) 148 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) 149 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) 150 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ 151 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ 152 ((SIZE) == DMA_PeripheralDataSize_Word)) 153 /** 154 * @} 155 */ 156 157 /** @defgroup DMA_memory_data_size 158 * @{ 159 */ 160 161 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) 162 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) 163 #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) 164 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ 165 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ 166 ((SIZE) == DMA_MemoryDataSize_Word)) 167 /** 168 * @} 169 */ 170 171 /** @defgroup DMA_circular_normal_mode 172 * @{ 173 */ 174 175 #define DMA_Mode_Circular ((uint32_t)0x00000020) 176 #define DMA_Mode_Normal ((uint32_t)0x00000000) 177 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) 178 /** 179 * @} 180 */ 181 182 /** @defgroup DMA_priority_level 183 * @{ 184 */ 185 186 #define DMA_Priority_VeryHigh ((uint32_t)0x00003000) 187 #define DMA_Priority_High ((uint32_t)0x00002000) 188 #define DMA_Priority_Medium ((uint32_t)0x00001000) 189 #define DMA_Priority_Low ((uint32_t)0x00000000) 190 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ 191 ((PRIORITY) == DMA_Priority_High) || \ 192 ((PRIORITY) == DMA_Priority_Medium) || \ 193 ((PRIORITY) == DMA_Priority_Low)) 194 /** 195 * @} 196 */ 197 198 /** @defgroup DMA_memory_to_memory 199 * @{ 200 */ 201 202 #define DMA_M2M_Enable ((uint32_t)0x00004000) 203 #define DMA_M2M_Disable ((uint32_t)0x00000000) 204 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) 205 206 /** 207 * @} 208 */ 209 210 /** @defgroup DMA_interrupts_definition 211 * @{ 212 */ 213 214 #define DMA_IT_TC ((uint32_t)0x00000002) 215 #define DMA_IT_HT ((uint32_t)0x00000004) 216 #define DMA_IT_TE ((uint32_t)0x00000008) 217 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) 218 219 #define DMA1_IT_GL1 ((uint32_t)0x00000001) 220 #define DMA1_IT_TC1 ((uint32_t)0x00000002) 221 #define DMA1_IT_HT1 ((uint32_t)0x00000004) 222 #define DMA1_IT_TE1 ((uint32_t)0x00000008) 223 #define DMA1_IT_GL2 ((uint32_t)0x00000010) 224 #define DMA1_IT_TC2 ((uint32_t)0x00000020) 225 #define DMA1_IT_HT2 ((uint32_t)0x00000040) 226 #define DMA1_IT_TE2 ((uint32_t)0x00000080) 227 #define DMA1_IT_GL3 ((uint32_t)0x00000100) 228 #define DMA1_IT_TC3 ((uint32_t)0x00000200) 229 #define DMA1_IT_HT3 ((uint32_t)0x00000400) 230 #define DMA1_IT_TE3 ((uint32_t)0x00000800) 231 #define DMA1_IT_GL4 ((uint32_t)0x00001000) 232 #define DMA1_IT_TC4 ((uint32_t)0x00002000) 233 #define DMA1_IT_HT4 ((uint32_t)0x00004000) 234 #define DMA1_IT_TE4 ((uint32_t)0x00008000) 235 #define DMA1_IT_GL5 ((uint32_t)0x00010000) 236 #define DMA1_IT_TC5 ((uint32_t)0x00020000) 237 #define DMA1_IT_HT5 ((uint32_t)0x00040000) 238 #define DMA1_IT_TE5 ((uint32_t)0x00080000) 239 #define DMA1_IT_GL6 ((uint32_t)0x00100000) 240 #define DMA1_IT_TC6 ((uint32_t)0x00200000) 241 #define DMA1_IT_HT6 ((uint32_t)0x00400000) 242 #define DMA1_IT_TE6 ((uint32_t)0x00800000) 243 #define DMA1_IT_GL7 ((uint32_t)0x01000000) 244 #define DMA1_IT_TC7 ((uint32_t)0x02000000) 245 #define DMA1_IT_HT7 ((uint32_t)0x04000000) 246 #define DMA1_IT_TE7 ((uint32_t)0x08000000) 247 248 #define DMA2_IT_GL1 ((uint32_t)0x10000001) 249 #define DMA2_IT_TC1 ((uint32_t)0x10000002) 250 #define DMA2_IT_HT1 ((uint32_t)0x10000004) 251 #define DMA2_IT_TE1 ((uint32_t)0x10000008) 252 #define DMA2_IT_GL2 ((uint32_t)0x10000010) 253 #define DMA2_IT_TC2 ((uint32_t)0x10000020) 254 #define DMA2_IT_HT2 ((uint32_t)0x10000040) 255 #define DMA2_IT_TE2 ((uint32_t)0x10000080) 256 #define DMA2_IT_GL3 ((uint32_t)0x10000100) 257 #define DMA2_IT_TC3 ((uint32_t)0x10000200) 258 #define DMA2_IT_HT3 ((uint32_t)0x10000400) 259 #define DMA2_IT_TE3 ((uint32_t)0x10000800) 260 #define DMA2_IT_GL4 ((uint32_t)0x10001000) 261 #define DMA2_IT_TC4 ((uint32_t)0x10002000) 262 #define DMA2_IT_HT4 ((uint32_t)0x10004000) 263 #define DMA2_IT_TE4 ((uint32_t)0x10008000) 264 #define DMA2_IT_GL5 ((uint32_t)0x10010000) 265 #define DMA2_IT_TC5 ((uint32_t)0x10020000) 266 #define DMA2_IT_HT5 ((uint32_t)0x10040000) 267 #define DMA2_IT_TE5 ((uint32_t)0x10080000) 268 269 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) 270 271 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ 272 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ 273 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ 274 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ 275 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ 276 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ 277 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ 278 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ 279 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ 280 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ 281 ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ 282 ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ 283 ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ 284 ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ 285 ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ 286 ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ 287 ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ 288 ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ 289 ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ 290 ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ 291 ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ 292 ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ 293 ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ 294 ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) 295 296 /** 297 * @} 298 */ 299 300 /** @defgroup DMA_flags_definition 301 * @{ 302 */ 303 #define DMA1_FLAG_GL1 ((uint32_t)0x00000001) 304 #define DMA1_FLAG_TC1 ((uint32_t)0x00000002) 305 #define DMA1_FLAG_HT1 ((uint32_t)0x00000004) 306 #define DMA1_FLAG_TE1 ((uint32_t)0x00000008) 307 #define DMA1_FLAG_GL2 ((uint32_t)0x00000010) 308 #define DMA1_FLAG_TC2 ((uint32_t)0x00000020) 309 #define DMA1_FLAG_HT2 ((uint32_t)0x00000040) 310 #define DMA1_FLAG_TE2 ((uint32_t)0x00000080) 311 #define DMA1_FLAG_GL3 ((uint32_t)0x00000100) 312 #define DMA1_FLAG_TC3 ((uint32_t)0x00000200) 313 #define DMA1_FLAG_HT3 ((uint32_t)0x00000400) 314 #define DMA1_FLAG_TE3 ((uint32_t)0x00000800) 315 #define DMA1_FLAG_GL4 ((uint32_t)0x00001000) 316 #define DMA1_FLAG_TC4 ((uint32_t)0x00002000) 317 #define DMA1_FLAG_HT4 ((uint32_t)0x00004000) 318 #define DMA1_FLAG_TE4 ((uint32_t)0x00008000) 319 #define DMA1_FLAG_GL5 ((uint32_t)0x00010000) 320 #define DMA1_FLAG_TC5 ((uint32_t)0x00020000) 321 #define DMA1_FLAG_HT5 ((uint32_t)0x00040000) 322 #define DMA1_FLAG_TE5 ((uint32_t)0x00080000) 323 #define DMA1_FLAG_GL6 ((uint32_t)0x00100000) 324 #define DMA1_FLAG_TC6 ((uint32_t)0x00200000) 325 #define DMA1_FLAG_HT6 ((uint32_t)0x00400000) 326 #define DMA1_FLAG_TE6 ((uint32_t)0x00800000) 327 #define DMA1_FLAG_GL7 ((uint32_t)0x01000000) 328 #define DMA1_FLAG_TC7 ((uint32_t)0x02000000) 329 #define DMA1_FLAG_HT7 ((uint32_t)0x04000000) 330 #define DMA1_FLAG_TE7 ((uint32_t)0x08000000) 331 332 #define DMA2_FLAG_GL1 ((uint32_t)0x10000001) 333 #define DMA2_FLAG_TC1 ((uint32_t)0x10000002) 334 #define DMA2_FLAG_HT1 ((uint32_t)0x10000004) 335 #define DMA2_FLAG_TE1 ((uint32_t)0x10000008) 336 #define DMA2_FLAG_GL2 ((uint32_t)0x10000010) 337 #define DMA2_FLAG_TC2 ((uint32_t)0x10000020) 338 #define DMA2_FLAG_HT2 ((uint32_t)0x10000040) 339 #define DMA2_FLAG_TE2 ((uint32_t)0x10000080) 340 #define DMA2_FLAG_GL3 ((uint32_t)0x10000100) 341 #define DMA2_FLAG_TC3 ((uint32_t)0x10000200) 342 #define DMA2_FLAG_HT3 ((uint32_t)0x10000400) 343 #define DMA2_FLAG_TE3 ((uint32_t)0x10000800) 344 #define DMA2_FLAG_GL4 ((uint32_t)0x10001000) 345 #define DMA2_FLAG_TC4 ((uint32_t)0x10002000) 346 #define DMA2_FLAG_HT4 ((uint32_t)0x10004000) 347 #define DMA2_FLAG_TE4 ((uint32_t)0x10008000) 348 #define DMA2_FLAG_GL5 ((uint32_t)0x10010000) 349 #define DMA2_FLAG_TC5 ((uint32_t)0x10020000) 350 #define DMA2_FLAG_HT5 ((uint32_t)0x10040000) 351 #define DMA2_FLAG_TE5 ((uint32_t)0x10080000) 352 353 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) 354 355 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ 356 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ 357 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ 358 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ 359 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ 360 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ 361 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ 362 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ 363 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ 364 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ 365 ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ 366 ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ 367 ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ 368 ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ 369 ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ 370 ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ 371 ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ 372 ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ 373 ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ 374 ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ 375 ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ 376 ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ 377 ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ 378 ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) 379 /** 380 * @} 381 */ 382 383 /** @defgroup DMA_Buffer_Size 384 * @{ 385 */ 386 387 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) 388 389 /** 390 * @} 391 */ 392 393 /** 394 * @} 395 */ 396 397 /** @defgroup DMA_Exported_Macros 398 * @{ 399 */ 400 401 /** 402 * @} 403 */ 404 405 /** @defgroup DMA_Exported_Functions 406 * @{ 407 */ 408 409 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); 410 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); 411 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); 412 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); 413 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); 414 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); 415 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); 416 void DMA_ClearFlag(uint32_t DMA_FLAG); 417 ITStatus DMA_GetITStatus(uint32_t DMA_IT); 418 void DMA_ClearITPendingBit(uint32_t DMA_IT); 419 420 #ifdef __cplusplus 421 } 422 #endif 423 424 #endif /*__STM32F10x_DMA_H */ 425 /** 426 * @} 427 */ 428 429 /** 430 * @} 431 */ 432 433 /** 434 * @} 435 */ 436 437 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ 438