1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_i2s.h 4 * @author MCD Application Team 5 * @brief Header file of I2S HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32H7xx_HAL_I2S_H 22 #define STM32H7xx_HAL_I2S_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h7xx_hal_def.h" 30 31 /** @addtogroup STM32H7xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup I2S 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup I2S_Exported_Types I2S Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief I2S Init structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Mode; /*!< Specifies the I2S operating mode. 50 This parameter can be a value of @ref I2S_Mode */ 51 52 uint32_t Standard; /*!< Specifies the standard used for the I2S communication. 53 This parameter can be a value of @ref I2S_Standard */ 54 55 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. 56 This parameter can be a value of @ref I2S_Data_Format */ 57 58 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. 59 This parameter can be a value of @ref I2S_MCLK_Output */ 60 61 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. 62 This parameter can be a value of @ref I2S_Audio_Frequency */ 63 64 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. 65 This parameter can be a value of @ref I2S_Clock_Polarity */ 66 67 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 68 This parameter can be a value of @ref I2S_MSB_LSB_transmission */ 69 70 uint32_t WSInversion; /*!< Control the Word Select Inversion. 71 This parameter can be a value of @ref I2S_WSInversion */ 72 73 uint32_t Data24BitAlignment; /*!< Specifies the Data Padding for 24 bits data length 74 This parameter can be a value of @ref I2S_Data_24Bit_Alignment */ 75 76 uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state 77 This parameter can be a value of @ref SPI_Master_Keep_IO_State */ 78 79 } I2S_InitTypeDef; 80 81 /** 82 * @brief HAL State structures definition 83 */ 84 typedef enum 85 { 86 HAL_I2S_STATE_RESET = 0x00UL, /*!< I2S not yet initialized or disabled */ 87 HAL_I2S_STATE_READY = 0x01UL, /*!< I2S initialized and ready for use */ 88 HAL_I2S_STATE_BUSY = 0x02UL, /*!< I2S internal process is ongoing */ 89 HAL_I2S_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */ 90 HAL_I2S_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */ 91 HAL_I2S_STATE_TIMEOUT = 0x06UL, /*!< I2S timeout state */ 92 HAL_I2S_STATE_ERROR = 0x07UL /*!< I2S error state */ 93 } HAL_I2S_StateTypeDef; 94 95 /** 96 * @brief I2S handle Structure definition 97 */ 98 typedef struct __I2S_HandleTypeDef 99 { 100 SPI_TypeDef *Instance; /*!< I2S registers base address */ 101 102 I2S_InitTypeDef Init; /*!< I2S communication parameters */ 103 104 uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ 105 106 __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ 107 108 __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */ 109 110 uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */ 111 112 __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */ 113 114 __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter 115 (This field is initialized at the 116 same value as transfer size at the 117 beginning of the transfer and 118 decremented when a sample is received 119 NbSamplesReceived = RxBufferSize-RxBufferCount) */ 120 121 void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */ 122 123 void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */ 124 125 DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ 126 127 DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ 128 129 __IO HAL_LockTypeDef Lock; /*!< I2S locking object */ 130 131 __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */ 132 133 __IO uint32_t ErrorCode; /*!< I2S Error code 134 This parameter can be a value of @ref I2S_Error */ 135 136 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 137 void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */ 138 void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */ 139 void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */ 140 void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */ 141 void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */ 142 void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */ 143 void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */ 144 145 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 146 } I2S_HandleTypeDef; 147 148 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) 149 /** 150 151 * @brief HAL I2S Callback ID enumeration definition 152 */ 153 typedef enum 154 { 155 HAL_I2S_TX_COMPLETE_CB_ID = 0x00UL, /*!< I2S Tx Completed callback ID */ 156 HAL_I2S_RX_COMPLETE_CB_ID = 0x01UL, /*!< I2S Rx Completed callback ID */ 157 HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< I2S Tx Half Completed callback ID */ 158 HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< I2S Rx Half Completed callback ID */ 159 HAL_I2S_ERROR_CB_ID = 0x06UL, /*!< I2S Error callback ID */ 160 HAL_I2S_MSPINIT_CB_ID = 0x07UL, /*!< I2S Msp Init callback ID */ 161 HAL_I2S_MSPDEINIT_CB_ID = 0x08UL /*!< I2S Msp DeInit callback ID */ 162 163 } HAL_I2S_CallbackIDTypeDef; 164 165 /** 166 * @brief HAL I2S Callback pointer definition 167 */ 168 typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */ 169 170 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 171 /** 172 * @} 173 */ 174 175 /* Exported constants --------------------------------------------------------*/ 176 /** @defgroup I2S_Exported_Constants I2S Exported Constants 177 * @{ 178 */ 179 /** @defgroup I2S_Error I2S Error 180 * @{ 181 */ 182 #define HAL_I2S_ERROR_NONE (0x00000000UL) /*!< No error */ 183 #define HAL_I2S_ERROR_TIMEOUT (0x00000001UL) /*!< Timeout error */ 184 #define HAL_I2S_ERROR_OVR (0x00000002UL) /*!< OVR error */ 185 #define HAL_I2S_ERROR_UDR (0x00000004UL) /*!< UDR error */ 186 #define HAL_I2S_ERROR_DMA (0x00000008UL) /*!< DMA transfer error */ 187 #define HAL_I2S_ERROR_PRESCALER (0x00000010UL) /*!< Prescaler Calculation error */ 188 #define HAL_I2S_ERROR_FRE (0x00000020UL) /*!< FRE error */ 189 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) 190 #define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000040UL) /*!< Invalid Callback error */ 191 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 192 /** 193 * @} 194 */ 195 196 /** @defgroup I2S_Mode I2S Mode 197 * @{ 198 */ 199 #define I2S_MODE_SLAVE_TX (0x00000000UL) 200 #define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) 201 #define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) 202 #define I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) 203 #define I2S_MODE_SLAVE_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2) 204 #define I2S_MODE_MASTER_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0) 205 /** 206 * @} 207 */ 208 209 /** @defgroup I2S_Standard I2S Standard 210 * @{ 211 */ 212 #define I2S_STANDARD_PHILIPS (0x00000000UL) 213 #define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) 214 #define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) 215 #define I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) 216 #define I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) 217 /** 218 * @} 219 */ 220 221 /** @defgroup I2S_Data_Format I2S Data Format 222 * @{ 223 */ 224 #define I2S_DATAFORMAT_16B (0x00000000UL) 225 #define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) 226 #define I2S_DATAFORMAT_24B (SPI_I2SCFGR_DATLEN_0) 227 #define I2S_DATAFORMAT_32B (SPI_I2SCFGR_DATLEN_1) 228 /** 229 * @} 230 */ 231 232 /** @defgroup I2S_MCLK_Output I2S MCLK Output 233 * @{ 234 */ 235 #define I2S_MCLKOUTPUT_ENABLE (SPI_I2SCFGR_MCKOE) 236 #define I2S_MCLKOUTPUT_DISABLE (0x00000000UL) 237 /** 238 * @} 239 */ 240 241 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency 242 * @{ 243 */ 244 #define I2S_AUDIOFREQ_192K (192000UL) 245 #define I2S_AUDIOFREQ_96K (96000UL) 246 #define I2S_AUDIOFREQ_48K (48000UL) 247 #define I2S_AUDIOFREQ_44K (44100UL) 248 #define I2S_AUDIOFREQ_32K (32000UL) 249 #define I2S_AUDIOFREQ_22K (22050UL) 250 #define I2S_AUDIOFREQ_16K (16000UL) 251 #define I2S_AUDIOFREQ_11K (11025UL) 252 #define I2S_AUDIOFREQ_8K (8000UL) 253 #define I2S_AUDIOFREQ_DEFAULT (2UL) 254 /** 255 * @} 256 */ 257 258 /** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode 259 * @{ 260 */ 261 #define I2S_CPOL_LOW (0x00000000UL) 262 #define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL) 263 /** 264 * @} 265 */ 266 267 /** @defgroup I2S_MSB_LSB_Transmission I2S MSB LSB Transmission 268 * @{ 269 */ 270 #define I2S_FIRSTBIT_MSB (0x00000000UL) 271 #define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST 272 /** 273 * @} 274 */ 275 276 /** @defgroup I2S_WSInversion I2S Word Select Inversion 277 * @{ 278 */ 279 #define I2S_WS_INVERSION_DISABLE (0x00000000UL) 280 #define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV 281 /** 282 * @} 283 */ 284 285 /** @defgroup I2S_Data_24Bit_Alignment Data Padding 24Bit 286 * @{ 287 */ 288 #define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000UL) 289 #define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT 290 /** 291 * @} 292 */ 293 294 /** @defgroup I2S_Master_Keep_IO_State Keep IO State 295 * @{ 296 */ 297 #define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U) 298 #define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR 299 /** 300 * @} 301 */ 302 303 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition 304 * @{ 305 */ 306 #define I2S_IT_RXP SPI_IER_RXPIE 307 #define I2S_IT_TXP SPI_IER_TXPIE 308 #define I2S_IT_UDR SPI_IER_UDRIE 309 #define I2S_IT_OVR SPI_IER_OVRIE 310 #define I2S_IT_FRE SPI_IER_TIFREIE 311 #define I2S_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE) 312 /** 313 * @} 314 */ 315 316 /** @defgroup I2S_Flags_Definition I2S Flags Definition 317 * @{ 318 */ 319 #define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */ 320 #define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */ 321 #define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */ 322 #define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */ 323 #define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */ 324 325 #define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE) 326 /** 327 * @} 328 */ 329 330 /** 331 * @} 332 */ 333 334 /* Exported macros -----------------------------------------------------------*/ 335 /** @defgroup I2S_Exported_macros I2S Exported Macros 336 * @{ 337 */ 338 339 /** @brief Reset I2S handle state 340 * @param __HANDLE__ specifies the I2S Handle. 341 * @retval None 342 */ 343 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) 344 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \ 345 (__HANDLE__)->State = HAL_I2S_STATE_RESET; \ 346 (__HANDLE__)->MspInitCallback = NULL; \ 347 (__HANDLE__)->MspDeInitCallback = NULL; \ 348 } while(0) 349 #else 350 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) 351 #endif 352 353 /** @brief Enable the specified SPI peripheral (in I2S mode). 354 * @param __HANDLE__ specifies the I2S Handle. 355 * @retval None 356 */ 357 #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)) 358 359 /** @brief Disable the specified SPI peripheral (in I2S mode). 360 * @param __HANDLE__ specifies the I2S Handle. 361 * @retval None 362 */ 363 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)) 364 365 /** @brief Enable the specified I2S interrupts. 366 * @param __HANDLE__ specifies the I2S Handle. 367 * This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral. 368 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 369 * This parameter can be one of the following values: 370 * @arg I2S_IT_RXP : Rx-Packet available interrupt 371 * @arg I2S_IT_TXP : Tx-Packet space available interrupt 372 * @arg I2S_IT_UDR : Underrun interrupt 373 * @arg I2S_IT_OVR : Overrun interrupt 374 * @arg I2S_IT_FRE : TI mode frame format error interrupt 375 * @arg I2S_IT_ERR : Error interrupt enable 376 * @retval None 377 */ 378 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__))) 379 380 /** @brief Disable the specified I2S interrupts. 381 * @param __HANDLE__ specifies the I2S Handle. 382 * This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral. 383 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 384 * This parameter can be one of the following values: 385 * @arg I2S_IT_RXP : Rx-Packet available interrupt 386 * @arg I2S_IT_TXP : Tx-Packet space available interrupt 387 * @arg I2S_IT_UDR : Underrun interrupt 388 * @arg I2S_IT_OVR : Overrun interrupt 389 * @arg I2S_IT_FRE : TI mode frame format error interrupt 390 * @arg I2S_IT_ERR : Error interrupt enable 391 * @retval None 392 */ 393 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__))) 394 395 /** @brief Check if the specified I2S interrupt source is enabled or disabled. 396 * @param __HANDLE__ specifies the I2S Handle. 397 * This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral. 398 * @param __INTERRUPT__ specifies the I2S interrupt source to check. 399 * This parameter can be one of the following values: 400 * @arg I2S_IT_RXP : Rx-Packet available interrupt 401 * @arg I2S_IT_TXP : Tx-Packet space available interrupt 402 * @arg I2S_IT_UDR : Underrun interrupt 403 * @arg I2S_IT_OVR : Overrun interrupt 404 * @arg I2S_IT_FRE : TI mode frame format error interrupt 405 * @arg I2S_IT_ERR : Error interrupt enable 406 * @retval The new state of __IT__ (TRUE or FALSE). 407 */ 408 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 409 410 /** @brief Check whether the specified I2S flag is set or not. 411 * @param __HANDLE__ specifies the I2S Handle. 412 * This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral. 413 * @param __FLAG__ specifies the flag to check. 414 * This parameter can be one of the following values: 415 * @arg I2S_FLAG_RXP : Rx-Packet available flag 416 * @arg I2S_FLAG_TXP : Tx-Packet space available flag 417 * @arg I2S_FLAG_UDR : Underrun flag 418 * @arg I2S_FLAG_OVR : Overrun flag 419 * @arg I2S_FLAG_FRE : TI mode frame format error flag 420 * @retval The new state of __FLAG__ (TRUE or FALSE). 421 */ 422 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 423 424 /** @brief Clear the I2S OVR pending flag. 425 * @param __HANDLE__ specifies the I2S Handle. 426 * @retval None 427 */ 428 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC) 429 430 /** @brief Clear the I2S UDR pending flag. 431 * @param __HANDLE__ specifies the I2S Handle. 432 * @retval None 433 */ 434 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC) 435 436 /** @brief Clear the I2S FRE pending flag. 437 * @param __HANDLE__: specifies the I2S Handle. 438 * @retval None 439 */ 440 #define __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC) 441 442 /** 443 * @} 444 */ 445 446 /* Exported functions --------------------------------------------------------*/ 447 /** @addtogroup I2S_Exported_Functions 448 * @{ 449 */ 450 451 /** @addtogroup I2S_Exported_Functions_Group1 452 * @{ 453 */ 454 /* Initialization/de-initialization functions ********************************/ 455 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); 456 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s); 457 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); 458 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); 459 460 /* Callbacks Register/UnRegister functions ***********************************/ 461 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) 462 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback); 463 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); 464 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 465 /** 466 * @} 467 */ 468 469 /** @addtogroup I2S_Exported_Functions_Group2 470 * @{ 471 */ 472 /* I/O operation functions ***************************************************/ 473 /* Blocking mode: Polling */ 474 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); 475 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); 476 477 /* Non-Blocking mode: Interrupt */ 478 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 479 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 480 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); 481 482 /* Non-Blocking mode: DMA */ 483 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 484 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 485 486 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); 487 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); 488 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); 489 490 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ 491 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); 492 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); 493 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); 494 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); 495 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); 496 /** 497 * @} 498 */ 499 500 /** @addtogroup I2S_Exported_Functions_Group3 501 * @{ 502 */ 503 /* Peripheral Control and State functions ************************************/ 504 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); 505 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); 506 /** 507 * @} 508 */ 509 510 /** 511 * @} 512 */ 513 514 /* Private types -------------------------------------------------------------*/ 515 /* Private variables ---------------------------------------------------------*/ 516 /* Private constants ---------------------------------------------------------*/ 517 /** @defgroup I2S_Private_Constants I2S Private Constants 518 * @{ 519 */ 520 521 /** 522 * @} 523 */ 524 525 /* Private macros ------------------------------------------------------------*/ 526 /** @defgroup I2S_Private_Macros I2S Private Macros 527 * @{ 528 */ 529 530 /** @brief Check whether the specified SPI flag is set or not. 531 * @param __SR__ copy of I2S SR register. 532 * @param __FLAG__ specifies the flag to check. 533 * This parameter can be one of the following values: 534 * @arg I2S_FLAG_RXP : Rx-Packet available flag 535 * @arg I2S_FLAG_TXP : Tx-Packet space available flag 536 * @arg I2S_FLAG_UDR : Underrun flag 537 * @arg I2S_FLAG_OVR : Overrun flag 538 * @arg I2S_FLAG_FRE : TI mode frame format error flag 539 * @retval SET or RESET. 540 */ 541 #define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) 542 543 /** @brief Check whether the specified SPI Interrupt is set or not. 544 * @param __IER__ copy of I2S IER register. 545 * @param __INTERRUPT__ specifies the SPI interrupt source to check. 546 * This parameter can be one of the following values: 547 * @arg I2S_IT_RXP : Rx-Packet available interrupt 548 * @arg I2S_IT_TXP : Tx-Packet space available interrupt 549 * @arg I2S_IT_UDR : Underrun interrupt 550 * @arg I2S_IT_OVR : Overrun interrupt 551 * @arg I2S_IT_FRE : TI mode frame format error interrupt 552 * @arg I2S_IT_ERR : Error interrupt enable 553 * @retval SET or RESET. 554 */ 555 #define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 556 557 /** @brief Checks if I2S Mode parameter is in allowed range. 558 * @param __MODE__ specifies the I2S Mode. 559 * This parameter can be a value of @ref I2S_Mode 560 * @retval None 561 */ 562 #define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ 563 ((__MODE__) == I2S_MODE_SLAVE_RX) || \ 564 ((__MODE__) == I2S_MODE_MASTER_TX) || \ 565 ((__MODE__) == I2S_MODE_MASTER_RX) || \ 566 ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX) || \ 567 ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX)) 568 569 #define IS_I2S_MASTER(__MODE__) (((__MODE__) == I2S_MODE_MASTER_TX) || \ 570 ((__MODE__) == I2S_MODE_MASTER_RX) || \ 571 ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX)) 572 573 #define IS_I2S_SLAVE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ 574 ((__MODE__) == I2S_MODE_SLAVE_RX) || \ 575 ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX)) 576 577 #define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ 578 ((__STANDARD__) == I2S_STANDARD_MSB) || \ 579 ((__STANDARD__) == I2S_STANDARD_LSB) || \ 580 ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ 581 ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) 582 583 #define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \ 584 ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ 585 ((__FORMAT__) == I2S_DATAFORMAT_24B) || \ 586 ((__FORMAT__) == I2S_DATAFORMAT_32B)) 587 588 #define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ 589 ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) 590 591 #define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ 592 ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ 593 ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) 594 595 #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ 596 ((__CPOL__) == I2S_CPOL_HIGH)) 597 598 #define IS_I2S_FIRST_BIT(__BIT__) (((__BIT__) == I2S_FIRSTBIT_MSB) || \ 599 ((__BIT__) == I2S_FIRSTBIT_LSB)) 600 601 #define IS_I2S_WS_INVERSION(__WSINV__) (((__WSINV__) == I2S_WS_INVERSION_DISABLE) || \ 602 ((__WSINV__) == I2S_WS_INVERSION_ENABLE)) 603 604 #define IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \ 605 ((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_LEFT)) 606 607 #define IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__) (((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \ 608 ((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_ENABLE)) 609 610 611 /** 612 * @} 613 */ 614 615 /** 616 * @} 617 */ 618 619 /** 620 * @} 621 */ 622 623 #ifdef __cplusplus 624 } 625 #endif 626 627 #endif /* STM32H7xx_HAL_I2S_H */ 628 629 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 630