1 /**
2 ******************************************************************************
3 * @file stm32f30x_spi.c
4 * @author MCD Application Team
5 * @version V1.2.3
6 * @date 10-July-2015
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Serial peripheral interface (SPI):
9 * + Initialization and Configuration
10 * + Data transfers functions
11 * + Hardware CRC Calculation
12 * + DMA transfers management
13 * + Interrupts and flags management
14 *
15 * @verbatim
16
17
18 ===============================================================================
19 ##### How to use this driver #####
20 ===============================================================================
21 [..]
22 (#) Enable peripheral clock using RCC_APBPeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)
23 function for SPI1 or using RCC_APBPeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)
24 function for SPI2.
25 (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHBPeriphClockCmd()
26 function.
27 (#) Peripherals alternate function:
28 (++) Connect the pin to the desired peripherals' Alternate
29 Function (AF) using GPIO_PinAFConfig() function.
30 (++) Configure the desired pin in alternate function by:
31 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
32 (++) Select the type, pull-up/pull-down and output speed via
33 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
34 (++) Call GPIO_Init() function.
35 (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
36 Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
37 function in SPI mode. In I2S mode, program the Mode, Standard, Data Format,
38 MCLK Output, Audio frequency and Polarity using I2S_Init() function.
39 (#) Configure the FIFO threshold using SPI_RxFIFOThresholdConfig() to select
40 at which threshold the RXNE event is generated.
41 (#) Enable the NVIC and the corresponding interrupt using the function
42 SPI_I2S_ITConfig() if you need to use interrupt mode.
43 (#) When using the DMA mode
44 (++) Configure the DMA using DMA_Init() function.
45 (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
46 (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
47 I2S_Cmd().
48 (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.
49 (#) Optionally you can enable/configure the following parameters without
50 re-initialization (i.e there is no need to call again SPI_Init() function):
51 (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
52 is programmed as Data direction parameter using the SPI_Init() function
53 it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
54 using the SPI_BiDirectionalLineConfig() function.
55 (++) When SPI_NSS_Soft is selected as Slave Select Management parameter
56 using the SPI_Init() function it can be possible to manage the
57 NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
58 (++) Reconfigure the data size using the SPI_DataSizeConfig() function.
59 (++) Enable or disable the SS output using the SPI_SSOutputCmd() function.
60 (#) To use the CRC Hardware calculation feature refer to the Peripheral
61 CRC hardware Calculation subsection.
62 [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI
63 peripheral is able to manage sending and receiving data simultaneously
64 using two data lines. Each SPI peripheral has an extended block called I2Sxext
65 (ie. I2S2ext for SPI2 and I2S3ext for SPI3).
66 The extension block is not a full SPI IP, it is used only as I2S slave to
67 implement full duplex mode. The extension block uses the same clock sources
68 as its master.
69 To configure I2S full duplex you have to:
70 (#) Configure SPIx in I2S mode (I2S_Init() function) as described above.
71 (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to
72 I2S_Init() function.
73 (#) Call I2S_Cmd() for SPIx then for its extended block.
74 (#) Configure interrupts or DMA requests and to get/clear flag status,
75 use I2Sxext instance for the extension block.
76 [..] Functions that can be called with I2Sxext instances are:
77 I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData16(), SPI_I2S_SendData16(),
78 SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(),
79 SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().
80 [..] Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
81 [..] RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
82 I2S_StructInit(&I2SInitStruct);
83 I2SInitStruct.Mode = I2S_Mode_MasterTx;
84 I2S_Init(SPI3, &I2SInitStruct);
85 I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)
86 I2S_Cmd(SPI3, ENABLE);
87 I2S_Cmd(SPI3ext, ENABLE);
88 ...
89 while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
90 {}
91 SPI_I2S_SendData16(SPI3, txdata[i]);
92 ...
93 while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)
94 {}
95 rxdata[i] = SPI_I2S_ReceiveData16(I2S3ext);
96 ...
97 [..]
98 (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd()
99 just after calling the function SPI_Init().
100
101 @endverbatim
102 ******************************************************************************
103 * @attention
104 *
105 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
106 *
107 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
108 * You may not use this file except in compliance with the License.
109 * You may obtain a copy of the License at:
110 *
111 * http://www.st.com/software_license_agreement_liberty_v2
112 *
113 * Unless required by applicable law or agreed to in writing, software
114 * distributed under the License is distributed on an "AS IS" BASIS,
115 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
116 * See the License for the specific language governing permissions and
117 * limitations under the License.
118 *
119 ******************************************************************************
120 */
121
122 /* Includes ------------------------------------------------------------------*/
123 #include "stm32f30x_spi.h"
124 #include "stm32f30x_rcc.h"
125
126 /** @addtogroup STM32F30x_StdPeriph_Driver
127 * @{
128 */
129
130 /** @defgroup SPI
131 * @brief SPI driver modules
132 * @{
133 */
134
135 /* Private typedef -----------------------------------------------------------*/
136 /* Private define ------------------------------------------------------------*/
137 /* SPI registers Masks */
138 #define CR1_CLEAR_MASK ((uint16_t)0x3040)
139 #define CR2_LDMA_MASK ((uint16_t)0x9FFF)
140
141 #define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040)
142
143 /* Private macro -------------------------------------------------------------*/
144 /* Private variables ---------------------------------------------------------*/
145 /* Private function prototypes -----------------------------------------------*/
146 /* Private functions ---------------------------------------------------------*/
147
148 /** @defgroup SPI_Private_Functions
149 * @{
150 */
151
152 /** @defgroup SPI_Group1 Initialization and Configuration functions
153 * @brief Initialization and Configuration functions
154 *
155 @verbatim
156 ===============================================================================
157 ##### Initialization and Configuration functions #####
158 ===============================================================================
159 [..] This section provides a set of functions allowing to initialize the SPI Direction,
160 SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
161 Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
162 [..] The SPI_Init() function follows the SPI configuration procedures for Master mode
163 and Slave mode (details for these procedures are available in reference manual).
164 [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected,
165 use the following function to manage the NSS bit:
166 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
167 [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard)
168 is selected, use the following function to enable the NSS output feature.
169 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
170 [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the
171 following function: void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
172 And it can be managed by software in the SPI Motorola mode using this function:
173 void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
174 [..] This section provides also functions to initialize the I2S Mode, Standard,
175 Data Format, MCLK Output, Audio frequency and Polarity.
176 [..] The I2S_Init() function follows the I2S configuration procedures for Master mode
177 and Slave mode.
178
179 @endverbatim
180 * @{
181 */
182
183 /**
184 * @brief Deinitializes the SPIx peripheral registers to their default
185 * reset values.
186 * @param SPIx: To select the SPIx peripheral, where x can be: 1, 2 or 3
187 * in SPI mode.
188 * @retval None
189 */
SPI_I2S_DeInit(SPI_TypeDef * SPIx)190 void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
191 {
192 /* Check the parameters */
193 assert_param(IS_SPI_ALL_PERIPH(SPIx));
194
195 if (SPIx == SPI1)
196 {
197 /* Enable SPI1 reset state */
198 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
199 /* Release SPI1 from reset state */
200 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
201 }
202 else if (SPIx == SPI2)
203 {
204 /* Enable SPI2 reset state */
205 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
206 /* Release SPI2 from reset state */
207 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
208 }
209 else if (SPIx == SPI3)
210 {
211 /* Enable SPI3 reset state */
212 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
213 /* Release SPI3 from reset state */
214 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
215 }
216 else
217 {
218 if (SPIx == SPI4)
219 {
220 /* Enable SPI4 reset state */
221 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE);
222 /* Release SPI4 from reset state */
223 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, DISABLE);
224 }
225 }
226 }
227
228 /**
229 * @brief Fills each SPI_InitStruct member with its default value.
230 * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
231 * @retval None
232 */
SPI_StructInit(SPI_InitTypeDef * SPI_InitStruct)233 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
234 {
235 /*--------------- Reset SPI init structure parameters values -----------------*/
236 /* Initialize the SPI_Direction member */
237 SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
238 /* Initialize the SPI_Mode member */
239 SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
240 /* Initialize the SPI_DataSize member */
241 SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
242 /* Initialize the SPI_CPOL member */
243 SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
244 /* Initialize the SPI_CPHA member */
245 SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
246 /* Initialize the SPI_NSS member */
247 SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
248 /* Initialize the SPI_BaudRatePrescaler member */
249 SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
250 /* Initialize the SPI_FirstBit member */
251 SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
252 /* Initialize the SPI_CRCPolynomial member */
253 SPI_InitStruct->SPI_CRCPolynomial = 7;
254 }
255
256 /**
257 * @brief Initializes the SPIx peripheral according to the specified
258 * parameters in the SPI_InitStruct.
259 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
260 * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
261 * contains the configuration information for the specified SPI peripheral.
262 * @retval None
263 */
SPI_Init(SPI_TypeDef * SPIx,SPI_InitTypeDef * SPI_InitStruct)264 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
265 {
266 uint16_t tmpreg = 0;
267
268 /* check the parameters */
269 assert_param(IS_SPI_ALL_PERIPH(SPIx));
270
271 /* Check the SPI parameters */
272 assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
273 assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
274 assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize));
275 assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
276 assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
277 assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
278 assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
279 assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
280 assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
281
282 /* Configuring the SPI in master mode */
283 if(SPI_InitStruct->SPI_Mode == SPI_Mode_Master)
284 {
285 /*---------------------------- SPIx CR1 Configuration ------------------------*/
286 /* Get the SPIx CR1 value */
287 tmpreg = SPIx->CR1;
288 /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
289 tmpreg &= CR1_CLEAR_MASK;
290 /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
291 master/slave mode, CPOL and CPHA */
292 /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
293 /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
294 /* Set LSBFirst bit according to SPI_FirstBit value */
295 /* Set BR bits according to SPI_BaudRatePrescaler value */
296 /* Set CPOL bit according to SPI_CPOL value */
297 /* Set CPHA bit according to SPI_CPHA value */
298 tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) |
299 (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) |
300 (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) |
301 SPI_InitStruct->SPI_FirstBit)));
302 /* Write to SPIx CR1 */
303 SPIx->CR1 = tmpreg;
304 /*-------------------------Data Size Configuration -----------------------*/
305 /* Get the SPIx CR2 value */
306 tmpreg = SPIx->CR2;
307 /* Clear DS[3:0] bits */
308 tmpreg &= (uint16_t)~SPI_CR2_DS;
309 /* Configure SPIx: Data Size */
310 tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
311 /* Write to SPIx CR2 */
312 SPIx->CR2 = tmpreg;
313 }
314 /* Configuring the SPI in slave mode */
315 else
316 {
317 /*---------------------------- Data size Configuration -----------------------*/
318 /* Get the SPIx CR2 value */
319 tmpreg = SPIx->CR2;
320 /* Clear DS[3:0] bits */
321 tmpreg &= (uint16_t)~SPI_CR2_DS;
322 /* Configure SPIx: Data Size */
323 tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
324 /* Write to SPIx CR2 */
325 SPIx->CR2 = tmpreg;
326 /*---------------------------- SPIx CR1 Configuration ------------------------*/
327 /* Get the SPIx CR1 value */
328 tmpreg = SPIx->CR1;
329 /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
330 tmpreg &= CR1_CLEAR_MASK;
331 /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
332 master/salve mode, CPOL and CPHA */
333 /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
334 /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
335 /* Set LSBFirst bit according to SPI_FirstBit value */
336 /* Set BR bits according to SPI_BaudRatePrescaler value */
337 /* Set CPOL bit according to SPI_CPOL value */
338 /* Set CPHA bit according to SPI_CPHA value */
339 tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) |
340 (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) |
341 (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) |
342 SPI_InitStruct->SPI_FirstBit)));
343
344 /* Write to SPIx CR1 */
345 SPIx->CR1 = tmpreg;
346 }
347
348 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
349 SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
350
351 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
352 /* Write to SPIx CRCPOLY */
353 SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
354 }
355
356 /**
357 * @brief Fills each I2S_InitStruct member with its default value.
358 * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
359 * @retval None
360 */
I2S_StructInit(I2S_InitTypeDef * I2S_InitStruct)361 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
362 {
363 /*--------------- Reset I2S init structure parameters values -----------------*/
364 /* Initialize the I2S_Mode member */
365 I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
366
367 /* Initialize the I2S_Standard member */
368 I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
369
370 /* Initialize the I2S_DataFormat member */
371 I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
372
373 /* Initialize the I2S_MCLKOutput member */
374 I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
375
376 /* Initialize the I2S_AudioFreq member */
377 I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
378
379 /* Initialize the I2S_CPOL member */
380 I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
381 }
382
383 /**
384 * @brief Initializes the SPIx peripheral according to the specified
385 * parameters in the I2S_InitStruct.
386 * @param SPIx:To select the SPIx peripheral, where x can be: 2 or 3
387 * in I2S mode.
388 * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
389 * contains the configuration information for the specified SPI peripheral
390 * configured in I2S mode.
391 * @note
392 * The function calculates the optimal prescaler needed to obtain the most
393 * accurate audio frequency (depending on the I2S clock source, the PLL values
394 * and the product configuration). But in case the prescaler value is greater
395 * than 511, the default value (0x02) will be configured instead.
396 * @retval None
397 */
I2S_Init(SPI_TypeDef * SPIx,I2S_InitTypeDef * I2S_InitStruct)398 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
399 {
400 uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
401 uint32_t tmp = 0;
402 RCC_ClocksTypeDef RCC_Clocks;
403 uint32_t sourceclock = 0;
404
405 /* Check the I2S parameters */
406 assert_param(IS_SPI_23_PERIPH(SPIx));
407 assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
408 assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
409 assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
410 assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
411 assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
412 assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
413
414 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
415 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
416 SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK;
417 SPIx->I2SPR = 0x0002;
418
419 /* Get the I2SCFGR register value */
420 tmpreg = SPIx->I2SCFGR;
421
422 /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
423 if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
424 {
425 i2sodd = (uint16_t)0;
426 i2sdiv = (uint16_t)2;
427 }
428 /* If the requested audio frequency is not the default, compute the prescaler */
429 else
430 {
431 /* Check the frame length (For the Prescaler computing) */
432 if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
433 {
434 /* Packet length is 16 bits */
435 packetlength = 1;
436 }
437 else
438 {
439 /* Packet length is 32 bits */
440 packetlength = 2;
441 }
442
443 /* I2S Clock source is System clock: Get System Clock frequency */
444 RCC_GetClocksFreq(&RCC_Clocks);
445
446 /* Get the source clock value: based on System Clock value */
447 sourceclock = RCC_Clocks.SYSCLK_Frequency;
448
449 /* Compute the Real divider depending on the MCLK output state with a floating point */
450 if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
451 {
452 /* MCLK output is enabled */
453 tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
454 }
455 else
456 {
457 /* MCLK output is disabled */
458 tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
459 }
460
461 /* Remove the floating point */
462 tmp = tmp / 10;
463
464 /* Check the parity of the divider */
465 i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
466
467 /* Compute the i2sdiv prescaler */
468 i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
469
470 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
471 i2sodd = (uint16_t) (i2sodd << 8);
472 }
473
474 /* Test if the divider is 1 or 0 or greater than 0xFF */
475 if ((i2sdiv < 2) || (i2sdiv > 0xFF))
476 {
477 /* Set the default values */
478 i2sdiv = 2;
479 i2sodd = 0;
480 }
481
482 /* Write to SPIx I2SPR register the computed value */
483 SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
484
485 /* Configure the I2S with the SPI_InitStruct values */
486 tmpreg |= (uint16_t)((uint16_t)(SPI_I2SCFGR_I2SMOD | I2S_InitStruct->I2S_Mode) | \
487 (uint16_t)((uint16_t)((uint16_t)(I2S_InitStruct->I2S_Standard |I2S_InitStruct->I2S_DataFormat) |\
488 I2S_InitStruct->I2S_CPOL)));
489
490 /* Write to SPIx I2SCFGR */
491 SPIx->I2SCFGR = tmpreg;
492 }
493
494 /**
495 * @brief Enables or disables the specified SPI peripheral.
496 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
497 * @param NewState: new state of the SPIx peripheral.
498 * This parameter can be: ENABLE or DISABLE.
499 * @retval None
500 */
SPI_Cmd(SPI_TypeDef * SPIx,FunctionalState NewState)501 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
502 {
503 /* Check the parameters */
504 assert_param(IS_SPI_ALL_PERIPH(SPIx));
505 assert_param(IS_FUNCTIONAL_STATE(NewState));
506
507 if (NewState != DISABLE)
508 {
509 /* Enable the selected SPI peripheral */
510 SPIx->CR1 |= SPI_CR1_SPE;
511 }
512 else
513 {
514 /* Disable the selected SPI peripheral */
515 SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
516 }
517 }
518
519 /**
520 * @brief Enables or disables the TI Mode.
521 * @note This function can be called only after the SPI_Init() function has
522 * been called.
523 * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
524 * are not taken into consideration and are configured by hardware
525 * respectively to the TI mode requirements.
526 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
527 * @param NewState: new state of the selected SPI TI communication mode.
528 * This parameter can be: ENABLE or DISABLE.
529 * @retval None
530 */
SPI_TIModeCmd(SPI_TypeDef * SPIx,FunctionalState NewState)531 void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
532 {
533 /* Check the parameters */
534 assert_param(IS_SPI_ALL_PERIPH(SPIx));
535 assert_param(IS_FUNCTIONAL_STATE(NewState));
536
537 if (NewState != DISABLE)
538 {
539 /* Enable the TI mode for the selected SPI peripheral */
540 SPIx->CR2 |= SPI_CR2_FRF;
541 }
542 else
543 {
544 /* Disable the TI mode for the selected SPI peripheral */
545 SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);
546 }
547 }
548
549 /**
550 * @brief Enables or disables the specified SPI peripheral (in I2S mode).
551 * @param SPIx:To select the SPIx peripheral, where x can be: 2 or 3 in
552 * I2S mode or I2Sxext for I2S full duplex mode.
553 * @param NewState: new state of the SPIx peripheral.
554 * This parameter can be: ENABLE or DISABLE.
555 * @retval None
556 */
I2S_Cmd(SPI_TypeDef * SPIx,FunctionalState NewState)557 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
558 {
559 /* Check the parameters */
560 assert_param(IS_SPI_23_PERIPH_EXT(SPIx));
561 assert_param(IS_FUNCTIONAL_STATE(NewState));
562 if (NewState != DISABLE)
563 {
564 /* Enable the selected SPI peripheral in I2S mode */
565 SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
566 }
567 else
568 {
569 /* Disable the selected SPI peripheral in I2S mode */
570 SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
571 }
572 }
573
574 /**
575 * @brief Configures the data size for the selected SPI.
576 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
577 * @param SPI_DataSize: specifies the SPI data size.
578 * For the SPIx peripheral this parameter can be one of the following values:
579 * @arg SPI_DataSize_4b: Set data size to 4 bits
580 * @arg SPI_DataSize_5b: Set data size to 5 bits
581 * @arg SPI_DataSize_6b: Set data size to 6 bits
582 * @arg SPI_DataSize_7b: Set data size to 7 bits
583 * @arg SPI_DataSize_8b: Set data size to 8 bits
584 * @arg SPI_DataSize_9b: Set data size to 9 bits
585 * @arg SPI_DataSize_10b: Set data size to 10 bits
586 * @arg SPI_DataSize_11b: Set data size to 11 bits
587 * @arg SPI_DataSize_12b: Set data size to 12 bits
588 * @arg SPI_DataSize_13b: Set data size to 13 bits
589 * @arg SPI_DataSize_14b: Set data size to 14 bits
590 * @arg SPI_DataSize_15b: Set data size to 15 bits
591 * @arg SPI_DataSize_16b: Set data size to 16 bits
592 * @retval None
593 */
SPI_DataSizeConfig(SPI_TypeDef * SPIx,uint16_t SPI_DataSize)594 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
595 {
596 uint16_t tmpreg = 0;
597
598 /* Check the parameters */
599 assert_param(IS_SPI_ALL_PERIPH(SPIx));
600 assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));
601 /* Read the CR2 register */
602 tmpreg = SPIx->CR2;
603 /* Clear DS[3:0] bits */
604 tmpreg &= (uint16_t)~SPI_CR2_DS;
605 /* Set new DS[3:0] bits value */
606 tmpreg |= SPI_DataSize;
607 SPIx->CR2 = tmpreg;
608 }
609
610 /**
611 * @brief Configures the FIFO reception threshold for the selected SPI.
612 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
613 * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold.
614 * This parameter can be one of the following values:
615 * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO
616 * level is greater or equal to 1/2.
617 * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO
618 * level is greater or equal to 1/4.
619 * @retval None
620 */
SPI_RxFIFOThresholdConfig(SPI_TypeDef * SPIx,uint16_t SPI_RxFIFOThreshold)621 void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)
622 {
623 /* Check the parameters */
624 assert_param(IS_SPI_ALL_PERIPH(SPIx));
625 assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));
626
627 /* Clear FRXTH bit */
628 SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);
629
630 /* Set new FRXTH bit value */
631 SPIx->CR2 |= SPI_RxFIFOThreshold;
632 }
633
634 /**
635 * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
636 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
637 * @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
638 * This parameter can be one of the following values:
639 * @arg SPI_Direction_Tx: Selects Tx transmission direction
640 * @arg SPI_Direction_Rx: Selects Rx receive direction
641 * @retval None
642 */
SPI_BiDirectionalLineConfig(SPI_TypeDef * SPIx,uint16_t SPI_Direction)643 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
644 {
645 /* Check the parameters */
646 assert_param(IS_SPI_ALL_PERIPH(SPIx));
647 assert_param(IS_SPI_DIRECTION(SPI_Direction));
648 if (SPI_Direction == SPI_Direction_Tx)
649 {
650 /* Set the Tx only mode */
651 SPIx->CR1 |= SPI_Direction_Tx;
652 }
653 else
654 {
655 /* Set the Rx only mode */
656 SPIx->CR1 &= SPI_Direction_Rx;
657 }
658 }
659
660 /**
661 * @brief Configures internally by software the NSS pin for the selected SPI.
662 * @note This function can be called only after the SPI_Init() function has
663 * been called.
664 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
665 * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
666 * This parameter can be one of the following values:
667 * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
668 * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
669 * @retval None
670 */
SPI_NSSInternalSoftwareConfig(SPI_TypeDef * SPIx,uint16_t SPI_NSSInternalSoft)671 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
672 {
673 /* Check the parameters */
674 assert_param(IS_SPI_ALL_PERIPH(SPIx));
675 assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
676
677 if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
678 {
679 /* Set NSS pin internally by software */
680 SPIx->CR1 |= SPI_NSSInternalSoft_Set;
681 }
682 else
683 {
684 /* Reset NSS pin internally by software */
685 SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
686 }
687 }
688
689 /**
690 * @brief Configures the full duplex mode for the I2Sx peripheral using its
691 * extension I2Sxext according to the specified parameters in the
692 * I2S_InitStruct.
693 * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block.
694 * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
695 * contains the configuration information for the specified I2S peripheral
696 * extension.
697 *
698 * @note The structure pointed by I2S_InitStruct parameter should be the same
699 * used for the master I2S peripheral. In this case, if the master is
700 * configured as transmitter, the slave will be receiver and vice versa.
701 * Or you can force a different mode by modifying the field I2S_Mode to the
702 * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration.
703 *
704 * @note The I2S full duplex extension can be configured in slave mode only.
705 *
706 * @retval None
707 */
I2S_FullDuplexConfig(SPI_TypeDef * I2Sxext,I2S_InitTypeDef * I2S_InitStruct)708 void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
709 {
710 uint16_t tmpreg = 0, tmp = 0;
711
712 /* Check the I2S parameters */
713 assert_param(IS_I2S_EXT_PERIPH(I2Sxext));
714 assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
715 assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
716 assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
717 assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
718
719 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
720 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
721 I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK;
722 I2Sxext->I2SPR = 0x0002;
723
724 /* Get the I2SCFGR register value */
725 tmpreg = I2Sxext->I2SCFGR;
726
727 /* Get the mode to be configured for the extended I2S */
728 if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
729 {
730 tmp = I2S_Mode_SlaveRx;
731 }
732 else
733 {
734 if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
735 {
736 tmp = I2S_Mode_SlaveTx;
737 }
738 }
739
740
741 /* Configure the I2S with the SPI_InitStruct values */
742 tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
743 (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
744 (uint16_t)I2S_InitStruct->I2S_CPOL))));
745
746 /* Write to SPIx I2SCFGR */
747 I2Sxext->I2SCFGR = tmpreg;
748 }
749
750 /**
751 * @brief Enables or disables the SS output for the selected SPI.
752 * @note This function can be called only after the SPI_Init() function has
753 * been called and the NSS hardware management mode is selected.
754 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
755 * @param NewState: new state of the SPIx SS output.
756 * This parameter can be: ENABLE or DISABLE.
757 * @retval None
758 */
SPI_SSOutputCmd(SPI_TypeDef * SPIx,FunctionalState NewState)759 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
760 {
761 /* Check the parameters */
762 assert_param(IS_SPI_ALL_PERIPH(SPIx));
763 assert_param(IS_FUNCTIONAL_STATE(NewState));
764 if (NewState != DISABLE)
765 {
766 /* Enable the selected SPI SS output */
767 SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
768 }
769 else
770 {
771 /* Disable the selected SPI SS output */
772 SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
773 }
774 }
775
776 /**
777 * @brief Enables or disables the NSS pulse management mode.
778 * @note This function can be called only after the SPI_Init() function has
779 * been called.
780 * @note When TI mode is selected, the control bits NSSP is not taken into
781 * consideration and are configured by hardware respectively to the
782 * TI mode requirements.
783 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
784 * @param NewState: new state of the NSS pulse management mode.
785 * This parameter can be: ENABLE or DISABLE.
786 * @retval None
787 */
SPI_NSSPulseModeCmd(SPI_TypeDef * SPIx,FunctionalState NewState)788 void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
789 {
790 /* Check the parameters */
791 assert_param(IS_SPI_ALL_PERIPH(SPIx));
792 assert_param(IS_FUNCTIONAL_STATE(NewState));
793
794 if (NewState != DISABLE)
795 {
796 /* Enable the NSS pulse management mode */
797 SPIx->CR2 |= SPI_CR2_NSSP;
798 }
799 else
800 {
801 /* Disable the NSS pulse management mode */
802 SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP);
803 }
804 }
805
806 /**
807 * @}
808 */
809
810 /** @defgroup SPI_Group2 Data transfers functions
811 * @brief Data transfers functions
812 *
813 @verbatim
814 ===============================================================================
815 ##### Data transfers functions #####
816 ===============================================================================
817 [..] This section provides a set of functions allowing to manage the SPI or I2S
818 data transfers.
819 [..] In reception, data are received and then stored into an internal Rx buffer while
820 In transmission, data are first stored into an internal Tx buffer before being
821 transmitted.
822 [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
823 function and returns the Rx buffered value. Whereas a write access to the SPI_DR
824 can be done using SPI_I2S_SendData() function and stores the written data into
825 Tx buffer.
826
827 @endverbatim
828 * @{
829 */
830
831 /**
832 * @brief Transmits a Data through the SPIx peripheral.
833 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
834 * @param Data: Data to be transmitted.
835 * @retval None
836 */
SPI_SendData8(SPI_TypeDef * SPIx,uint8_t Data)837 void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
838 {
839 uint32_t spixbase = 0x00;
840
841 /* Check the parameters */
842 assert_param(IS_SPI_ALL_PERIPH(SPIx));
843
844 spixbase = (uint32_t)SPIx;
845 spixbase += 0x0C;
846
847 *(__IO uint8_t *) spixbase = Data;
848 }
849
850 /**
851 * @brief Transmits a Data through the SPIx/I2Sx peripheral.
852 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
853 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
854 * @param Data: Data to be transmitted.
855 * @retval None
856 */
SPI_I2S_SendData16(SPI_TypeDef * SPIx,uint16_t Data)857 void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)
858 {
859 /* Check the parameters */
860 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
861
862 SPIx->DR = (uint16_t)Data;
863 }
864
865 /**
866 * @brief Returns the most recent received data by the SPIx peripheral.
867 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
868 * @retval The value of the received data.
869 */
SPI_ReceiveData8(SPI_TypeDef * SPIx)870 uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx)
871 {
872 uint32_t spixbase = 0x00;
873
874 /* Check the parameters */
875 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
876
877 spixbase = (uint32_t)SPIx;
878 spixbase += 0x0C;
879
880 return *(__IO uint8_t *) spixbase;
881 }
882
883 /**
884 * @brief Returns the most recent received data by the SPIx peripheral.
885 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3 or 4
886 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
887 * @retval The value of the received data.
888 */
SPI_I2S_ReceiveData16(SPI_TypeDef * SPIx)889 uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)
890 {
891 /* Check the parameters */
892 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
893
894 return SPIx->DR;
895 }
896 /**
897 * @}
898 */
899
900 /** @defgroup SPI_Group3 Hardware CRC Calculation functions
901 * @brief Hardware CRC Calculation functions
902 *
903 @verbatim
904 ===============================================================================
905 ##### Hardware CRC Calculation functions #####
906 ===============================================================================
907 [..] This section provides a set of functions allowing to manage the SPI CRC hardware
908 calculation.
909 [..] SPI communication using CRC is possible through the following procedure:
910 (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
911 Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
912 function.
913 (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
914 (#) Enable the SPI using the SPI_Cmd() function
915 (#) Before writing the last data to the TX buffer, set the CRCNext bit using the
916 SPI_TransmitCRC() function to indicate that after transmission of the last
917 data, the CRC should be transmitted.
918 (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
919 bit is reset. The CRC is also received and compared against the SPI_RXCRCR
920 value.
921 If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
922 can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
923 [..]
924 (@)
925 (+@) It is advised to don't read the calculate CRC values during the communication.
926 (+@) When the SPI is in slave mode, be careful to enable CRC calculation only
927 when the clock is stable, that is, when the clock is in the steady state.
928 If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
929 to the SCK slave input clock as soon as CRCEN is set, and this, whatever
930 the value of the SPE bit.
931 (+@) With high bitrate frequencies, be careful when transmitting the CRC.
932 As the number of used CPU cycles has to be as low as possible in the CRC
933 transfer phase, it is forbidden to call software functions in the CRC
934 transmission sequence to avoid errors in the last data and CRC reception.
935 In fact, CRCNEXT bit has to be written before the end of the transmission/reception
936 of the last data.
937 (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
938 degradation of the SPI speed performance due to CPU accesses impacting the
939 SPI bandwidth.
940 (+@) When the STM32F30x are configured as slaves and the NSS hardware mode is
941 used, the NSS pin needs to be kept low between the data phase and the CRC
942 phase.
943 (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
944 calculation takes place even if a high level is applied on the NSS pin.
945 This may happen for example in case of a multislave environment where the
946 communication master addresses slaves alternately.
947 (+@) Between a slave deselection (high level on NSS) and a new slave selection
948 (low level on NSS), the CRC value should be cleared on both master and slave
949 sides in order to resynchronize the master and slave for their respective
950 CRC calculation.
951 [..]
952 (@) To clear the CRC, follow the procedure below:
953 (#@) Disable SPI using the SPI_Cmd() function.
954 (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
955 (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
956 (#@) Enable SPI using the SPI_Cmd() function.
957
958 @endverbatim
959 * @{
960 */
961
962 /**
963 * @brief Configures the CRC calculation length for the selected SPI.
964 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
965 * @param SPI_CRCLength: specifies the SPI CRC calculation length.
966 * This parameter can be one of the following values:
967 * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits
968 * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits
969 * @retval None
970 */
SPI_CRCLengthConfig(SPI_TypeDef * SPIx,uint16_t SPI_CRCLength)971 void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
972 {
973 /* Check the parameters */
974 assert_param(IS_SPI_ALL_PERIPH(SPIx));
975 assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));
976
977 /* Clear CRCL bit */
978 SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);
979
980 /* Set new CRCL bit value */
981 SPIx->CR1 |= SPI_CRCLength;
982 }
983
984 /**
985 * @brief Enables or disables the CRC value calculation of the transferred bytes.
986 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
987 * @param NewState: new state of the SPIx CRC value calculation.
988 * This parameter can be: ENABLE or DISABLE.
989 * @retval None
990 */
SPI_CalculateCRC(SPI_TypeDef * SPIx,FunctionalState NewState)991 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
992 {
993 /* Check the parameters */
994 assert_param(IS_SPI_ALL_PERIPH(SPIx));
995 assert_param(IS_FUNCTIONAL_STATE(NewState));
996
997 if (NewState != DISABLE)
998 {
999 /* Enable the selected SPI CRC calculation */
1000 SPIx->CR1 |= SPI_CR1_CRCEN;
1001 }
1002 else
1003 {
1004 /* Disable the selected SPI CRC calculation */
1005 SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
1006 }
1007 }
1008
1009 /**
1010 * @brief Transmits the SPIx CRC value.
1011 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
1012 * @retval None
1013 */
SPI_TransmitCRC(SPI_TypeDef * SPIx)1014 void SPI_TransmitCRC(SPI_TypeDef* SPIx)
1015 {
1016 /* Check the parameters */
1017 assert_param(IS_SPI_ALL_PERIPH(SPIx));
1018
1019 /* Enable the selected SPI CRC transmission */
1020 SPIx->CR1 |= SPI_CR1_CRCNEXT;
1021 }
1022
1023 /**
1024 * @brief Returns the transmit or the receive CRC register value for the specified SPI.
1025 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
1026 * @param SPI_CRC: specifies the CRC register to be read.
1027 * This parameter can be one of the following values:
1028 * @arg SPI_CRC_Tx: Selects Tx CRC register
1029 * @arg SPI_CRC_Rx: Selects Rx CRC register
1030 * @retval The selected CRC register value..
1031 */
SPI_GetCRC(SPI_TypeDef * SPIx,uint8_t SPI_CRC)1032 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
1033 {
1034 uint16_t crcreg = 0;
1035 /* Check the parameters */
1036 assert_param(IS_SPI_ALL_PERIPH(SPIx));
1037 assert_param(IS_SPI_CRC(SPI_CRC));
1038
1039 if (SPI_CRC != SPI_CRC_Rx)
1040 {
1041 /* Get the Tx CRC register */
1042 crcreg = SPIx->TXCRCR;
1043 }
1044 else
1045 {
1046 /* Get the Rx CRC register */
1047 crcreg = SPIx->RXCRCR;
1048 }
1049 /* Return the selected CRC register */
1050 return crcreg;
1051 }
1052
1053 /**
1054 * @brief Returns the CRC Polynomial register value for the specified SPI.
1055 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
1056 * @retval The CRC Polynomial register value.
1057 */
SPI_GetCRCPolynomial(SPI_TypeDef * SPIx)1058 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
1059 {
1060 /* Check the parameters */
1061 assert_param(IS_SPI_ALL_PERIPH(SPIx));
1062
1063 /* Return the CRC polynomial register */
1064 return SPIx->CRCPR;
1065 }
1066
1067 /**
1068 * @}
1069 */
1070
1071 /** @defgroup SPI_Group4 DMA transfers management functions
1072 * @brief DMA transfers management functions
1073 *
1074 @verbatim
1075 ===============================================================================
1076 ##### DMA transfers management functions #####
1077 ===============================================================================
1078
1079 @endverbatim
1080 * @{
1081 */
1082
1083 /**
1084 * @brief Enables or disables the SPIx/I2Sx DMA interface.
1085 * @param SPIx:To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3 or 4
1086 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
1087 * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
1088 * This parameter can be any combination of the following values:
1089 * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
1090 * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
1091 * @param NewState: new state of the selected SPI DMA transfer request.
1092 * This parameter can be: ENABLE or DISABLE.
1093 * @retval None
1094 */
SPI_I2S_DMACmd(SPI_TypeDef * SPIx,uint16_t SPI_I2S_DMAReq,FunctionalState NewState)1095 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
1096 {
1097 /* Check the parameters */
1098 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
1099 assert_param(IS_FUNCTIONAL_STATE(NewState));
1100 assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));
1101
1102 if (NewState != DISABLE)
1103 {
1104 /* Enable the selected SPI DMA requests */
1105 SPIx->CR2 |= SPI_I2S_DMAReq;
1106 }
1107 else
1108 {
1109 /* Disable the selected SPI DMA requests */
1110 SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
1111 }
1112 }
1113
1114 /**
1115 * @brief Configures the number of data to transfer type(Even/Odd) for the DMA
1116 * last transfers and for the selected SPI.
1117 * @note This function have a meaning only if DMA mode is selected and if
1118 * the packing mode is used (data length <= 8 and DMA transfer size halfword)
1119 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
1120 * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state.
1121 * This parameter can be one of the following values:
1122 * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even
1123 * and number of data for reception Even.
1124 * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd
1125 * and number of data for reception Even.
1126 * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even
1127 * and number of data for reception Odd.
1128 * @arg SPI_LastDMATransfer_TxOddRxOdd: RNumber of data for transmission Odd
1129 * and number of data for reception Odd.
1130 * @retval None
1131 */
SPI_LastDMATransferCmd(SPI_TypeDef * SPIx,uint16_t SPI_LastDMATransfer)1132 void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)
1133 {
1134 /* Check the parameters */
1135 assert_param(IS_SPI_ALL_PERIPH(SPIx));
1136 assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));
1137
1138 /* Clear LDMA_TX and LDMA_RX bits */
1139 SPIx->CR2 &= CR2_LDMA_MASK;
1140
1141 /* Set new LDMA_TX and LDMA_RX bits value */
1142 SPIx->CR2 |= SPI_LastDMATransfer;
1143 }
1144
1145 /**
1146 * @}
1147 */
1148
1149 /** @defgroup SPI_Group5 Interrupts and flags management functions
1150 * @brief Interrupts and flags management functions
1151 *
1152 @verbatim
1153 ===============================================================================
1154 ##### Interrupts and flags management functions #####
1155 ===============================================================================
1156 [..] This section provides a set of functions allowing to configure the SPI/I2S
1157 Interrupts sources and check or clear the flags or pending bits status.
1158 The user should identify which mode will be used in his application to manage
1159 the communication: Polling mode, Interrupt mode or DMA mode.
1160
1161 *** Polling Mode ***
1162 ====================
1163 [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
1164 (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register.
1165 (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register.
1166 (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
1167 (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur.
1168 (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur.
1169 (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur.
1170 (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.
1171 (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
1172 (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
1173 [..]
1174 (@) Do not use the BSY flag to handle each data transmission or reception.
1175 It is better to use the TXE and RXNE flags instead.
1176 [..] In this Mode it is advised to use the following functions:
1177 (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
1178 (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
1179
1180 *** Interrupt Mode ***
1181 ======================
1182 [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources
1183 and 5 pending bits:
1184 [..] Pending Bits:
1185 (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register.
1186 (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register.
1187 (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur.
1188 (#) I2S_IT_UDR : to indicate an Underrun Error occurs.
1189 (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.
1190 [..] Interrupt Source:
1191 (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
1192 interrupt.
1193 (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
1194 empty interrupt.
1195 (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
1196 [..] In this Mode it is advised to use the following functions:
1197 (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
1198 (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
1199
1200 *** FIFO Status ***
1201 ===================
1202 [..] It is possible to monitor the FIFO status when a transfer is ongoing using the
1203 following function:
1204 (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction);
1205
1206 *** DMA Mode ***
1207 ================
1208 [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
1209 (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
1210 (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
1211 [..] In this Mode it is advised to use the following function:
1212 (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
1213
1214 @endverbatim
1215 * @{
1216 */
1217
1218 /**
1219 * @brief Enables or disables the specified SPI/I2S interrupts.
1220 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3 or 4
1221 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
1222 * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
1223 * This parameter can be one of the following values:
1224 * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
1225 * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
1226 * @arg SPI_I2S_IT_ERR: Error interrupt mask
1227 * @param NewState: new state of the specified SPI interrupt.
1228 * This parameter can be: ENABLE or DISABLE.
1229 * @retval None
1230 */
SPI_I2S_ITConfig(SPI_TypeDef * SPIx,uint8_t SPI_I2S_IT,FunctionalState NewState)1231 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
1232 {
1233 uint16_t itpos = 0, itmask = 0 ;
1234
1235 /* Check the parameters */
1236 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
1237 assert_param(IS_FUNCTIONAL_STATE(NewState));
1238 assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
1239
1240 /* Get the SPI IT index */
1241 itpos = SPI_I2S_IT >> 4;
1242
1243 /* Set the IT mask */
1244 itmask = (uint16_t)1 << (uint16_t)itpos;
1245
1246 if (NewState != DISABLE)
1247 {
1248 /* Enable the selected SPI interrupt */
1249 SPIx->CR2 |= itmask;
1250 }
1251 else
1252 {
1253 /* Disable the selected SPI interrupt */
1254 SPIx->CR2 &= (uint16_t)~itmask;
1255 }
1256 }
1257
1258 /**
1259 * @brief Returns the current SPIx Transmission FIFO filled level.
1260 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
1261 * @retval The Transmission FIFO filling state.
1262 * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty
1263 * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
1264 * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full.
1265 * - SPI_TransmissionFIFOStatus_Full: when FIFO is full.
1266 */
SPI_GetTransmissionFIFOStatus(SPI_TypeDef * SPIx)1267 uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx)
1268 {
1269 /* Get the SPIx Transmission FIFO level bits */
1270 return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));
1271 }
1272
1273 /**
1274 * @brief Returns the current SPIx Reception FIFO filled level.
1275 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral.
1276 * @retval The Reception FIFO filling state.
1277 * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty
1278 * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
1279 * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full.
1280 * - SPI_ReceptionFIFOStatus_Full: when FIFO is full.
1281 */
SPI_GetReceptionFIFOStatus(SPI_TypeDef * SPIx)1282 uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)
1283 {
1284 /* Get the SPIx Reception FIFO level bits */
1285 return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));
1286 }
1287
1288 /**
1289 * @brief Checks whether the specified SPI flag is set or not.
1290 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3 or 4
1291 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
1292 * @param SPI_I2S_FLAG: specifies the SPI flag to check.
1293 * This parameter can be one of the following values:
1294 * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
1295 * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
1296 * @arg SPI_I2S_FLAG_BSY: Busy flag.
1297 * @arg SPI_I2S_FLAG_OVR: Overrun flag.
1298 * @arg SPI_I2S_FLAG_MODF: Mode Fault flag.
1299 * @arg SPI_I2S_FLAG_CRCERR: CRC Error flag.
1300 * @arg SPI_I2S_FLAG_FRE: TI frame format error flag.
1301 * @arg I2S_FLAG_UDR: Underrun Error flag.
1302 * @arg I2S_FLAG_CHSIDE: Channel Side flag.
1303 * @retval The new state of SPI_I2S_FLAG (SET or RESET).
1304 */
SPI_I2S_GetFlagStatus(SPI_TypeDef * SPIx,uint16_t SPI_I2S_FLAG)1305 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
1306 {
1307 FlagStatus bitstatus = RESET;
1308 /* Check the parameters */
1309 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
1310 assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
1311
1312 /* Check the status of the specified SPI flag */
1313 if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
1314 {
1315 /* SPI_I2S_FLAG is set */
1316 bitstatus = SET;
1317 }
1318 else
1319 {
1320 /* SPI_I2S_FLAG is reset */
1321 bitstatus = RESET;
1322 }
1323 /* Return the SPI_I2S_FLAG status */
1324 return bitstatus;
1325 }
1326
1327 /**
1328 * @brief Clears the SPIx CRC Error (CRCERR) flag.
1329 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3 or 4
1330 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
1331 * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
1332 * This function clears only CRCERR flag.
1333 * @note OVR (OverRun error) flag is cleared by software sequence: a read
1334 * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
1335 * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
1336 * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
1337 * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
1338 * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
1339 * @retval None
1340 */
SPI_I2S_ClearFlag(SPI_TypeDef * SPIx,uint16_t SPI_I2S_FLAG)1341 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
1342 {
1343 /* Check the parameters */
1344 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
1345 assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));
1346
1347 /* Clear the selected SPI CRC Error (CRCERR) flag */
1348 SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
1349 }
1350
1351 /**
1352 * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
1353 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3 or 4
1354 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
1355 * @param SPI_I2S_IT: specifies the SPI interrupt source to check.
1356 * This parameter can be one of the following values:
1357 * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
1358 * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
1359 * @arg SPI_IT_MODF: Mode Fault interrupt.
1360 * @arg SPI_I2S_IT_OVR: Overrun interrupt.
1361 * @arg I2S_IT_UDR: Underrun interrupt.
1362 * @arg SPI_I2S_IT_FRE: Format Error interrupt.
1363 * @retval The new state of SPI_I2S_IT (SET or RESET).
1364 */
SPI_I2S_GetITStatus(SPI_TypeDef * SPIx,uint8_t SPI_I2S_IT)1365 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
1366 {
1367 ITStatus bitstatus = RESET;
1368 uint16_t itpos = 0, itmask = 0, enablestatus = 0;
1369
1370 /* Check the parameters */
1371 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
1372 assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
1373
1374 /* Get the SPI_I2S_IT index */
1375 itpos = 0x01 << (SPI_I2S_IT & 0x0F);
1376
1377 /* Get the SPI_I2S_IT IT mask */
1378 itmask = SPI_I2S_IT >> 4;
1379
1380 /* Set the IT mask */
1381 itmask = 0x01 << itmask;
1382
1383 /* Get the SPI_I2S_IT enable bit status */
1384 enablestatus = (SPIx->CR2 & itmask) ;
1385
1386 /* Check the status of the specified SPI interrupt */
1387 if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
1388 {
1389 /* SPI_I2S_IT is set */
1390 bitstatus = SET;
1391 }
1392 else
1393 {
1394 /* SPI_I2S_IT is reset */
1395 bitstatus = RESET;
1396 }
1397 /* Return the SPI_I2S_IT status */
1398 return bitstatus;
1399 }
1400
1401 /**
1402 * @}
1403 */
1404
1405 /**
1406 * @}
1407 */
1408
1409 /**
1410 * @}
1411 */
1412
1413 /**
1414 * @}
1415 */
1416
1417 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1418