1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_spi.h 4 * @author MCD Application Team 5 * @version V1.6.1 6 * @date 21-October-2015 7 * @brief This file contains all the functions prototypes for the SPI 8 * firmware library. 9 ****************************************************************************** 10 * @attention 11 * 12 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> 13 * 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 * You may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at: 17 * 18 * http://www.st.com/software_license_agreement_liberty_v2 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ****************************************************************************** 27 */ 28 29 /* Define to prevent recursive inclusion -------------------------------------*/ 30 #ifndef __STM32F4xx_SPI_H 31 #define __STM32F4xx_SPI_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* Includes ------------------------------------------------------------------*/ 38 #include "stm32f4xx.h" 39 40 /** @addtogroup STM32F4xx_StdPeriph_Driver 41 * @{ 42 */ 43 44 /** @addtogroup SPI 45 * @{ 46 */ 47 48 /* Exported types ------------------------------------------------------------*/ 49 50 /** 51 * @brief SPI Init structure definition 52 */ 53 54 typedef struct 55 { 56 uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. 57 This parameter can be a value of @ref SPI_data_direction */ 58 59 uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. 60 This parameter can be a value of @ref SPI_mode */ 61 62 uint16_t SPI_DataSize; /*!< Specifies the SPI data size. 63 This parameter can be a value of @ref SPI_data_size */ 64 65 uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. 66 This parameter can be a value of @ref SPI_Clock_Polarity */ 67 68 uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. 69 This parameter can be a value of @ref SPI_Clock_Phase */ 70 71 uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by 72 hardware (NSS pin) or by software using the SSI bit. 73 This parameter can be a value of @ref SPI_Slave_Select_management */ 74 75 uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 76 used to configure the transmit and receive SCK clock. 77 This parameter can be a value of @ref SPI_BaudRate_Prescaler 78 @note The communication clock is derived from the master 79 clock. The slave clock does not need to be set. */ 80 81 uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 82 This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 83 84 uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ 85 }SPI_InitTypeDef; 86 87 /** 88 * @brief I2S Init structure definition 89 */ 90 91 typedef struct 92 { 93 94 uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. 95 This parameter can be a value of @ref I2S_Mode */ 96 97 uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. 98 This parameter can be a value of @ref I2S_Standard */ 99 100 uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. 101 This parameter can be a value of @ref I2S_Data_Format */ 102 103 uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. 104 This parameter can be a value of @ref I2S_MCLK_Output */ 105 106 uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. 107 This parameter can be a value of @ref I2S_Audio_Frequency */ 108 109 uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. 110 This parameter can be a value of @ref I2S_Clock_Polarity */ 111 }I2S_InitTypeDef; 112 113 /* Exported constants --------------------------------------------------------*/ 114 115 /** @defgroup SPI_Exported_Constants 116 * @{ 117 */ 118 119 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ 120 ((PERIPH) == SPI2) || \ 121 ((PERIPH) == SPI3) || \ 122 ((PERIPH) == SPI4) || \ 123 ((PERIPH) == SPI5) || \ 124 ((PERIPH) == SPI6)) 125 126 #define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ 127 ((PERIPH) == SPI2) || \ 128 ((PERIPH) == SPI3) || \ 129 ((PERIPH) == SPI4) || \ 130 ((PERIPH) == SPI5) || \ 131 ((PERIPH) == SPI6) || \ 132 ((PERIPH) == I2S2ext) || \ 133 ((PERIPH) == I2S3ext)) 134 135 #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ 136 ((PERIPH) == SPI3)) 137 138 #define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ 139 ((PERIPH) == SPI3) || \ 140 ((PERIPH) == I2S2ext) || \ 141 ((PERIPH) == I2S3ext)) 142 143 #define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \ 144 ((PERIPH) == I2S3ext)) 145 146 147 /** @defgroup SPI_data_direction 148 * @{ 149 */ 150 151 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) 152 #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) 153 #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) 154 #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) 155 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ 156 ((MODE) == SPI_Direction_2Lines_RxOnly) || \ 157 ((MODE) == SPI_Direction_1Line_Rx) || \ 158 ((MODE) == SPI_Direction_1Line_Tx)) 159 /** 160 * @} 161 */ 162 163 /** @defgroup SPI_mode 164 * @{ 165 */ 166 167 #define SPI_Mode_Master ((uint16_t)0x0104) 168 #define SPI_Mode_Slave ((uint16_t)0x0000) 169 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ 170 ((MODE) == SPI_Mode_Slave)) 171 /** 172 * @} 173 */ 174 175 /** @defgroup SPI_data_size 176 * @{ 177 */ 178 179 #define SPI_DataSize_16b ((uint16_t)0x0800) 180 #define SPI_DataSize_8b ((uint16_t)0x0000) 181 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ 182 ((DATASIZE) == SPI_DataSize_8b)) 183 /** 184 * @} 185 */ 186 187 /** @defgroup SPI_Clock_Polarity 188 * @{ 189 */ 190 191 #define SPI_CPOL_Low ((uint16_t)0x0000) 192 #define SPI_CPOL_High ((uint16_t)0x0002) 193 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ 194 ((CPOL) == SPI_CPOL_High)) 195 /** 196 * @} 197 */ 198 199 /** @defgroup SPI_Clock_Phase 200 * @{ 201 */ 202 203 #define SPI_CPHA_1Edge ((uint16_t)0x0000) 204 #define SPI_CPHA_2Edge ((uint16_t)0x0001) 205 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ 206 ((CPHA) == SPI_CPHA_2Edge)) 207 /** 208 * @} 209 */ 210 211 /** @defgroup SPI_Slave_Select_management 212 * @{ 213 */ 214 215 #define SPI_NSS_Soft ((uint16_t)0x0200) 216 #define SPI_NSS_Hard ((uint16_t)0x0000) 217 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ 218 ((NSS) == SPI_NSS_Hard)) 219 /** 220 * @} 221 */ 222 223 /** @defgroup SPI_BaudRate_Prescaler 224 * @{ 225 */ 226 227 #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) 228 #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) 229 #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) 230 #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) 231 #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) 232 #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) 233 #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) 234 #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) 235 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ 236 ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ 237 ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ 238 ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ 239 ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ 240 ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ 241 ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ 242 ((PRESCALER) == SPI_BaudRatePrescaler_256)) 243 /** 244 * @} 245 */ 246 247 /** @defgroup SPI_MSB_LSB_transmission 248 * @{ 249 */ 250 251 #define SPI_FirstBit_MSB ((uint16_t)0x0000) 252 #define SPI_FirstBit_LSB ((uint16_t)0x0080) 253 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ 254 ((BIT) == SPI_FirstBit_LSB)) 255 /** 256 * @} 257 */ 258 259 /** @defgroup SPI_I2S_Mode 260 * @{ 261 */ 262 263 #define I2S_Mode_SlaveTx ((uint16_t)0x0000) 264 #define I2S_Mode_SlaveRx ((uint16_t)0x0100) 265 #define I2S_Mode_MasterTx ((uint16_t)0x0200) 266 #define I2S_Mode_MasterRx ((uint16_t)0x0300) 267 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ 268 ((MODE) == I2S_Mode_SlaveRx) || \ 269 ((MODE) == I2S_Mode_MasterTx)|| \ 270 ((MODE) == I2S_Mode_MasterRx)) 271 /** 272 * @} 273 */ 274 275 276 /** @defgroup SPI_I2S_Standard 277 * @{ 278 */ 279 280 #define I2S_Standard_Phillips ((uint16_t)0x0000) 281 #define I2S_Standard_MSB ((uint16_t)0x0010) 282 #define I2S_Standard_LSB ((uint16_t)0x0020) 283 #define I2S_Standard_PCMShort ((uint16_t)0x0030) 284 #define I2S_Standard_PCMLong ((uint16_t)0x00B0) 285 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ 286 ((STANDARD) == I2S_Standard_MSB) || \ 287 ((STANDARD) == I2S_Standard_LSB) || \ 288 ((STANDARD) == I2S_Standard_PCMShort) || \ 289 ((STANDARD) == I2S_Standard_PCMLong)) 290 /** 291 * @} 292 */ 293 294 /** @defgroup SPI_I2S_Data_Format 295 * @{ 296 */ 297 298 #define I2S_DataFormat_16b ((uint16_t)0x0000) 299 #define I2S_DataFormat_16bextended ((uint16_t)0x0001) 300 #define I2S_DataFormat_24b ((uint16_t)0x0003) 301 #define I2S_DataFormat_32b ((uint16_t)0x0005) 302 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ 303 ((FORMAT) == I2S_DataFormat_16bextended) || \ 304 ((FORMAT) == I2S_DataFormat_24b) || \ 305 ((FORMAT) == I2S_DataFormat_32b)) 306 /** 307 * @} 308 */ 309 310 /** @defgroup SPI_I2S_MCLK_Output 311 * @{ 312 */ 313 314 #define I2S_MCLKOutput_Enable ((uint16_t)0x0200) 315 #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) 316 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ 317 ((OUTPUT) == I2S_MCLKOutput_Disable)) 318 /** 319 * @} 320 */ 321 322 /** @defgroup SPI_I2S_Audio_Frequency 323 * @{ 324 */ 325 326 #define I2S_AudioFreq_192k ((uint32_t)192000) 327 #define I2S_AudioFreq_96k ((uint32_t)96000) 328 #define I2S_AudioFreq_48k ((uint32_t)48000) 329 #define I2S_AudioFreq_44k ((uint32_t)44100) 330 #define I2S_AudioFreq_32k ((uint32_t)32000) 331 #define I2S_AudioFreq_22k ((uint32_t)22050) 332 #define I2S_AudioFreq_16k ((uint32_t)16000) 333 #define I2S_AudioFreq_11k ((uint32_t)11025) 334 #define I2S_AudioFreq_8k ((uint32_t)8000) 335 #define I2S_AudioFreq_Default ((uint32_t)2) 336 337 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ 338 ((FREQ) <= I2S_AudioFreq_192k)) || \ 339 ((FREQ) == I2S_AudioFreq_Default)) 340 /** 341 * @} 342 */ 343 344 /** @defgroup SPI_I2S_Clock_Polarity 345 * @{ 346 */ 347 348 #define I2S_CPOL_Low ((uint16_t)0x0000) 349 #define I2S_CPOL_High ((uint16_t)0x0008) 350 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ 351 ((CPOL) == I2S_CPOL_High)) 352 /** 353 * @} 354 */ 355 356 /** @defgroup SPI_I2S_DMA_transfer_requests 357 * @{ 358 */ 359 360 #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) 361 #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) 362 #define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) 363 /** 364 * @} 365 */ 366 367 /** @defgroup SPI_NSS_internal_software_management 368 * @{ 369 */ 370 371 #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) 372 #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) 373 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ 374 ((INTERNAL) == SPI_NSSInternalSoft_Reset)) 375 /** 376 * @} 377 */ 378 379 /** @defgroup SPI_CRC_Transmit_Receive 380 * @{ 381 */ 382 383 #define SPI_CRC_Tx ((uint8_t)0x00) 384 #define SPI_CRC_Rx ((uint8_t)0x01) 385 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) 386 /** 387 * @} 388 */ 389 390 /** @defgroup SPI_direction_transmit_receive 391 * @{ 392 */ 393 394 #define SPI_Direction_Rx ((uint16_t)0xBFFF) 395 #define SPI_Direction_Tx ((uint16_t)0x4000) 396 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ 397 ((DIRECTION) == SPI_Direction_Tx)) 398 /** 399 * @} 400 */ 401 402 /** @defgroup SPI_I2S_interrupts_definition 403 * @{ 404 */ 405 406 #define SPI_I2S_IT_TXE ((uint8_t)0x71) 407 #define SPI_I2S_IT_RXNE ((uint8_t)0x60) 408 #define SPI_I2S_IT_ERR ((uint8_t)0x50) 409 #define I2S_IT_UDR ((uint8_t)0x53) 410 #define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) 411 412 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ 413 ((IT) == SPI_I2S_IT_RXNE) || \ 414 ((IT) == SPI_I2S_IT_ERR)) 415 416 #define SPI_I2S_IT_OVR ((uint8_t)0x56) 417 #define SPI_IT_MODF ((uint8_t)0x55) 418 #define SPI_IT_CRCERR ((uint8_t)0x54) 419 420 #define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) 421 422 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ 423 ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ 424 ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ 425 ((IT) == SPI_I2S_IT_TIFRFE)) 426 /** 427 * @} 428 */ 429 430 /** @defgroup SPI_I2S_flags_definition 431 * @{ 432 */ 433 434 #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) 435 #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) 436 #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) 437 #define I2S_FLAG_UDR ((uint16_t)0x0008) 438 #define SPI_FLAG_CRCERR ((uint16_t)0x0010) 439 #define SPI_FLAG_MODF ((uint16_t)0x0020) 440 #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) 441 #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) 442 #define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) 443 444 #define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) 445 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ 446 ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ 447 ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ 448 ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ 449 ((FLAG) == SPI_I2S_FLAG_TIFRFE)) 450 /** 451 * @} 452 */ 453 454 /** @defgroup SPI_CRC_polynomial 455 * @{ 456 */ 457 458 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) 459 /** 460 * @} 461 */ 462 463 /** @defgroup SPI_I2S_Legacy 464 * @{ 465 */ 466 467 #define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx 468 #define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx 469 #define SPI_IT_TXE SPI_I2S_IT_TXE 470 #define SPI_IT_RXNE SPI_I2S_IT_RXNE 471 #define SPI_IT_ERR SPI_I2S_IT_ERR 472 #define SPI_IT_OVR SPI_I2S_IT_OVR 473 #define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE 474 #define SPI_FLAG_TXE SPI_I2S_FLAG_TXE 475 #define SPI_FLAG_OVR SPI_I2S_FLAG_OVR 476 #define SPI_FLAG_BSY SPI_I2S_FLAG_BSY 477 #define SPI_DeInit SPI_I2S_DeInit 478 #define SPI_ITConfig SPI_I2S_ITConfig 479 #define SPI_DMACmd SPI_I2S_DMACmd 480 #define SPI_SendData SPI_I2S_SendData 481 #define SPI_ReceiveData SPI_I2S_ReceiveData 482 #define SPI_GetFlagStatus SPI_I2S_GetFlagStatus 483 #define SPI_ClearFlag SPI_I2S_ClearFlag 484 #define SPI_GetITStatus SPI_I2S_GetITStatus 485 #define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit 486 /** 487 * @} 488 */ 489 490 /** 491 * @} 492 */ 493 494 /* Exported macro ------------------------------------------------------------*/ 495 /* Exported functions --------------------------------------------------------*/ 496 497 /* Function used to set the SPI configuration to the default reset state *****/ 498 void SPI_I2S_DeInit(SPI_TypeDef* SPIx); 499 500 /* Initialization and Configuration functions *********************************/ 501 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); 502 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); 503 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); 504 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); 505 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 506 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 507 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); 508 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); 509 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); 510 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 511 void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 512 513 void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct); 514 515 /* Data transfers functions ***************************************************/ 516 void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); 517 uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); 518 519 /* Hardware CRC Calculation functions *****************************************/ 520 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); 521 void SPI_TransmitCRC(SPI_TypeDef* SPIx); 522 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); 523 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); 524 525 /* DMA transfers management functions *****************************************/ 526 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); 527 528 /* Interrupts and flags management functions **********************************/ 529 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); 530 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 531 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 532 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 533 void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 534 535 #ifdef __cplusplus 536 } 537 #endif 538 539 #endif /*__STM32F4xx_SPI_H */ 540 541 /** 542 * @} 543 */ 544 545 /** 546 * @} 547 */ 548 549 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 550