1 /*
2 This file is part of adms - http://sourceforge.net/projects/mot-adms.
3
4 adms is a code generator for the Verilog-AMS language.
5
6 Copyright (C) 2002-2012 Laurent Lemaitre <r29173@users.sourceforge.net>
7 2014-08-12 Guilherme Brondani Torri <guitorri@gmail.com>
8 2013-07-24 Bastien ROUCARIÈS <roucaries.bastien@gmail.com>
9
10 This program is free software: you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation, either version 3 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>.
22 */
23
24 %option outfile="verilogaLex.c"
25 %option prefix="veriloga"
26
27 %{
28
29 #include "admsVeriloga.h"
30 #include "verilogaYacc.h"
31
adms_strtointeger(const char * mystr)32 static int adms_strtointeger (const char *mystr)
33 {
34 int val;
35 errno=0;
36 val=(int)strtol(mystr,NULL,10);
37 if(errno)
38 adms_message_fatal(("%s: strtoint conversion failed\n",mystr))
39 return val;
40 }
adms_veriloga_setfile_input(FILE * ifile)41 void adms_veriloga_setfile_input (FILE *ifile)
42 {
43 yyin=ifile;
44 }
verilogaerror(const char * s)45 void verilogaerror (const char *s)
46 {
47 adms_message_fatal(("%s: during lexical analysis %s at line %i -- see '%s'\n",root()->_curfilename,s,root()->_curline,verilogatext))
48 }
POS_UPDATE(const int myyyleng,const char * myyytext)49 void POS_UPDATE(const int myyyleng,const char*myyytext)
50 {
51 int c=root()->_fpos;
52 adms_message_dbg_vla(("%s:%i:%i-%i read token '%s'\n",root()->_curfilename,
53 root()->_curline,c+1,c+myyyleng,myyytext))
54 adms_admsmain_valueto_fpos(root(),c+myyyleng);
55 }
TKRETURN(const char * myyytext,const int myyyleng)56 void TKRETURN(const char*myyytext, const int myyyleng)
57 {
58 verilogalval._lexval=adms_lexval_new(myyytext,root()->_curfilename,root()->_curline,root()->_fpos+1);
59 POS_UPDATE(myyyleng,myyytext);
60 }
TKSTRIPPEDRETURN(const char * myyytext,const int myyyleng)61 void TKSTRIPPEDRETURN(const char*myyytext, const int myyyleng)
62 {
63 char*mystrippedstring;
64 int mynewlen=strlen(myyytext)-2;
65 assert(mynewlen>=0);
66 mystrippedstring=(char*)malloc(mynewlen+1);
67 if(mystrippedstring)
68 {
69 strncpy(mystrippedstring,myyytext+1,mynewlen);
70 mystrippedstring[mynewlen]='\0';
71 }
72 POS_UPDATE(myyyleng,myyytext);
73 verilogalval._lexval=adms_lexval_new(
74 mystrippedstring,
75 root()->_curfilename,
76 root()->_curline,
77 root()->_fpos
78 );
79 free(mystrippedstring);
80 }
81 #ifdef YYDEBUG
82 extern int yydebug;
83 #endif
84
85 %}
86
87 whitespace0 [ \t\v\f]*
88 whitespace [ \t\v\f]+
89 newline \r?\n
90 wn [ \t\v\f\r?\n]
91 wn0 [ \t\v\f\r?\n]*
92 wn1 [ \t\v\f\r?\n]+
93 ident [A-Za-z_][A-Za-z0-9_]*
94 attribute [A-Za-z_][A-Za-z0-9_:.]*
95 attributevalue {wn0}={wn0}{anystring}
96 anystring \"([^\"]|\\\")*\"
97 b8_int 0[0-9]*
98 b10_uint [1-9][0-9]*
99 b16_int 0[xX][0-9A-Fa-f]+
100 float [0-9]*\.[0-9]+([eE][+-]?[0-9]+)?|[0-9]+\.?([eE][+-]?[0-9]+)?
101 char \'[^\']*[\'\n]
102
103 %x insideAttribute
104 %x insideAttributeBegin
105 %x insideAttributeEqual
106 %x insideAttributeValue
107 %x insideAttributeEnd
108 %x insidePragma
109 %option nounput
110
111 %%
112
113 {newline} {
114 adms_admsmain_valueto_curline(root(),root()->_curline+1);
115 adms_admsmain_valueto_fpos(root(),0);
116 }
117
118 ^#{whitespace} {BEGIN(insidePragma);}
119 {whitespace} {POS_UPDATE(yyleng,yytext);}
120
121 <insidePragma>{
122 {anystring} {
123 char*mystrippedstring;
124 int mynewlen=strlen(yytext)-2;
125 assert(mynewlen>=0);
126 mystrippedstring=(char*)malloc(mynewlen+1);
127 if(mystrippedstring)
128 {
129 strncpy(mystrippedstring,yytext+1,mynewlen);
130 mystrippedstring[mynewlen]='\0';
131 }
132 adms_admsmain_valueto_curfilename(root(),mystrippedstring);
133 free(mystrippedstring);
134 }
135 {b10_uint} {
136 adms_admsmain_valueto_curline(root(),adms_strtointeger(yytext));
137 adms_admsmain_valueto_fpos(root(),0);
138 }
139 {newline} {
140 BEGIN(INITIAL);
141 adms_admsmain_valueto_fpos(root(),0);
142 }
143 {whitespace} {POS_UPDATE(yyleng,yytext);}
144 . {
145 adms_message_fatal(("[%s:%i]: inside pragma declaration unexpected character at [%s]\n",root()->_curfilename,root()->_curline,yytext))
146 }
147 }
148
149 {anystring} {TKSTRIPPEDRETURN(yytext,yyleng); return tk_anystring;}
150
151 "(*"{wn0} {BEGIN(insideAttribute); {TKRETURN(yytext,yyleng); return tk_beginattribute;}}
152
153 <insideAttribute>{
154 "*)" {BEGIN(INITIAL);TKRETURN(yytext,yyleng);return tk_endattribute;}
155 {attribute}{attributevalue} {BEGIN(insideAttributeBegin);yyless(0);}
156 . {
157 char myyytext[1000];
158 register int i=0;
159 myyytext[i]=yytext[0];
160 for(;;)
161 {
162 while((myyytext[i]!='*')&&(myyytext[i]!=EOF))
163 {
164 myyytext[++i]=input();
165 }
166 if(myyytext[i]=='*')
167 {
168 while((myyytext[++i]=input())=='*')
169 ;
170 if(myyytext[i]==')')
171 {
172 BEGIN(INITIAL);
173 i-=2;
174 while(myyytext[i]==' ')
175 i--;
176 myyytext[i+1]='\0';
177 POS_UPDATE(yyleng,yytext);
178 verilogalval._lexval=adms_lexval_new(
179 myyytext,
180 root()->_curfilename,
181 root()->_curline,
182 root()->_fpos
183 );
184 return tk_anytext;
185 }
186 }
187 if(myyytext[i]==EOF)
188 {
189 adms_message_fatal(("[%s:%i]: inside Verilog-ams EOF found in attribute declaration [%s]\n",root()->_curfilename,root()->_curline,yytext))
190 }
191 }
192 }
193 }
194 <insideAttributeBegin>{
195 {attribute} {BEGIN(insideAttributeEqual);TKRETURN(yytext,yyleng);return tk_ident;}
196 . {
197 adms_message_fatal(("[%s:%i]: inside Verilog-ams attribute declaration unexpected character at [%s]\n",root()->_curfilename,root()->_curline,yytext))
198 }
199 }
200 <insideAttributeEqual>{
201 {wn0}={wn0} {BEGIN(insideAttributeValue);return '=';}
202 . {
203 adms_message_fatal(("[%s:%i]: inside Verilog-ams attribute declaration unexpected character at [%s]\n",root()->_curfilename,root()->_curline,yytext))
204 }
205 }
206 <insideAttributeValue>{
207 {anystring} {TKSTRIPPEDRETURN(yytext,yyleng);BEGIN(insideAttributeEnd);return tk_anystring;}
208 . {
209 adms_message_fatal(("[%s:%i]: inside Verilog-ams attribute declaration unexpected character at [%s]\n",root()->_curfilename,root()->_curline,yytext))
210 }
211 }
212 <insideAttributeEnd>{
213 {wn0}"*)" {BEGIN(INITIAL);TKRETURN(yytext,yyleng);return tk_endattribute;}
214 {wn1} {BEGIN(insideAttributeBegin);POS_UPDATE(yyleng,yytext);}
215 {wn0},{wn0} {BEGIN(insideAttributeBegin);POS_UPDATE(yyleng,yytext);}
216 {attribute}{attributevalue} {BEGIN(insideAttributeBegin);yyless(0);}
217 . {
218 adms_message_fatal(("[%s:%i]: inside Verilog-ams attribute declaration unexpected character at [%s]\n",root()->_curfilename,root()->_curline,yytext))
219 }
220 }
221
222 parameter {TKRETURN(yytext,yyleng); return tk_parameter;}
223 aliasparameter {TKRETURN(yytext,yyleng); return tk_aliasparameter;}
224 aliasparam {TKRETURN(yytext,yyleng); return tk_aliasparam;}
225 module {TKRETURN(yytext,yyleng); return tk_module;}
226 endmodule {TKRETURN(yytext,yyleng); return tk_endmodule;}
227 function {TKRETURN(yytext,yyleng); return tk_function;}
228 endfunction {TKRETURN(yytext,yyleng); return tk_endfunction;}
229 discipline {TKRETURN(yytext,yyleng); return tk_discipline;}
230 potential {TKRETURN(yytext,yyleng); return tk_potential;}
231 flow {TKRETURN(yytext,yyleng); return tk_flow;}
232 domain {TKRETURN(yytext,yyleng); return tk_domain;}
233 ground {TKRETURN(yytext,yyleng); return tk_ground;}
234 enddiscipline {TKRETURN(yytext,yyleng); return tk_enddiscipline;}
235 nature {TKRETURN(yytext,yyleng); return tk_nature;}
236 endnature {TKRETURN(yytext,yyleng); return tk_endnature;}
237 input {TKRETURN(yytext,yyleng); return tk_input;}
238 output {TKRETURN(yytext,yyleng); return tk_output;}
239 inout {TKRETURN(yytext,yyleng); return tk_inout;}
240 branch {TKRETURN(yytext,yyleng); return tk_branch;}
241 analog {TKRETURN(yytext,yyleng); return tk_analog;}
242 begin {TKRETURN(yytext,yyleng); return tk_begin;}
243 end {TKRETURN(yytext,yyleng); return tk_end;}
244 if {TKRETURN(yytext,yyleng); return tk_if;}
245 while {TKRETURN(yytext,yyleng); return tk_while;}
246 case {TKRETURN(yytext,yyleng); return tk_case;}
247 endcase {TKRETURN(yytext,yyleng); return tk_endcase;}
248 default {TKRETURN(yytext,yyleng); return tk_default;}
249 for {TKRETURN(yytext,yyleng); return tk_for;}
250 else {TKRETURN(yytext,yyleng); return tk_else;}
251 integer {TKRETURN(yytext,yyleng); return tk_integer;}
252 real {TKRETURN(yytext,yyleng); return tk_real;}
253 string {TKRETURN(yytext,yyleng); return tk_string;}
254 from {TKRETURN(yytext,yyleng); return tk_from;}
255 exclude {TKRETURN(yytext,yyleng); return tk_exclude;}
256 inf {TKRETURN(yytext,yyleng); return tk_inf;}
257 INF {TKRETURN(yytext,yyleng); return tk_inf;}
258
259 {ident} {
260 TKRETURN(yytext,yyleng);
261 switch (verilogactx()){
262 case ctx_moduletop:
263 if (adms_admsmain_list_discipline_lookup_by_id(root(),yytext)) {
264 return tk_disc_id;
265 }
266 default:
267 return tk_ident;
268 }
269 }
270
271 \>\> {TKRETURN(yytext,yyleng); return tk_op_shr;}
272 \<\< {TKRETURN(yytext,yyleng); return tk_op_shl;}
273 \&\& {TKRETURN(yytext,yyleng); return tk_and;}
274 \|\| {TKRETURN(yytext,yyleng); return tk_or;}
275 \^\~ {TKRETURN(yytext,yyleng); return tk_bitwise_equr;}
276
277 \${ident} {TKRETURN(yytext,yyleng); return tk_dollar_ident;}
278 {char} {TKSTRIPPEDRETURN(yytext,yyleng); return tk_char;}
279 {b8_int} {TKRETURN(yytext,yyleng); return tk_integer;}
280 {b10_uint} {TKRETURN(yytext,yyleng); return tk_integer;}
281 {b16_int} {TKRETURN(yytext,yyleng); return tk_integer;}
282 {float} {TKRETURN(yytext,yyleng); return tk_number;}
283
284 . {POS_UPDATE(yyleng,yytext);return yytext[0];}
285
286 %%
287
288 int yywrap (void) {return 1;}
289
290 // vim:sw=2:ts=8:noet:
291