1%%%%%%%%%%%%%%%% 2% $Id: simulation.tex,v 1.9 2009/09/01 21:33:42 jpc Exp $ 3% $Log: simulation.tex,v $ 4% Revision 1.9 2009/09/01 21:33:42 jpc 5% Include patches from Fedora (Chitlesh Goorah) and Naohiko Shimizu. 6% 7% Revision 1.8 2009/08/26 12:25:16 jpc 8% Some more adjustments for LaTeX: no more here.sty, rule thickness put 9% after begin{document} for fancyhdr. 10% 11% Revision 1.7 2009/08/26 11:41:55 jpc 12% Replacing fancyheaders by fancyhdr for newer LaTeX's versions. 13% 14% Revision 1.6 2007/12/26 14:55:22 xtof 15% ged rif of old styles 16% 17% Revision 1.5 2004/10/16 12:52:05 fred 18% Erasing the psfig include from the file, changed the font to 10 pt 19% instead of 12 (sparing trees and not being payed by the thickness of 20% my production) and changing font to charter since I got tired of 21% Palatino, sorry Herman! 22% 23%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 24 25%--------------------------------- page style -------------------------------- 26\documentclass{article} 27\usepackage[dvips]{graphics} 28\usepackage[english]{babel} 29\usepackage{setspace} 30\usepackage{fancybox} 31\usepackage{fancyhdr} 32\usepackage{float} 33\usepackage{graphicx} 34%\usepackage{here} 35%\usepackage{isolatin1} 36\usepackage{charter} 37\usepackage{picinpar} 38\usepackage{rotate} 39\usepackage{subfigure} 40\usepackage{sverb} 41\usepackage{t1enc} 42\usepackage{wrapfig} 43 44 45\setlength{\topmargin}{0cm} 46\setlength{\headheight}{1cm} 47\setlength{\textheight}{23cm} 48\setlength{\textwidth}{16cm} 49\setlength{\oddsidemargin}{0cm} 50\setlength{\evensidemargin}{0cm} 51\setlength{\columnsep}{0.125in} 52\setlength{\columnseprule}{0.5pt} 53\setlength{\footskip}{1cm} 54\setstretch{1} 55 56%--------------------------------- styles-------------------------------- 57% 58% Setting the width of the verbatim parts according to 80 tt chars 59% Since it is tt, any char is fine 60% 61\newlength{\verbatimbox} 62\settowidth{\verbatimbox}{\scriptsize\tt 63xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 64} 65 66\newenvironment{sourcelisting} 67 {\VerbatimEnvironment\par\noindent\scriptsize 68 \begin{Sbox}\begin{minipage}{\verbatimbox}\begin{Verbatim}}% 69 {\end{Verbatim}\end{minipage}\end{Sbox} 70 71\setlength{\fboxsep}{3mm}\center\shadowbox{\TheSbox}\normalsize\par\noindent} 72 73\newenvironment{commandline} 74 {\VerbatimEnvironment\par\vspace*{2mm}\noindent\footnotesize 75 \begin{Sbox}\begin{minipage}{.979\textwidth}\begin{Verbatim}}% 76 {\end{Verbatim}\end{minipage}\end{Sbox}\setlength{\shadowsize}{2pt}% 77 \shadowbox{\TheSbox}\normalsize\par\noindent} 78 79\rfoot{\thepage} 80\lfoot{ALLIANCE TUTORIAL} 81\cfoot{} 82 83%--------------------------------- page style -------------------------------- 84\pagestyle{fancy} 85\rhead{VHDL Modeling and simulation} 86\lhead{PART 1} 87\rfoot{\thepage} 88\lfoot{ALLIANCE TUTORIAL} 89\cfoot{} 90 91%---------------------------------- document --------------------------------- 92 93\begin{document} 94\setlength{\footrulewidth}{0.6pt} 95 96\title{ 97 {\Huge ALLIANCE TUTORIAL\\} 98 {\large 99 Pierre \& Marie Curie University \\ 100 2001 - 2004\\ 101 } 102 \vspace{1cm} 103 {\huge 104 PART 1\\ 105 Simulation 106 } 107} 108\date{} 109 110\author{Frederic AK \hspace{2cm} Kai-shing LAM\\ 111Modified by LJ 112} 113 114\maketitle 115 116\begin{figure}[H]\centering 117 \includegraphics[height=7cm]{cpt3.epsi} 118\end{figure} 119 120\begin{figure} 121\end{figure} 122 123\thispagestyle{empty} 124\def\myfbox#1{\vspace*{3mm}\fbox{#1}\vspace{3mm}} 125 126 \vspace{3cm} 127 128 129\newpage 130\large{ The purpose of this tutorial is to provide a quick turn of some { \bf 131ALLIANCE } tools, developed at the LIP6 laboratory of Pierre and Marie Curie 132University. 133 134The tutorial is composed of 3 main parts independent from each other: 135 136\begin{itemize}\itemsep=-.8ex 137\item {VHDL modeling and simulation} 138\item {Logical synthesis} 139\item {Place and route} 140\end{itemize} 141 142Before going further you must ensure that all the environment variables are 143properly set (source alcenv.sh or alcenv.csh file) 144and that the Alliance tools are available when invoking them at the shell 145prompt. 146 147All the tools used in this tutorial are documented at least with a 148manual page. 149 150\newpage 151{\bf Contents}\\ 152\\ 153{1} {\bf Behavioral VHDL} 154 155{1.1} Introduction 156 157{1.2} Behavioral Description 158 159{1.3} Stimuli format 160 161{1.4} Simulation 162 163{1.5} Simulation with Delay\\ 164\\ 165{2} {\bf Structural VHDL} 166 167{2.1} Introduction 168 169{2.2} Stimuli Generation 170 171{2.3} Structural View 172 173{2.4} Structural view and validation of each block 174 175{2.5} Simulation and validation of the addaccu on 2 hierarchical levels 176 177\newpage 178 {\huge 179 PART 1 :\\ } 180 \vspace{1cm} 181 {\huge 182 VHDL modeling and simulation 183 } 184 185All the files used in this part are located in the \\ 186\texttt{/usr/share/doc/alliance-doc-5.0/tutorial/simulation/src} directory.\\ 187This directory contains two subdirectories and one Makefile : 188\begin{itemize} 189\item The Makefile allows you to validate automatically the entire simulation part 190\item {\bf addaccu\_beh} = the behavioral description (Register Transfert Level) 191 192\begin{itemize} 193\item Makefile to validate automatically the entire behavioral description 194\item addaccu.vbe is the behavioral description of addaccu 195\item patterns.pat is the simulation patterns for addaccu 196\item addaccu\_dly.vbe is the behavioral description of addaccu with delay 197\item patterns\_dly.pat is the simulation patterns for addaccu with delay 198\item addaccu4.vhdl is the behavioral description of addaccu using standard VHDL subset 199\end{itemize} 200 201\item {\bf addaccu\_struct} = the structural view 202 203\begin{itemize} 204\item Makefile to validate automatically the entire structural view 205\item pat\_new.c is the vectors generation file 206\item addaccu.vbe is the behavioral description of addaccu 207\item mux.vbe is the behavioral description of multiplexer 208\item accu.vbe is the behavioral description of accumulator 209\item alu.vbe is the behavioral description of adder 210\item addaccu.vst is the structural view of addaccu 211\item mux.vst is the structural view of multiplexer 212\item accu.vst is the structural view of accumulator 213\item alu.vst is the structural view of adder 214\end{itemize} 215 216\end{itemize} 217 218The {\bf ALLIANCE} tools used are : 219\begin{itemize}\itemsep=-.8ex 220\item {\bf vasy} : {\bf VHDL} analyzer and convertor. 221\item {\bf asimut} : {\bf VHDL} Compiler and Simulator. 222\item{\bf genpat} : Procedural generator of stimuli. 223\end{itemize} 224 225You can obtain the detailed informations on an any 226{\bf ALLIANCE} tool by typing the command : 227 228\begin{commandline} 229 > man <tool name> 230\end{commandline} 231 232To validate the behavioral and the structural description you can : 233\begin{itemize} 234\item run the {\bf UNIX} commands in the order indicated by this tutorial. 235\item validate automatically the entire behavioral (or structural) description using the command : 236\end{itemize} 237 238\begin{commandline} 239> make 240\end{commandline} 241If you want to start again this validation from the beginning, 242you just have to type : 243\begin{sourcelisting} 244 > make clean 245 > make 246\end{sourcelisting} 247 248\newpage 249\section{Behavioral VHDL} 250 251\subsection{Introduction} 252 253The goal of this part is to write then to simulate the behavior 254of a very small circuit : 255An accumulating adder which we will call addaccu. 256 257The description of the behavior of addaccu will be made 258in {\bf Behavioral VHDL (DATAFLOW)}. 259 260\subsection{Behavioral Description} 261 262The behavioral description of a circuit consists on a set 263of boolean functions calculating the outputs according to the 264inputs with the use of possible internal signals ; in our case, a 265signal which connects the output of the accumulator to the entry 266of the multiplexer (reg\_out), another which connects the output 267of the multiplexer to the entry of the adder (mux\_out) and 268finally a signal for carry (carry). 269 270At first, you must write the file of behavioral description of addaccu. 271This description must be of type : without delay (without After clause). 272 273This file will have the extension ".vbe" which is the usual extension 274to indicate a {\bf VHDL} behavioral file (Vhdl BEhaviour description). 275This description will have three distinct parts: 276 277\begin{itemize}\itemsep=-.8ex 278\item {\bf Block 1} : The 4 bits adder. 279\item {\bf Block 2} : The 4 bits multiplexer. 280\item {\bf Block 3} : The 4 bits accumulator. 281\end{itemize} 282 283The circuit has the following interface: 284 285\begin{itemize}\itemsep=-.8ex 286\item a 4 bits input bus a. 287\item a 4 bits input bus b. 288\item a 4 bits output bus S. 289\item a clock input signal ck. 290\item a control input signal sel. 291\item two alimentation inputs signals VDD and VSS. 292\end{itemize} 293 294 295\begin{figure}[H] 296 \center 297 \includegraphics[width=.5\textwidth]{addac.eps} 298 \caption{\bf accumulating adder } 299\end{figure} 300 301\begin{enumerate} 302\item {\bf mux } is a 4 bits multiplexer 1 among 2\\ 303 {\bf mux} truth table : \\ 304 sel = 0 => mux\_out = a \\ 305 sel = 1 => mux\_out = reg\_out \\ 306\item {\bf alu} is a 4 bits adder \\ 307 s = b + mux\_out \\ 308\item {\bf accu} is a register (flip-flop) \\ 309 ck = 0 =$>$ reg\_out = reg\_out \\ 310 ck = 1 =$>$ reg\_out = reg\_out \\ 311 ck : 0-$>$1 =$>$ reg\_out = s \\ 312\end{enumerate} 313 314Then you must validate your description while compiling with {\bf ASIMUT}. 315 316\begin{commandline} 317 > asimut -b -c <file name> 318\end{commandline} 319 320\begin{itemize}\itemsep=-.8ex 321\item {\bf file name} is the file name of your behavioral description without 322 extension ({\bf addaccu}). 323\item {\bf -b} option to indicate that the description is purely behavioral. 324\item{\bf -c} option to compile without simulating. 325\end{itemize} 326 327If you do not wish to use the environment variables positioned by 328default, other environment variables can be used by {\bf ASIMUT}. 329 330\begin{sourcelisting} 331 > MBK_WORK_LIB = . 332 > MBK_CATA_LIB = . 333 > MBK_CATAL_NAME = CATAL 334 > MBK_IN_LO = VST 335\end{sourcelisting} 336 337under Bash : 338\begin{sourcelisting} 339 > export var = value 340\end{sourcelisting} 341 342under standard Bourne Shell : 343\begin{sourcelisting} 344 > var = value 345 > export var 346\end{sourcelisting} 347 348under C Shell : 349\begin{sourcelisting} 350 > setenv var value 351\end{sourcelisting} 352 353The meaning of these variables is to be discovered in the {\bf 354man} of {\bf ASIMUT} tool. 355 356\subsection{Description with Standard VHDL subset} 357 358Alliance tools use a very particular and restricted {\bf VHDL} subset (vbe and 359vst file format). 360 361If you want to describe the behavior of your circuit (at Register Transfert Level) 362with a more common {\bf VHDL} subset you can use {\bf VASY} 363to automatically convert your {\bf VHDL} descriptions in 364Alliance subset. 365 366The file addaccu4.vhdl is a description of the addaccu circuit, 367using classical {\bf VHDL} subset (with process statements, 368IEEE 1164 VHDL types, aritmetic operators etc ...) 369 370You can convert this description to the {\bf .vbe} file format using 371 {\bf VASY}~: 372\begin{commandline} 373 > vasy -Vao addaccu4.vhdl 374\end{commandline} 375 376You can then compile and simulate the generated file addaccu4.vbe 377using {\bf asimut} exactly as it has been done with the addaccu.vbe file. 378 379\subsection{Stimuli of test} 380 381Once the behavioral description compiled successfully (without any 382error), to validate your description you must write a file of 383nonexhaustive but intelligent vectors of test. 384 385Therefore you must write a file {\bf patterns.pat} which contains a 386dozen vectors of test. These vectors of test make it possible to 387check that the adder makes the additions well with or without carry propagation , 388that the multiplexer gives the good operand to the input of the adder 389following the value of {\bf sel} signal and finally, that the accumulator 390correctly memorizes the output value of the adder. 391 392In order not to have signals overlapping temporally (phenomenon of 393" glitch "), you will use a clock with very high period (tck = 394100ns) compared to the propagation times. The clock must respect the 395following rate: 1 low state of 50 ns, then 1 high state of 50 ns, 396etc... 397 398If the {\bf PAT} syntax does not appear to you obvious, have a look to the 399man giving the patterns files format : PAT format. 400 401\begin{commandline} 402 > man 5 pat 403\end{commandline} 404 405 406The {\bf 5} refers here to the class of handbooks for files formats. 407 408\begin{itemize}\itemsep=-.8ex 409\item {\bf man 1 } : User Commands. 410\item {\bf man 2,3 } : Libraries. 411\item {\bf man 5 } : Files format. 412\item {\bf man 7 } : Environment variables. 413\end{itemize} 414 415 416\subsection{Simulation} 417 418Now you only have to simulate your addaccu with your vectors of 419tests, without any delay in order to check very quickly that the 420results on the outputs are well those which you wait. 421 422\begin{commandline} 423 > asimut -b addaccu patterns result_vbe 424\end{commandline} 425 426\begin{itemize}\itemsep=-.8ex 427\item {\bf addaccu} : file name of the behavioral description 428 ({\bf addaccu.vbe}). 429\item {\bf pattern} : file name of the vectors ({\bf pattern.pat}). 430\item {\bf result\_vbe} : file name of the patterns result 431 ({\bf result\_vbe.pat}). 432\item {\bf -b} : option to indicate a purely behavioral description. 433\end{itemize} 434 435The file of resulting vectors must be seriously analyzed to check 436the results of simulation. It is possible to use the graphical 437pattern viewer {\bf xpat} to analyze the results of 438the simulation. 439 440\subsection{Delays} 441 442The behavioral description written previously includes only 443zero-delay concurrent assignements. It is however possible to 444specify propagation times by using AFTER clauses, because the 445operations in a real circuit are not done instantaneously. For 446more details, do refer to the man for VBE files format. 447 448You must modify your behavioral description to add delays : 449 450\begin{itemize}\itemsep=-.8ex 451\item For the adder : {\bf 4 ns}. 452\item For the multiplexer : {\bf 2 ns}. 453\item For the accumulator : {\bf 3 ns}. 454\end{itemize} 455 456The installation of the delay for the accumulator requires an 457intermediate signal {\bf reg} because you cannot put delay on a 458signal of {\bf register} type. In the test vectors file, it is 459necessary to put the option {\bf spy} on the signals with delays 460so that we can see these delays. In the contrary case, 461these signals are sampled only at the times of the clock-edge. 462 463Then you must validate this modified behavioral description while simulating 464with { \bf asimut }. 465 466\begin{commandline} 467 > asimut -b addaccu_dly patterns_dly result_dly 468\end{commandline} 469 470 471The results obtained (result\_dly.pat) must be different from 472those obtained without AFTER clauses (result\_vbe.pat). To 473understand why, it is necessary to deeply analyze the temporal 474behavior of your circuit. The step of 50 ns used for the test 475vectors does not really make possible to observe the true 476temporal behavior of your circuit. You can spy on all the 477transitions from an internal signal or an output by specifying 478this characteristic while declaring in the file of 479test vectors (option { \bf spy }, for more details, consult the 480man for patterns files format). 481 482 483\newpage 484\section{Structural VHDL} 485 486\subsection{Introduction} 487 488 489The goal of this part is to write then to simulate in a 490hierarchical way the structural view of the circuit presented in 491first part of this Tutorial. The circuit will be describe in two 492levels of hierarchy : 493 494\begin{itemize}\itemsep=-.8ex 495\item The first level will write the circuit like the instanciation of three blocks. 496\item The second level will write each of the three blocks in term 497of elementary gates of the standard library. 498\end{itemize} 499 500Structural description of addaccu will be made in {\bf STRUCTURAL 501VHDL }. 502 503This part contains five distinct steps: 504\begin{itemize}\itemsep=-.8ex 505\item {\bf step 1} : Generation of the complete set of vectors and validation of the addaccu. 506\item {\bf step 2} : {\bf VHDL} structural description of the addaccu. 507\item {\bf step 3} : Simulation and validation of the structural addaccu 508 on a hierarchical level. 509\item {\bf step 4} : structural description and validation of each block. 510\item {\bf step 5} : Simulation and validation of the structural addaccu 511 on 2 hierarchical levels. 512\end{itemize} 513 514 515\subsection{Stimuli Generation} 516 517Normally, the behavioral description has been successfully compiled, 518and validated with some hand made vectors. 519Now you must create a file of test 520vectors more consequent (a hundred clock-edges). 521 522However, the writing of the stimuli file directly is a tiresome work. 523The tool {\bf genpat} enables you to undertake this work in a 524procedural way. The language {\bf genpat} is a subset of " C " functions. 525For more informations on genpat and the functions of the 526associated library do not hesitate to use the command: 527 528\begin{commandline} 529 > man genpat 530\end{commandline} 531 532Moreover, each basic function from {\bf genpat} has its man, the 533functions are in capital letters, as by example: 534 535\begin{commandline} 536 > man AFFECT 537\end{commandline} 538 539Here are some suggestions for your file of vectors generation : 540 541\begin{itemize}\itemsep=-.8ex 542\item Write a function independent of the management of 543 the clock. This clock will be synchronized on 2 times: 544 a low state of 50 ns followed by a high state of 50 ns. 545\item All the inputs of the circuit must be positioned in the first vector. 546\item Initialize the accumulating register with the function {\bf INIT}. 547\end{itemize} 548 549Once your file {\bf pat\_new.c} is written you must compile it. 550The following commands make it possible to compile the file of 551procedural description and to generate the file of vectors 552pat\_new.pat. 553 554\begin{commandline} 555 > genpat pat_new 556\end{commandline} 557 558If no error has occurred, the file {\bf pat\_new.pat} is now created. 559You only have to simulate your behavioral addaccu 560with this new set of vectors 561 562\begin{commandline} 563 > asimut -b -zerodelay addaccu pat_new res_new 564\end{commandline} 565 566The -zerodelay option states here that you wish a purely boolean 567simulation (without considering the propagation times). You obtain 568then a file of vectors (res\_new.pat) result. 569 570This file will be useful to you for the validation of the next 571stages 572 573\subsection{Structural View} 574 575The objective here is to realize a hierarchy on one level by 576making so that the structural view of the accumulating adder 577addaccu.vst instancies the behavioral description of the 3 basic 578components, the adder alu.vbe, the multiplexer mux.vbe and the 579accumulator accu.vbe. \\ 580Initially you must write the structural 581description file of addaccu. This file will have the extension " 582vst " which is the usual extension to indicate a { \bf VHDL } 583structural file (Vhdl Structural view). This view will contain the 584instanciation of three independent blocks: 585 586\begin{description}\itemsep=-.8ex 587\item[Block 1] : The 4 bits adder. 588\item[Block 2] : The 4 bits Multiplexer. 589\item[Block 3] : The 4 bits accumulator. 590\end{description} 591 592You must create a {\bf CATAL} file containing the identifier of 593each block followed by the attribute 'C' indicating that it is a 594basic element of the hierarchy. This shows you the importance of 595the {\bf CATAL} file which forces the simulator {\bf asimut} to 596use the behavioral sight of the components which are listed. You 597have to set the environment variable MBK\_IN\_LO: 598 599\begin{sourcelisting} 600 > MBK_IN_LO = vst 601 > export MBK_IN_LO 602\end{sourcelisting} 603 604The meaning of all the usable variables is to be discovered in the 605man of { \bf asimut } tool. 606 607Lastly, validate your structural description while compiling with \\ 608{ \bf asimut }. 609 610\begin{commandline} 611 > asimut -c addaccu 612\end{commandline} 613 614Then simulate your circuit with the vectors file obtained 615previously (the res\_new.pat file obtained by simulation 616zero-delay of the behavioral description). 617 618\begin{commandline} 619 > asimut -zerodelay -nores addaccu res_new 620\end{commandline} 621 622The -nores option states here that you do not wait a result file. 623When you do not have any more error of simulation you 624will have to create the structural view of each of the 3 blocks. 625 626\subsection{Structural view and validation of each block} 627 628Now you have to pass to a hierarchy on 2 levels. So it is 629necessary to write a structural view .vst for each basic component 630of the accumulating adder and to test one by one replacing the 631behavioral description of the basic components of the accumulating 632adder by their structural views by modifying the {\bf CATAL} file 633(by removing the component name ). 634 635Each block (alu, accu, mux) must now be described like an 636interconnection of elementary gates. The gates which are to instanciate will 637be chosen among those available in the library of standard cells { 638\bf SXLIB }. For the functionality of the various cells and their 639interface, the sxlib man is available. The behavioral 640description of each cell is present in \\ 641{\bf \$ALLIANCE\_TOP/cells/sxlib }. 642 643You must set the environment variable { \bf MBK\_CATA\_LIB } 644to be able to reach these cells. 645 646\begin{commandline} 647 > MBK_CATA_LIB=\$ALLIANCE\_TOP/cells/sxlib 648 > export MBK_CATA_LIB 649\end{commandline} 650 651For each block adopt following methodology to replace the 652behavioral description of the block by its structural view: 653 654\begin{itemize}\itemsep=-.8ex 655\item Write the structural view of the block { \bf (vst) }. 656\item 657Compile this block (asimut -c $<$block\_name$>$) to validate its 658syntax 659\item Remove its identifier from the { \bf CATAL } file. 660\item Simulate circuit addaccu again: \par 661\end{itemize} 662 663\begin{commandline} 664 > asimut -zerodelay -nores addaccu res_new 665\end{commandline} 666 667\subsection{Simulation and validation of the addaccu on 2 hierarchical levels} 668 669Now you only have to simulate your addaccu described in a 670hierarchical way (in which the basic elements are the library cells). 671 672\begin{itemize}\itemsep=-.8ex 673\item Erase the CATAL file, which is not necessary any more, the library of cells standards having its own catalogue. 674\item Simulate again the addaccu circuit 675\end{itemize} 676 677\begin{commandline} 678 > asimut addaccu pat_new res_dly 679\end{commandline} 680 681 Thus you will have replaced the behavioral description of the three blocks by their structural view. 682\begin{itemize}\itemsep=-.8ex 683\item You can again simulate the addaccu circuit in order to observe its temporal behavior 684 precisely (each cell of the standard library has a given propagation time). 685 You will use the { \bf spy } option for the internal signals and the outputs. 686 687\end{itemize} 688 689\begin{commandline} 690 > asimut addaccu pat_new res_dly 691\end{commandline} 692 693\end{document} 694