1%%%%%%%%%%%%%%%% 2% $Id: synthesis.tex,v 1.8 2009/09/01 21:33:43 jpc Exp $ 3% $Log: synthesis.tex,v $ 4% Revision 1.8 2009/09/01 21:33:43 jpc 5% Include patches from Fedora (Chitlesh Goorah) and Naohiko Shimizu. 6% 7% Revision 1.7 2009/08/26 12:25:16 jpc 8% Some more adjustments for LaTeX: no more here.sty, rule thickness put 9% after begin{document} for fancyhdr. 10% 11% Revision 1.6 2009/08/26 11:41:46 jpc 12% Replacing fancyheaders by fancyhdr for newer LaTeX's versions. 13% 14% Revision 1.5 2007/12/26 14:55:23 xtof 15% ged rif of old styles 16% 17% Revision 1.4 2004/10/16 12:52:17 fred 18% Erasing the psfig include from the file, changed the font to 10 pt 19% instead of 12 (sparing trees and not being payed by the thickness of 20% my production) and changing font to charter since I got tired of 21% Palatino, sorry Herman! 22% 23%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 24\documentclass{article} 25\usepackage[dvips]{graphics} 26\usepackage[english]{babel} 27\usepackage{setspace} 28\usepackage{fancybox} 29\usepackage{fancyhdr} 30\usepackage{float} 31\usepackage{graphicx} 32%\usepackage{here} 33%\usepackage{isolatin1} 34\usepackage{charter} 35\usepackage{picinpar} 36\usepackage{rotate} 37\usepackage{subfigure} 38\usepackage{sverb} 39\usepackage{t1enc} 40\usepackage{wrapfig} 41 42 43\setlength{\topmargin}{0cm} 44\setlength{\headheight}{1cm} 45\setlength{\textheight}{23cm} 46\setlength{\textwidth}{16cm} 47\setlength{\oddsidemargin}{0cm} 48\setlength{\evensidemargin}{0cm} 49\setlength{\columnsep}{0.125in} 50\setlength{\columnseprule}{0.5pt} 51\setlength{\footskip}{1cm} 52\setstretch{1} 53 54 55%--------------------------------- styles 56%-------------------------------- 57% 58% Setting the width of the verbatim parts according to 80 tt chars 59% Since it is tt, any char is fine 60% 61\newlength{\verbatimbox} 62\settowidth{\verbatimbox}{\scriptsize\tt 63xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 64} 65 66\newenvironment{sourcelisting} 67 {\VerbatimEnvironment\par\noindent\scriptsize 68 \begin{Sbox}\begin{minipage}{\verbatimbox}\begin{Verbatim}}% 69 {\end{Verbatim}\end{minipage}\end{Sbox} 70 71\setlength{\fboxsep}{3mm}\center\shadowbox{\TheSbox}\normalsize\par\noindent} 72 73\newenvironment{commandline} 74 {\VerbatimEnvironment\par\vspace*{2mm}\noindent\footnotesize 75 \begin{Sbox}\begin{minipage}{.979\textwidth}\begin{Verbatim}}% 76 {\end{Verbatim}\end{minipage}\end{Sbox}\setlength{\shadowsize}{2pt}% 77 \shadowbox{\TheSbox}\normalsize\par\noindent} 78 79\pagestyle{fancy} 80\rhead{Logic synthesis} 81\lhead{PART 2} 82\rfoot{\thepage} 83\lfoot{ALLIANCE TUTORIAL} 84\cfoot{} 85 86%---------------------------------- document --------------------------------- 87\begin{document} 88\setlength{\footrulewidth}{0.6pt} 89 90\title{ 91 {\Huge ALLIANCE TUTORIAL\\} 92 {\large 93 Pierre \& Marie Curie University \\ 94 2001 - 2004\\ 95 } 96 \vspace{1cm} 97 {\huge 98 PART 2\\ 99 Logic synthesis 100 } 101} 102\date{} 103\author{ 104 Ak Frederic\hspace{2cm} Lam Kai-shing\\ 105Modified by LJ 106} 107 108\maketitle 109 110\begin{figure}[H]\centering 111 \includegraphics[height=7cm]{amd2901.epsi} 112\end{figure} 113 114\begin{figure} 115\end{figure} 116 117\thispagestyle{empty} 118\def\myfbox#1{\vspace*{3mm}\fbox{#1}\vspace{3mm}} 119 120\newpage 121\large{ The purpose of this tutorial is to provide a quick turn of some { \bf 122ALLIANCE } tools, developed at the LIP6 laboratory of Pierre and Marie Curie 123University. 124 125The tutorial is composed of 3 main parts independent from each other: 126 127\begin{itemize}\itemsep=-.8ex 128\item {VHDL modeling and simulation} 129\item {Logic synthesis} 130\item {Place and route} 131\end{itemize} 132 133Before going further you must ensure that all the environment variables are 134properly set (source alcenv.sh or alcenv.csh file) 135and that the Alliance tools are available when invoking them at the shell 136prompt. 137 138All tools used in this tutorial are documented at least with a 139manual page. 140 141\newpage 142{\bf Contents}\\ 143\\ 144 {1} {\bf Introduction} 145\\ 146 {2} {\bf Finite states machine Synthesis} 147 148 {2.1} Introduction 149 150 {2.2} MOORE and MEALY automatons 151 152 {2.3} SYF and VHDL 153 154 {2.4} Example 155 156 {2.5} Step to follow 157\\ 158 {3} {\bf Automat for digicode} 159 160 {3.1} Step to follow 161\\ 162 {4} {\bf Logic synthesis and structural optimization} 163 164 {4.1} Introduction 165 166\hspace{0.5cm} {4.1.1} Logic synthesis 167 168\hspace{0.5cm} {4.1.2} Solve fan-out problems 169 170\hspace{0.5cm} {4.1.3} Long path visualization 171 172\hspace{0.5cm} {4.1.4} Netlist Checking 173 174\hspace{0.5cm} {4.1.5} Scan-path insertion 175 176 {4.2} Step to follow 177 178\hspace{0.5cm} {4.2.1} {\it Mapping} on predefined cells 179 180\hspace{0.5cm} {4.2.2} Netlist visualization 181 182\hspace{0.5cm} {4.2.3} Boolean network optimization 183 184\hspace{0.5cm} {4.2.4} Netlist optimization 185 186\hspace{0.5cm} {4.2.5} Netlist checking 187 188\hspace{0.5cm} {4.2.6} Scan-path insertion in the netlist 189\\ 190 {5} {\bf AMD 2901} 191 192 {5.1} exercise 193 194 {5.2} step to follow 195 196 {5.3} error found 197\\ 198 {6} {\bf AMD2901 structure} 199\\ 200 {7} {\bf Part controls design } 201 202 {7.1}{ \bf genlib } description example 203 204 {7.2} provided files checking 205 206 {7.3} Part controls description 207\\ 208 {8} {\bf Data-path design} 209 210 {8.1} Example of description with genlib macro-functions 211 212 {8.2} Data-path description 213\\ 214{9} {\bf The { \it Makefile } or how to manage tasks dependency } 215 216 {9.1.1} Rules 217 218 {9.1.2} models Rules 219 220 {9.1.3} Variables definitions 221 222 {9.1.4} Predefined variables 223\\ 224 {10} {\bf Appendix: Diagrams as an indication but not-in conformity with the behavioral} 225 226 227\newpage 228 {\huge 229 PART 2 :\\ } 230 \vspace{1cm} 231 {\huge 232 Logic Synthesis 233 } 234 235All the files used in this part are located under \\ 236\texttt{/usr/share/doc/alliance-doc-5.0/tutorials/synthesis/src} directory.\\ 237This directory contents four subdirectories and one Makefile : 238\begin{itemize}\itemsep=-.8ex 239 240\item Makefile 241\item amdbug 242 \begin{itemize}\itemsep=-.8ex 243 \item Makefile 244 \item amdfindbug.pat : tests file 245 \item several files amd.vbe : behavioral description 246 \end{itemize} 247\item counter 248 \begin{itemize}\itemsep=-.8ex 249 \item Makefile 250 \item cpt5.fsm : description in fsm 251 \item cpt5.pat : tests file 252 \end{itemize} 253\item digicode 254 \begin{itemize}\itemsep=-.8ex 255 \item Makefile 256 \item digicode.fsm : description in fsm 257 \item paramfile.lax : use to modify the fan-out 258 \item digicode.pat : tests file 259 \item scan.path : make it possible to observe registers 260 contents 261 \end{itemize} 262\item amd2901 263 \begin{itemize}\itemsep=-.8ex 264 \item Makefile 265 \item amd2901\_ctl.vbe : behavioral description of control 266 part 267 \item amd2901\_dpt.vbe : behavioral description of data-path 268 \item amd2901\_ctl.c : file .c of control part 269 \item amd2901\_dpt.c : file .c of data-path 270 \item amd2901\_core.c : file .c of heart 271 \item amd2901\_chip.c : file .c of the circuit with their 272 pads 273 \item pattern.pat : tests file 274 \end{itemize} 275\end{itemize} 276 277 278\newpage 279\section{Introduction} 280%--------------------- 281 The goal of this section is to present some ALLIANCE tools which are: 282 283\begin{itemize}\itemsep=-.8ex 284\item Logic synthesis tools { \bf SYF, BOOM, BOOG, LOON, SCAPIN }; 285\item Data-path generation tool{\bf GENLIB }; 286\item { \it netlist } graphical viewer { \bf XSCH }; 287\item formal proof Tools {\bf FLATBEH, PROOF}; 288\item The simulator { \bf ASIMUT }; 289\end{itemize} 290 291The first two sections will relate to the { \it netlist } { \bf 292generation and validation } methods of predefined cells. Indeed, 293even if it is acquired that the tools for ALLIANCE generation 294function correctly, the validation of each generated view is { \bf 295essential }. It makes it possible to limit 296the cost and the time of the design. \\ 297The two other sections will be reserved for the { \bf data-path 298generation and the control part } of AMD2901. 299 300\section{Finite states machine Synthesis} 301 302\subsection{Introduction} 303 304A pure combinatorial circuit has no internal registers. So 305its outputs depend only on its primary inputs. On the contrary 306a synchronous sequential circuit having internal registers sees its 307outputs changing according to its inputs but also memorized values 308in its registers. As consequence, the circuit state at the moment 309t+1 also depends on its state at the moment t. This type of 310circuit can be formally modelized as a { \bf finite states machine}. 311 312\begin{figure}[H]\centering 313 \includegraphics[width=9cm]{ex_digicode.eps} 314 \caption{Automat} 315 \label{Fig:ex_digicode} 316\end{figure} 317 318\subsection{MOORE and MEALY automaton} 319%--------------------------------------- 320The MOORE automaton sees the state of its outputs changing only on 321clock-edges. The inputs can thus move between two clock-edges 322without modifying the outputs. But in the case of MEALY automaton, 323the variation of the inputs can modify at any time the value of 324the outputs. It will be essential to separate the generation 325function from the transition function (Moore automaton). 326Two distinct processes will then modelize the next state computation 327and the current state register update. 328 329\begin{figure}[H]\centering 330 \includegraphics[width=15cm]{automate.eps} 331 \caption{Automats} 332 \label{Fig:automaton} 333\end{figure} 334 335 336\subsection{SYF and VHDL} 337%----------------------- 338In order to describe the automatons, we use a particular {\bf VHDL } 339style description that defines architecture "FSM" ({ \bf 340F}inite-{\bf S}tate { \bf M}achine). 341 342The corresponding file also has the extension { \bf fsm }. From 343this file, the tool { \bf SYF } makes the automaton synthesis and 344after state encoding, it transforms this abstracted automaton into 345a Boolean network and a state register. 346{ \bf SYF } then generates a { \bf VHDL } file using the 347{\bf vbe } subset. 348Like most of all tools used in alliance, it is 349necessary to set some variables before using { \bf SYF }. 350You can refer to the { \bf man } page of { \bf syf } for more details. 351 352\subsection{Example} 353%------------------- 354 355In order to take in hand the particular syntax of a { 356\bf fsm } file, an example of { \bf three } successive "1" counter 357is presented. Its vocation is to detect for example on a 358connection series, a sequence of { \bf three } successive "1" counter. 359The state graph is represented on the figure 360\ref{Fig:graphe1}.\\ 361The { \bf fsm } format is detailed in the man page { \bf fsm(5) }. 362 363\begin{sourcelisting} 364 entity circuit is 365 port ( 366 ck, i, reset, vdd, vss : in bit; 367 o : out bit 368 ); 369 end circuit; 370 architecture MOORE of circuit is 371 type ETAT _TYPE is (E0, E1, E2, E3); 372 signal EF, EP : ETAT _TYPE; 373- - pragma CURRENT _STATE EP 374- - pragma NEXT _STATE EF 375- - pragma CLOCK CK 376 begin 377 process (EP, i, reset) 378 begin 379 if (reset='1') then 380 EF<=E0; 381 else 382 case EP is 383 when E0 = 384 if (i='1') then 385 EF <= E1; 386 else 387 EF <= E0; 388 end if; 389 when E1 = 390 if (i='1') then 391 EF <= E2; 392 else 393 EF <= E0; 394 end if; 395 when E2 = 396 if (i='1') then 397 EF <= E3; 398 else 399 EF <= E0; 400 end if; 401 when E3 = 402 if (i='1') then 403 EF <= E3; 404 else 405 EF <= E0; 406 end if; 407 when others = assert ('1') 408 report "etat illegal"; 409 end case; 410 end if; 411 case EP is 412 when E0 = 413 o <= '0' ; 414 when E1 = 415 o <= '0' ; 416 when E2 = 417 o <= '0' ; 418 when E3 = 419 o <= '1' ; 420 when others = assert ('1') 421 report "etat illegal"; 422 end case; 423 end process; 424 process(ck) 425 begin 426 if (ck='1' and not ck'stable) then 427 EP <= EF; 428 end if; 429 end process; 430 end MOORE; 431\end{sourcelisting} 432 433\begin{figure}[H]\centering 434 \includegraphics[height=8cm]{graphe1.eps} 435 \caption{states graph of three successive "1" counter} 436 \label{Fig:graphe1} 437\end{figure} 438 439 440\subsection{Step to follow} 441%--------------------------------- 442 443Now you can use this example to write the description of a { \bf five } successive "1" 444counter in a{\bf Moore } automaton. 445 446\begin{itemize}\itemsep=-.8ex 447\item position the environment variables . \item launch { \bf 448SYF } with the coding options { \bf -a, -J, -m, -O, -R } 449 and by using the options { \bf -CEV }. \ \ 450 451 -a Uses "Asp" as encoding algorithm. 452 453 -j Uses "Jedi" as encoding algorithm. 454 455 -m Uses "Mustang" as encoding algorithm. 456 457 -o Uses the one hot encoding algorithm. 458 459 -r Uses distinct random numbers for state encoding. 460 461\begin{commandline} 462> syf -CEV -a <fsm_source> 463\end{commandline} 464\item visualize the files { \bf enc }. Those files contains one state 465 name followed by its hexadecimal code value. 466 467\item write stimuli (test vectors) and simulate with { \bf ASIMUT }. 468\end{itemize} 469 470%\subsection{Utilisation d'un chemin de test ({\it scan-path}\/)} 471%------------------------------------------------------- 472% Pour ins\'erer automatiquement un chemin de scan qui permet 473%d'observer en mode test le contenu de tous les registres du circuit, il 474%faut ajouter au fichier {\bf .fsm} les commandes suivantes:\\ 475% 476%\begin{itemize}\itemsep=-.8ex 477%\item ajouter les connecteurs n\'ecessaires au {\it scan-path}\/ par exemple:\\ 478% \\ 479% test : in bit\\ 480% scanin : in bit\\ 481% scanout : out bit\\ 482%\item ajouter les pragmas n\'ecessaires au {\it scan-path}\/ par exemple:\\ 483% \\ 484% - -pragma SCAN\_TEST test\\ 485% - -pragma SCAN\_IN scanin\\ 486% - -pragma SCAN\_OUT scanout 487%\item Choisir un codage et relancer {\bf SYF} avec l'option {\bf -P} 488% qui ajoute le {\it scan-path}\/. 489%\item Ecrire un fichier de vecteurs de test permettant de v\'erifier le 490% fonctionnement du {\it scan-path}\ et simuler sous {\bf ASIMUT}. 491%\end{itemize} 492% 493 494\newpage 495 496\section{Automaton for digicode} 497%------------------------------- 498 499We want to design a digicode circuit whose keyboard is 500represented on the figure \ref{Fig:keyboard}. 501The specifications are as follows: 502 503\begin{figure}[H]\centering 504 \includegraphics[width=7cm,height=7cm]{clavier.eps} 505 \caption{Clavier} 506 \label{Fig:keyboard} 507\end{figure} 508 509\begin{itemize}\itemsep=-.8ex 510\item The numbers from 0 to 9 are coded in natural binary on 4 bits. 511 A and B are coded in the following way: 512 \begin{itemize}\itemsep=-.8ex 513 \item A: 1010 514 \item B: 1011 515 \end{itemize} 516\item The digicode works in two modes: 517 \begin{itemize}\itemsep=-.8ex 518 \item Day Mode: The door opens while pressing on "O" or if entering the good code 519 \item Night Mode: The door opens only if the code is correct. 520 \end{itemize} 521 To distinguish the two cases an external "timer" calculates the signal { \bf day} 522 which is equal to ' 1 ' between 8h00 and 20h00 and ' 0 ' otherwise. 523\item The digicode order an alarm as soon as one of the entered 524numbers is not the good. \item The digicode automaton returns in 525idle state if nothing 526 returned to the keyboard at the end of 5 seconds 527 or if alarm sounded during 2mn - signal { \it \bf reset } -. For that it receives a signal 528 from { \bf reset } external timer. 529\item The chip works at 10MHz. 530\item Any pressure of a key of the keyboard is then followed by the signal { \it \bf press\_kbd }. 531 This one announces to the chip that the output data of the 532 keyboard is valid. This signal is set to 1 during a clock-edge. 533\end{itemize} 534 535The code is { \bf 53A17 } (but you can take the code who agrees to 536you). The interface of this automaton is as follows: 537 538\begin{itemize}\itemsep=-.8ex 539\item in {\bf ck} 540\item in {\bf reset} 541\item in {\bf day} 542\item in {\bf i[3:0]} 543\item in {\bf O} 544\item in {\bf press\_kbd} 545\item out {\bf door} 546\item out {\bf alarm} 547\end{itemize} 548 549 550\begin{figure}[H]\centering 551 \includegraphics[height=8cm]{graphe_solution_digicode.eps} 552 \caption{Digicode states graph} 553 \label{Fig:graph 2} 554\end{figure} 555 556\subsection{Step to follow} 557%--------------------------------- 558 559\begin{itemize}\itemsep=-.8ex 560\item draw the states graph. 561\item describe it in the { \bf fsm } format . 562\item synthesize your description with { \bf SYF } using 563 different state encoding algorithms 564 { \bf -a, -j, -m, -o, -r } and by using the options { \bf -CEV}.\\ 565\begin{commandline} 566> syf -CEV -a <fsm_source> 567\end{commandline} 568\item write stimuli (test vectors). 569\item simulate with { \bf ASIMUT } all the resulting {\bf vbe} descriptions. 570\end{itemize} 571 572\newpage 573%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 574 575\section{Logic synthesis and structural optimization} 576%-------------------------------------------------------- 577 578\subsection{Introduction} 579%------------------------ 580 581\subsubsection{Logic synthesis} 582%--------------------------------- 583 The logic synthesis permits to obtain a { \it netlist } of 584 gates given a Boolean network (format { \bf vbe }). 585 Several tools are available: 586 587\begin{itemize}\itemsep=-.8ex 588\item The tool { \bf BOOM } allows the Boolean network optimization before mapping with { \bf BOOG }. 589\item The tool { \bf BOOG } synthesizes a { \it netlist } by using a library 590 with predefined cells such as { \bf SXLIB }. 591 The { \it netlist } can be either with the format { \bf vst } or with the format { \bf al }. 592 Check the environment variable { \bf MBK\_OUT\_LO}=vst. 593\end{itemize}\itemsep=-.8ex 594 595\subsubsection{Solve fan-out problems } 596%----------------------------------------------------- 597 Generated { \it netlist}\/s may contain internal signals that drive a 598 significant number of gates (large FAN-OUT). 599 In order to solve this problem, the tool 600 { \bf LOON } replaces the cells having a too large fan-out by more powerful 601 cells and/or insert buffers. 602 603\subsubsection{Long path visualization } 604%----------------------------------------------------- 605 At any moment, the { \it netlist}\/s can be graphically displayed using {\bf XSCH}. 606This tool permits also to highlight the longest path on the schematic thanks to the files { \bf 607xsc } and { \bf vst } generated by { \bf BOOG } and { \bf LOON }. 608 609\begin{figure}[H]\centering 610 \includegraphics[]{T_RC.eps} 611 \caption{Simplified timing diagram } 612 \label{Fig:T_RC} 613\end{figure} 614 615Equivalent resistor { \it R } of the { \it figure \ref{Fig:T_RC} } 616is calculated on the totality of the transistors of the { \it AND 617} belonging to the active way. In the same way, the capacity { \it 618C } is calculated on the busy transistors of the { \it NOR } 619corresponding to the way between { \it i0 } and the output of the 620cell. 621 622\subsubsection{Netlist Checking} 623%----------------------------------------------------- 624 The netlist must be validated. For that, you have { \bf ASIMUT }, 625 but also the tool { \bf PROOF } which proceeds to a formal comparison of two behavioral 626 descriptions ({ \bf vbe }). The tool { \bf FLATBEH } is usefull to obtain a 627 new behavioral file starting from a { \it netlist } 628 (given a {\bf vbe} file for each leave cells of the hierarchy). 629 630\subsubsection{Scan-path insertion} 631%----------------------------------------------------- 632 With { \bf SCAPIN } we can insert a scan-path into the netlist. 633 The scan-path allow the designer to observe in test mode the value of all registers of your circuit. 634 The path is created by changing each registers into a mux\_register (or by inserting a multiplexer 635 in front of all registers). 636 637\newpage 638 639\subsection{Step to follow} 640%--------------------------------- 641 642\subsubsection{{\it Mapping} on predefined cells} 643%---------------------------------------------------------- 644 For each Boolean network obtained previously: 645 646\begin{itemize}\itemsep=-.8ex 647\item set properly environment variables; 648\item synthesize the structural view: 649\begin{commandline} 650> boog <vbe_source> 651\end{commandline} 652\item launch { \bf BOOG } on different {\it netlist}\/s to observe {\bf SYF} 653 options influence (different state encoding technics). 654\item validate the work of { \bf BOOG } with { \bf ASIMUT }, 655 the { \it netlist}\/s obtained with stimuli which were used to 656 validate the initial Boolean network. 657\end{itemize}\itemsep=-.8ex 658 659\subsubsection{Netlist visualization} 660%---------------------------------------------------------- 661 662\begin{itemize}\itemsep=-.8ex 663\item The longest path (critical path) is described in the { \bf xsc } file produced 664 by { \bf boog }. 665 The { \bf XSCH } tool will use it to highlight this path on the schematic. 666 To launch the graphical schematic viewer: 667\begin{commandline} 668>xsch -I vst -l <vst_source> 669\end{commandline} 670\item The red color indicates the critical path. 671\item you can use the option '{ \it -slide }' followed by netlist names to display one by one a set of 672 schematics. 673 The keys ' { \it + } ' and ' { \it - }' can then be used to display respectively next and previous 674 netlist. 675\end{itemize}\itemsep=-.8ex 676 677 678\subsubsection{Boolean network optimization} 679%------------------------------------------------- 680 To analyze Boolean optimization effect : 681 682\begin{itemize}\itemsep=-.8ex 683\item launch Boolean optimization with the tool { \bf BOOM } 684 by asking an optimization in { \bf surface } then in { \bf delay } ; 685\begin{commandline} 686>boom -V <vbe_source> <vbe_destination> 687\end{commandline} 688 689\item test { \bf BOOM } with the various algorithms - S, - J, - 690B, - G, - p..., the options specifie which algorithm has to be used for the boolean optimization. 691 692\item compare the literal number after factorization. \item 693remake the Boolean networks synthesis with the tool { \bf BOOG } 694 and compare the results. 695\end{itemize} 696 697\subsubsection{Netlist optimization } 698%------------------- 699 For all the structural view obtained previously: 700\begin{itemize}\itemsep=-.8ex 701\item launch { \bf LOON } with the command: 702\begin{commandline} 703>loon <vst_source> <vst_destination> <lax_param> 704\end{commandline} 705\item carry out an fanout optimization by modifying the fanout 706factor in the option file { \bf .lax }.The optimization mode and level are able to be change in this file. 707 \item impose capacities 708values on the outputs. 709\end{itemize} 710 711\subsubsection{Netlist checking} 712%------------------- 713 to carry out on the best of your { \it netlist}\/s: 714 715\begin{itemize}\itemsep=-.8ex 716\item validate the work of { \bf LOON } by running { \bf ASIMUT } 717 on the different { \it netlist}\/s obtained, using the stimuli 718 that were defined to validate the initial behavioral view. 719\item Make a formal comparison of your netlist with 720 the original behavioral file resulting from { \bf SYF }: 721\begin{commandline} 722>flatbeh <vst_source> <vbe_dest> 723\end{commandline} 724\begin{commandline} 725>proof -d <vbe_origin> <vbe_dest> 726\end{commandline} 727\end{itemize} 728 729Checks if the files are formally identicals. 730 731\subsubsection{Scan-path insertion in the netlist} 732%------------------- 733 to carry out on the best of your { \it netlist}\/s: 734 735\begin{itemize}\itemsep=-.8ex 736\item insert a scan-path connecting all the digicode registers. 737\begin{commandline} 738>scapin -VRB <vst_source> <path_file> <vst_dest> 739\end{commandline} 740 741\newpage 742 743\# Example of .path file 744\begin{sourcelisting} 745BEGIN_PATH_REG 746 747cs_0 748cs_1 749cs_2 750END_PATH_REG 751 752BEGIN_CONNECTOR 753 754SCAN_IN scin 755SCAN_OUT scout 756SCAN_TEST test 757END_CONNECTOR 758\end{sourcelisting} 759\item build ten patterns to test the scan-path and simulate with 760{ \bf ASIMUT }. 761\end{itemize}\itemsep=-.8ex 762 763\newpage 764\section{AMD 2901} 765 766\subsection{exercise} 767 768First of all, here is an exercise to understand the AMD2901 769chip functionality. The goal is to design it 770using Alliance, as described in the following parts of 771this tutorial. 772 773To explore all functionalities, you will have 774to validate the behavioral view that will be provided. 775All needed informations will be find in appendix. 776 777The validation will have to be done using stimuli 778generated by {\bf genpat}. The vectors must be carefully written 779to enable you to detect { \bf BUG } in your behavioral file { \bf .vbe }. 780Approximately 500 patterns will be enough for debugging your AMD 2901. 781 782\subsection{step to follow} 783It is necessary to generate stimuli that tests all the parts and all functions 784of the AMD following the specifications described in the documentation. 785 786\begin{itemize}\itemsep=-.8ex 787\item filling and reading the 16 boxes memories of the RAM . 788\item test the RAM shifter 789\item filling and reading of the accumulator. 790\item test the accumulator shifter . 791\item test the arithmetic and logic operations 792 (addition, subtraction, overflow, carry, propagation, etc...) . 793\item exhaustive test of the inputs conditioned by I[2:0]. 794\item data-path test vectors 795\end{itemize} 796 797\subsection{error found} 798 799You can notice that for the RAM shifter values "101" and "111" of 800i[8:6], the AMD causes a shift of the accumulator that should not 801take place. 802 803for the values "000" and "001" of i[8:6], the circuit writes the 804ALU output in RAM . 805 806The AMD carries out the operation R xor S for 807I[5:3]=111 instead of carrying out the operation for I[5:3]=110. 808 809It carries out the operation /(R Xor S) for I[5:3]=110 instead of 810I[5:3]=111. 811 812\newpage 813\section{AMD2901 structure} 814 815 816We break up Amd2901 into 2 blocks: %la partie cont\^ole qui regroupe la ``glu'' logique et la partie op\'erative (chemin de donn\'ees).% 817\begin{figure}[H]\center 818\leavevmode 819\includegraphics[width=10cm]{bloc} 820\caption{Amd2901 Organization \label{bloc}} 821\end{figure} 822 823 824\begin{itemize}\itemsep=-.8ex 825\item The data-path contains the Amd2901 regular parts , the 826registers and the arithmetic logic unit. 827\item The control part contains irregular logic, 828 the instructions decoding and the flags computation. 829\end{itemize} 830 831\newpage 832We will use the following hierarchical description: 833\begin{figure}[H]\center 834\leavevmode 835\includegraphics[width=10cm]{hier} 836\caption{Hierarchy \label{hier}} 837\end{figure} 838 839The provided files are as follows:\\ 840\begin{itemize}\itemsep=-.8ex 841\item amd2901\_ctl.vbe, behavioral description of the part 842controls \item amd2901\_dpt.vbe, behavioral description of the 843part data-path \item amd2901\_ctl.c, file { \bf C } of the part 844controls \item amd2901\_dpt.c, file { \bf C } of the part of data 845path \item amd2901\_core.c, file { \bf C } of the heart \item 846amd2901\_chip.c, file { \bf C } of the circuit containing the pads 847\item pattern.pat, tests file \item CATAL, file listing the 848behavioral files, to be modify \item Makefile, to automate the 849generation 850\end{itemize} 851 852 853%%%%%%%%%%%%%%%%%%%% 854 855 856\newpage 857\section{Part controls design } 858 859 860This part of irregular logic will be carried out with the cells of the library {\bf SXLIB}.\\ 861\\ 862Description in VHDL netlist (i.e { \it .vst }) of the various 863gates hazardous when the circuit contain 864several thousands of them. there exists a tool for procedural 865signals lists generation , { \bf genlib }. It is then enough to 866describe in C using macro-functions the { \it signals list } in 867gates of the block. The library of macro-functions C is called { 868\bf genlib }. The { \bf genlib } execution produces a description 869VHDL with the format { \it .VST }. For more details, consult the 870manual (man) on { \bf genlib }. 871 872\subsection{{ \bf genlib } description example } 873 874here a simple circuit: 875 876\begin{figure}[H]\center 877\leavevmode 878\includegraphics[width=10cm]{exemple1} 879\end{figure} 880 881The equivalent { \bf genlib } file is as follows: 882 883\begin{sourcelisting} 884#include <genlib.h> 885 main() 886 { 887 GENLIB_DEF_LOFIG("circuit"); 888 889 /* Connectors declaration */ 890 GENLIB_LOCON("a",IN,"a1"); 891 GENLIB_LOCON("b",IN,"b1"); 892 GENLIB_LOCON("c",IN,"c1"); 893 GENLIB_LOCON("d",IN,"d1"); 894 GENLIB_LOCON("e",IN,"e1"); 895 GENLIB_LOCON("s",OUT,"s1"); 896 897 GENLIB_LOCON("vdd",IN,"vdd"); 898 GENLIB_LOCON("vss",IN,"vss"); 899 900 /* Combinatorial gates instanciation */ 901 GENLIB_LOINS("na2_x1","nand2","a1","c1","f1","vdd","vss",0); 902 GENLIB_LOINS("no2_x1","nor2","b1","e1","g1","vdd","vss",0); 903 GENLIB_LOINS("o2_x2","or2","d1","f1","h1","vdd","vss",0); 904 GENLIB_LOINS("inv_x1","inv","g1","i1","vdd","vss",0); 905 GENLIB_LOINS("a2_x2","and2","h1","i1","s1","vdd","vss",0); 906 907 /* Save of the figure */ 908 GENLIB_SAVE_LOFIG(); 909 exit(0); 910 } 911\end{sourcelisting} 912 913Save it under the name `` circuit.c '' then compile the file with 914the command : \ 915\begin{commandline} 916> genlib circuit 917\end{commandline} 918 919You obtain the file `` circuit.vst ''. (if is not it, it may be 920due to environment variables that are not properly set for { \bf genlib }). 921 922\subsection{provided files checking} 923Create the file { \bf CATAL } in your simulation directory . It 924must contain the following lines: 925\ \\ 926\begin{commandline} 927amd2901_ctl C 928amd2901_dpt C 929\end{commandline} 930 931It makes the simulator use the 932behavioral files (.vbe) of `` amd2901\_ctl '' and of `` amd2901\_dpt ' '. \\ 933 934\begin{commandline} 935> asimut amd2901_chip pattern result 936\end{commandline} 937 938You can verify the resulting patterns by using { \bf xpat } on the file `` 939result ''. 940 941\subsection{Part controls description } 942 943The diagrams corresponding to the signals list to design are 944provided to you. %To supplement the file `` amd2901\_ctl.c '' then 945compile it by using the steps below. \\ 946 947%Positionner les variables d'environnement sp\'ecifiant les formats des diff\'erentes vues ainsi que les librairies de cellules utilis\'ees.\\ 948% 949%\myfbox{ 950%\shortstack[l]{ 951%{\bf $>$ setenv VH\_MAXERR 10}\\ 952%{\bf $>$ setenv VH\_BEHSFX vbe}\\ 953%{\bf $>$ setenv VH\_PATSFX pat}\\ 954%{\bf $>$ setenv VH\_LIBLST .}\\ 955%{\bf $>$ setenv MBK\_WORK\_LIB .}\\ 956%{\bf $>$ setenv MBK\_CATA\_LIB .:\$ALLIANCE\_TOP/cells/sxlib:}\\ 957%{\bf \$ALLIANCE\_TOP/cells/padlib}\\ 958%{\bf $>$ setenv MBK\_CATAL\_NAME CATAL}\\ 959%{\bf $>$ setenv MBK\_IN\_LO vst}\\ 960%{\bf $>$ setenv MBK\_OUT\_LO vst}\\ 961%{\bf $>$ setenv MBK\_IN\_PH ap}\\ 962%{\bf $>$ setenv MBK\_OUT\_PH ap} 963%} 964%}\\ 965 966Generate the signals list { \bf vst } starting from the file { \bf 967c } by the command: 968\begin{commandline} 969> genlib amd2901_ctl 970\end{commandline} 971 972Then validate the structural view obtained by simulating the 973complete circuit with the tests vectors which are provided to you. 974Replace the behavioral view of the part controls by his structural 975view by removing the name { \it amd2901\_ctl } of { \bf CATAL } 976file. 977 978\begin{commandline} 979> asimut -zerodelay amd2901_chip vecteurs result 980\end{commandline} 981 982Note that one carries out a simulation `` without delay '' of the netlist. In the event 983of problem, do not hesitate to use { \bf xpat }. 984 985\begin{commandline} 986> asimut amd2901_chip pattern result 987\end{commandline} 988 989After having validated the functional behavior of the netlist, 990simulate it using propagation delays. 991Modify time values between the patterns. Indeed, { 992\bf asimut } is able to evaluate the propagation times for each 993cell of the netlist (taken into account the "after" clauses 994specify in vbe files). 995 996%%%%%%%%%%%%%%%%%%%% 997 998\newpage 999\section{Data-path design} 1000The data path is formed by the regular logic of the circuit. In 1001order to benefit from this regularity, we generates the signals 1002list in the vectorial operators form (or columns) { \it via } the 1003macro-functions of the tool { \bf genlib } . That makes it 1004possible to save place by using several times the same material . 1005For example, the { \it NOT } of a mux of { \it N } bits is 1006instanciate only once for these { \it N } bits... 1007 1008\subsection{Example of description with genlib macro-functions} 1009 1010Let us consider the following circuit: 1011 1012\begin{figure}[H]\center 1013\leavevmode 1014\includegraphics[width=10cm]{exemple2} 1015\end{figure} 1016 1017Here the corresponding data-path structure : 1018\begin{figure}[H]\center \leavevmode 1019\includegraphics[width=10cm]{datap} 1020\end{figure} 1021 1022Each gate occupies a column, a column making it possible to treat 1023a whole of bits for the same operator. The first line represents bit 3, the last bit 0 . 1024 1025\newpage 1026 1027The file { \bf genlib } correspondent is as follows: 1028 1029\begin{sourcelisting} 1030#include <genlib.h> 1031 main() 1032 { 1033 GENLIB_DEF_LOFIG("data_path"); 1034 1035 /* connectors declaration */ 1036 GENLIB_LOCON("a[3:0]",IN,"a[3:0]"); 1037 GENLIB_LOCON("b[3:0]",IN,"b[3:0]"); 1038 GENLIB_LOCON("c[3:0]",IN,"c[3:0]"); 1039 GENLIB_LOCON("v",IN,"w"); 1040 GENLIB_LOCON("cout",OUT,"ct"); 1041 GENLIB_LOCON("s[3:0]",OUT,"s[3:0]"); 1042 GENLIB_LOCON("cmd",IN,"cmd"); 1043 GENLIB_LOCON("vdd",IN,"vdd"); 1044 GENLIB_LOCON("vss",IN,"vss"); 1045 1046 /* operators creation */ 1047 GENLIB_MACRO(GEN_NAND2, "model_nand2_4bits", F_PLACE, 4, 1); 1048 GENLIB_MACRO(GEN_OR2, "model_or2_4bits", F_PLACE, 4); 1049 GENLIB_MACRO(GEN_ADSB2F, "model_add2_4bits", F_PLACE, 4); 1050 1051 /* operators Instanciation */ 1052 GENLIB_LOINS("model_nand2_4bits", "model_nand2_4bits", 1053 "v", "v", "v", "v", 1054 "a[3:0]", 1055 "d_aux[3:0]", 1056 vdd, vss, NULL); 1057 GENLIB_LOINS("model_or2_4bits", "model_or2_4bits", 1058 "d_aux[3:0]", 1059 "b[3:0]", 1060 "e_aux[3:0]", 1061 vdd, vss, NULL); 1062 GENLIB_LOINS("model_add2_4bits", "model_add2_4bits", 1063 "cmd", 1064 "cout", 1065 "ovr", 1066 "e_aux[3:0]", 1067 "c[3:0]", 1068 "s[3:0]", 1069 vdd, vss, NULL); 1070 1071 /* Save of figure */ 1072 GENLIB_SAVE_LOFIG(); 1073 exit(0); 1074 } 1075\end{sourcelisting} 1076 1077 1078Save it under the name `` data\_path.c '', then compile the file 1079with the command: 1080 1081\begin{commandline} 1082> genlib data_path 1083\end{commandline} 1084 1085You obtain the file `` data\_path.vst '' (in the contrary case, it 1086may be that your environment is badly configured for { \bf genlib 1087}).In this case, 1088pass to the section `` Data path description''.\\ 1089 1090{\bf Note:} { \bf genlib } can also create the physical placement 1091(the drawing) of a structural description .\\ 1092 1093\subsection{Data-path description} 1094 1095The diagrams corresponding to the signals list to design are 1096given. %To supplement the file `` amd2901\_dpt.c '' then 1097Compile it following the steps below .\\ 1098 1099%Positionner les variables d'environnement sp\'ecifiant les formats des diff\'erentes vues ainsi que les librairies de cellules utilis\'ees.\\ 1100% 1101%\myfbox{ 1102%\shortstack[l]{ 1103%{\bf $>$ setenv MBK\_CATA\_LIB .:\$ALLIANCE\_TOP/cells/sxlib:}\\ 1104%{\bf \$ALLIANCE\_TOP/cells/padlib: \$ALLIANCE\_TOP/cells/fplib:}\\ 1105%{\bf \$ALLIANCE\_TOP/cells/rfg}\\ 1106%{\bf $>$ setenv MBK\_CATAL\_NAME CATAL}\\ 1107%{\bf $>$ setenv FPGEN\_LIB ./colonnes} 1108%} 1109%}\\ 1110 1111 1112Generate the signals list { \bf vst } starting from the { \bf c } file, 1113 using the command: \\ 1114\ \\ 1115\begin{commandline} 1116> genlib amd2901_dpt 1117\end{commandline} 1118 1119Validate the netlist in the same way as it has been done for the control part. 1120Remove CATAL file and simulate the circuit with { \bf asimut }. 1121 1122\begin{commandline} 1123> asimut -zerodelay amd2901_chip pattern result 1124\end{commandline} 1125\\ 1126 1127%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 1128 1129 1130 1131\newpage 1132 1133\section{The { \it Makefile } or how to manage tasks dependencies } 1134%------------------------------------------------------------------------------- 1135 1136The synthesis under { \bf Alliance } breaks up into several tools 1137being carried out chronologically on a data flow. Each tool has 1138its own options giving the results more or less adapted 1139according to the use of the circuit. 1140 1141 1142\begin{figure}[H]\centering 1143 \includegraphics[]{synthese.eps} 1144 \caption{the synthesis} 1145 \label{Fig: the synthesis} 1146\end{figure} 1147 1148\begin{figure} 1149\end{figure} 1150 1151The data dependency in the flow are materialized in reality by 1152file dependency. The file {\bf Makefile} carried out using the 1153command {\bf make} makes it possible to manage these dependencies. 1154 1155\subsubsection{Rules} 1156%---------------------------------------------------- 1157A {\bf Makefile} is a file containing one or more rules 1158translating the dependency between the actions and the files. 1159 1160example : 1161 1162\begin{sourcelisting} 1163target1 : dependence1 dependence2 .... 1164 #Rq: each command must be preceded by a tabulation 1165 command_X 1166 command_Y 1167 . 1168 . 1169 . 1170\end{sourcelisting} 1171 1172The dependencies and targets represent files in general. \\ 1173Only the first rule (except the models cf \ref{models}) of the 1174{\bf Makefile} is examined. 1175The following rules are ignored if they are not implied by the first. \\ 1176So some dependencies of a rule { \bf X } are themselves of the 1177rules in the { \bf Makefile } 1178then these last will be examined before the appealing rule { \bf X }. \\ 1179For each rule { \bf X } examined, so at least one of its 1180dependencies is more recent than its target then the commands of 1181the rule { \bf X } will be carried out. 1182{ \it Note:: } the commands are generally used to produce the target (i.e a new file). \\ 1183A target should not represent a file. In this case, the commands 1184of this rule will be always carried out. 1185 1186 1187\subsubsection{\label{models}models Rules} 1188%----------------------------------------- 1189These rules are more general-purpose because you can specify more 1190complex dependency rules. A model rule be similar to a normal 1191rule, except a symbol (\%) appears in the target name. The 1192dependencies also employ (\%) to indicate the relation between the 1193dependency name and the target name. The following model rule 1194specifies how all the files { \bf vst } are formed starting from 1195the { \bf vbe }. 1196 1197\begin{sourcelisting} 1198#example of rule for the synthesis 1199%.vst : %.vbe 1200 boog $* 1201\end{sourcelisting} 1202%\normalsize 1203 1204\subsubsection{Variables definitions } 1205%---------------------------------------------------- 1206You can define variables in any place of the file { \bf Makefile 1207}, but for legibility we will define them at the beginning of 1208file. 1209 1210\begin{sourcelisting} 1211#variables definitions 1212MY_COPY = cp -r 1213MY_NUM = 42 1214MY_STRING ="hello" 1215\end{sourcelisting} 1216 1217They are usable in any place of the { \bf Makefile }. They must be 1218preceded by the character { \bf \$ } 1219 1220\begin{sourcelisting} 1221#use a variable in a rule 1222 1223copy: 1224 ${MY_COPY} digicode.vbe tmp/ 1225\end{sourcelisting} 1226 1227\subsubsection{Predefined variables} 1228%----------------------------------------- 1229 1230\begin{itemize}\itemsep=-.8ex 1231\item {\bf \$@} ~~Complete target name. 1232\item {\bf \$*} ~~Name of the targets file without the extension. 1233\item {\bf \$<} ~~Name of the first dependent file. 1234\item {\bf \$+} ~~Names of all the dependent files with double dependencies indexed 1235 in their order of appearance. 1236\item {\bf \$\verb1^1 } ~~Names of all the dependent files. The doubles are remote. 1237\item {\bf \$?} ~~Names of all the dependent files more recent than the target. 1238\item {\bf \$\%} ~~Name of member for targets which are archives (language C). 1239 If, for example, the target is { \it libDisp.a(image.o) }, 1240 { \bf \$\%} is { \it image.o } and { \bf \$@ } is { \it libDisp.a }. 1241\end{itemize} 1242 1243\newpage 1244\section{Appendix: Diagrams as an indication but not-in conformity with the behavioral} 1245 1246\begin{figure}[H]\center 1247\leavevmode 1248\includegraphics[width=12cm]{ctl-mrs-1} 1249\end{figure} 1250\begin{figure}[H]\center 1251\leavevmode 1252\includegraphics[width=12cm]{ctl-alu-1} 1253\end{figure} 1254\begin{figure}[H]\center 1255\leavevmode 1256\includegraphics[width=12cm]{ctl-wen-1} 1257\end{figure} 1258\begin{figure}[H]\center 1259\leavevmode 1260\includegraphics[width=10cm]{dpt-all-1} 1261\end{figure} 1262 1263\begin{figure}[H]\center 1264\leavevmode 1265\includegraphics[width=12cm]{dpt-alu-1} 1266\end{figure} 1267 1268\begin{figure}[H]\center 1269\leavevmode 1270\includegraphics[width=12cm]{ctldecode} 1271\end{figure} 1272 1273\begin{figure}[H]\center 1274\leavevmode 1275\includegraphics[width=12cm]{ctldecodebw} 1276\end{figure} 1277 1278\begin{figure}[H]\center 1279\leavevmode 1280\includegraphics[width=12cm]{dptbanc} 1281\end{figure} 1282 1283\end{document} 1284