1library ieee; 2 use ieee.std_logic_1164.all; 3 4 5entity sequencer is 6 generic ( 7 seq : string 8 ); 9 port ( 10 clk : in std_logic; 11 data : out std_logic 12 ); 13end entity sequencer; 14 15 16architecture rtl of sequencer is 17 18 signal index : natural := seq'low; 19 signal ch : character; 20 21 function to_bit (a : in character) return std_logic is 22 variable ret : std_logic; 23 begin 24 case a is 25 when '0' | '_' => ret := '0'; 26 when '1' | '-' => ret := '1'; 27 when others => ret := 'X'; 28 end case; 29 return ret; 30 end function to_bit; 31 32begin 33 34 35 process (clk) is 36 begin 37 if rising_edge(clk) then 38 if (index < seq'high) then 39 index <= index + 1; 40 end if; 41 end if; 42 end process; 43 44 ch <= seq(index); 45 46 data <= to_bit(ch); 47 48 49end architecture rtl; 50 51 52library ieee; 53 use ieee.std_logic_1164.all; 54 55 56entity psl_next_event_a is 57end entity psl_next_event_a; 58 59 60architecture psl of psl_next_event_a is 61 signal clk : std_logic := '0'; 62 63 component sequencer is 64 generic ( 65 seq : string 66 ); 67 port ( 68 clk : in std_logic; 69 data : out std_logic 70 ); 71 end component sequencer; 72 73 signal a, b, c : std_logic; 74 75begin 76 77 -- 012345678901234 78 SEQ_A : sequencer generic map ("_-______________-____") port map (clk, a); 79 SEQ_B : sequencer generic map ("--___--__----________") port map (clk, b); 80 SEQ_C : sequencer generic map ("_____-___---_____----") port map (clk, c); 81 82 83 -- All is sensitive to rising edge of clk 84 default clock is rising_edge(clk); 85 86 -- This assertion holds 87 assert_NEXT_EVENT_a : assert always ((a and b) -> next_event_a(c)[1 to 4](b)); 88 89 process 90 begin 91 for i in 1 to 2*20 loop 92 wait for 1 ns; 93 clk <= not clk; 94 end loop; 95 wait; 96 end process; 97 98end architecture psl; 99