1library ieee; 2use ieee.std_logic_1164.all; 3use ieee.numeric_std.all; 4use ieee.fixed_pkg.all; 5use ieee.std_logic_textio.all; 6use std.textio.all; 7 8library work; 9use work.test_pkg.all; 10 11 12entity test_bench is 13 14end entity; 15 16 17architecture bench of test_bench is 18 signal counter : natural range 0 to 1000; 19 signal my_signal : sfixed(0 downto -15); 20 signal my_array : t_sf_array(0 to 15)(0 downto -15) := do_something(16, my_signal); 21 signal s_rst : std_logic := '1'; 22 signal s_clk : std_logic := '1'; 23 24begin 25 s_rst <= '0' after 50 ns; 26 s_clk <= not s_clk after 10 ns; 27 28 write_result : process (s_rst, s_clk) is 29 file test_file : text open write_mode is "output.txt"; 30 variable wrline : line; 31 variable linenum : integer := 0; 32 begin 33 if (s_rst = '1') then 34 linenum := 0; 35 elsif (rising_edge(s_clk) and counter < 16) then 36 write(wrline, real'image(to_real(my_array(counter)))); 37 writeline(test_file, wrline); 38 end if; 39 end process; 40end architecture; 41