1library ieee;
2use ieee.std_logic_1164.all;
3
4
5library ieee;
6use ieee.numeric_std.all;
7
8entity output_split1 is
9	port (
10		wa0_data : in  std_logic_vector(7 downto 0);
11		wa0_addr : in  std_logic_vector(2 downto 0);
12		ra0_data : out std_logic_vector(7 downto 0);
13		ra0_addr : in  std_logic_vector(2 downto 0);
14		wa0_en : in  std_logic;
15		clk : in  std_logic
16	);
17end output_split1;
18architecture augh of output_split1 is
19
20	-- Embedded RAM
21
22	type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
23	signal ram : ram_type := (others => (others => '0'));
24
25
26	-- Little utility functions to make VHDL syntactically correct
27	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
28	--   This happens when accessing arrays with <= 2 cells, for example.
29
30	function to_integer(B: std_logic) return integer is
31		variable V: std_logic_vector(0 to 0);
32	begin
33		V(0) := B;
34		return to_integer(unsigned(V));
35	end;
36
37	function to_integer(V: std_logic_vector) return integer is
38	begin
39		return to_integer(unsigned(V));
40	end;
41
42begin
43
44	-- Sequential process
45	-- It handles the Writes
46
47	process (clk)
48	begin
49		if rising_edge(clk) then
50
51			-- Write to the RAM
52			-- Note: there should be only one port.
53
54			if wa0_en = '1' then
55				ram( to_integer(wa0_addr) ) <= wa0_data;
56			end if;
57
58		end if;
59	end process;
60
61	-- The Read side (the outputs)
62
63	ra0_data <= ram( to_integer(ra0_addr) );
64
65end architecture;
66