README
1
2 This is the "ieee_proposed" library. This is a compatability library,
3which is designed to provide all of the functionality of the VHDL-200X-FT
4packages in VHDL-93. The "_c" after the package name is used to denote
5that this is a 1993 compliant version of this package. Otherwise, the
6name of the file and the name of the package are the same.
7
8Please compile the following files into a library named "ieee_proposed":
9standard_additions_c.vhdl
10env_c.vhdl
11standard_textio_additions_c.vhdl
12std_logic_1164_additions.vhdl
13numeric_std_additions.vhdl
14numeric_std_unsigned_c.vhdl
15fixed_pkg_c.vhdl
16float_pkg_c.vhdl
17
18
19New/Updated functions
20A) standard_additions -- Additions to the package "std.standard"
21 Use model:
22 use ieee_proposed.standard_additions.all;
23 Dependancies: None.
24 Notes: The functions "rising_edge" and "falling_edge" are defined in
25 this package. If you use "numeric_bit" they are ALSO defined in that
26 package, causing a conflict. The VHDL-2008 version of numeric_bit
27 has these functions commented out, as well as the "sll", "srl", "ror"
28 and "rol" functions which are implicit.
29 New types defined in this package:
30 REAL_VECTOR
31 TIME_VECTOR
32 INTEGER_VECTOR
33 BOOLEAN_VECTOR
34 New constants defined in this package:
35 SIM_RESOLUTION : TIME - returns the simulator's resolution (1 ns default)
36 1) "maximum" and "minimum" are defined for all default datatypes
37 2) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
38 These functions reduce a bit_vector to a single bit. Example:
39 or_reduce ("0101") = '1'. In VHDL-2008 syntax these will be "or".
40 3) "vector" and "bit" operations are defined. These will perform a
41 boolean operation of a vector. Example:
42 "1" xor "1010" = "0101";
43 5) /??/ function is defined for "bit" ("??" operator is release)
44 if (/??/('1')) then -- will return a "true".
45 6) rising_edge and falling_edge functions are defined (see Notes).
46 7) to_string function - Converts any of the base types into a string.
47 Example:
48 assert (bv = "101") report "result was " & to_string(bv) severity note;
49 8) to_hstring and to_ostring function (bit_vector to hex or octal string)
50B) standard_textio_additions - Additions to the package "std.textio"
51 Use model:
52 use ieee_proposed.standard_textio_additions.all;
53 Dependencies: std.textio, ieee_proposed.standard_additions
54 1) tee - Echos the string to BOTH the file and the screen
55 2) SREAD and SWRITE - String read and write routines (so you no longer
56 need to do write (L, string'("ABCEDFG"));
57 3) HREAD and HWRITE (Hex read and write) for bit_vector
58 4) OREAD and OWRITE (octal read and write) for bit_vector
59 5) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
60 bit_vector
61 6) justify - Justify a string left or right with a width. Example:
62 justify ("ABCD", left, 6); will result in "ABCD "
63C) std_logic_1164_additions - Additions to the package "ieee.std_logic_1164"
64 Usage model:
65 use ieee.std_logic_1164.all;
66 -- use ieee.std_logic_textio.all; -- Comment out, included in "_additions".
67 use ieee_proposed.std_logic_1164_additions.all;
68 Dependencies: ieee.std_logic_1164
69 Note: The contents of the "std_logic_textio" package have now been
70 included in the "std_logic_1164" package, and an EMPTY "std_logic_textio"
71 package is provided in the new release.
72 1) Short had aliases:
73 a) to_bv - calls "to_BitVector"
74 b) to_slv - calls "to_StdLogicVector"
75 c) to_sulv - calls "to_stdULogicVector"
76 2) Long hand aliases:
77 a) to_bit_vector - calls "to_BitVector"
78 b) to_std_logic_vector - calls "to_StdLogicVector"
79 c) to_std_ulogic_vector - calls "to_StdULogicVector"
80 3) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
81 These functions reduce a std_logic_vector (or ulogic) to a single bit.
82 In vhdl-2006 these will be unary "or", example "or "11011" = '1'"
83 4) "vector" and "std_ulogic" operations are defined. These will perform a
84 boolean operation of a vector. Example:
85 "1" xor "1010" = "0101";
86 5) "std_ulogic" and "boolean" operations are defined. Thus:
87 if '1' and true then -- returns a "true".
88 6) "\??\" function is defined for "std_ulogic" ("??" operator is release)
89 if (bool('1')) then -- will return a "true".
90 7) READ and WRITE procedures for "std_logic_vector", "std_ulogic_vector"
91 and "std_ulogic" are defined.
92 8) HREAD and HWRITE (Hex read and write) for std_logic_vector
93 and std_ulogic_vector. These are more "forgiving" than the ones
94 originally from "std_logic_textio"
95 9) OREAD and OWRITE (octal read and write) for std_logic_vector
96 and std_ulogic_vector. These are more "forgiving" than the ones
97 originally from "std_logic_textio"
98 10) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
99 std_logic_vector and std_ulogic_vector.
100 11) to_string function - Converts a "std_ulogic", "std_logic_vector" or
101 "std_ulogic_vector" types into a string.
102 Example:
103 assert (slv = "101") report "result was " & to_string(slv) severity note;
104 12) to_hstring and to_ostring function (std_(u)logic_vector to hex or octal
105 string)
106D) numeric_std_additions - additions the the package "ieee.numeric_std"
107 Usage Model:
108 use ieee.std_logic_1164.all;
109 use ieee.numeric_std.all;
110 use ieee_proposed.numeric_std_additions.all;
111 Dependencies: ieee.std_logic_1164, ieee.numeric_std
112 1) SIGNED or UNSIGNED + std_ulogic operators
113 2) SIGNED or UNSIGNED - std_ulogic operators
114 3) type UNRESOLVED_UNSIGNED (aliased to U_UNSIGNED) is an unresolved
115 verion of UNSIGNED. It is aliased to "UNSIGNED" for compatability.
116 4) type UNRESOLVED_SIGNED (aliased to U_SIGNED) is an unresolved
117 verion of SIGNED. It is aliased to "SIGNED" for compatability.
118 5) \?=\, \?/=\ - similar to "std_match", but return std_ulogic values.
119 \?<\, \?<=\, \?>\, \?>=\ - compare functions which retrun std_ulogic.
120 (these will be "?="... operators in the release)
121 7) To_X01, To_X01Z, To_U01X, Is_X - same as std_logic_1164 functions,
122 but overloaded for SIGNED and UNSIGNED.
123 8) "sla" and "sra" - Mathmetically correct versions of these functions.
124 9) minimum and maximum - smaller or larger of two SIGNED or UNSIGNED values.
125 10) find_rightmost and find_leftmost - finds the first bit in a string.
126 Example:
127 find_leftmost (c12, '1'); -- returns the Log2 of "c12".
128 returns -1 if not found.
129 11) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
130 These functions reduce a SIGNED or an UNSIGNED to a single bit.
131 (will overload the "or" and "and", ... operators in the release)
132 12) SIGNED or UNSIGNED and "std_ulogic" operations are defined.
133 These will perform a boolean operation of a vector. Example:
134 "1" xor "1010" = "0101";
135 13) READ and WRITE procedures for "SIGNED", and "UNSIGNED" are defined.
136 14) HREAD and HWRITE (Hex read and write) for SIGNED and UNSIGNED.
137 These are more "forgiving" than the ones
138 originally from "std_logic_textio"
139 15) OREAD and OWRITE (octal read and write) for "SIGNED" and "UNSIGNED.
140 These are more "forgiving" than the ones
141 originally from "std_logic_textio"
142 16) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
143 SIGNED and UNSIGNED.
144 17) to_string function - Converts a "SIGNED" or "UNSIGNED" types into a
145 string. Example:
146 assert (UNS = "101") report "result was " & to_string(UNS) severity note;
147 18) to_hstring and to_ostring function (SIGNED or UNSIGNED to hex or octal
148 string)
149E) numeric_std_unsigned - Simular to the "std_logic_unsigned" packages, but
150 with all of the functionality of the "numeric_std" package.
151 use model:
152 use ieee.std_logic_1164.all;
153 use ieee_proposed.numeric_std_unsigned.all;
154 dependencies: ieee.numeric_std, ieee_proposed.numeric_std_additions
155
156F) For fixed point package:
157use model:
158use ieee.std_logic_1164.all;
159use ieee.numeric_std.all;
160use ieee_proposed.math_utility_pkg.all;
161use ieee_proposed.fixed_pkg.all;
162See fixed point package documentation
163http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Fixed_ug.pdf [DEAD LINK]
164
165G) For floating point package:
166use model:
167use ieee.std_logic_1164.all;
168use ieee.numeric_std.all;
169use ieee_proposed.math_utility_pkg.all;
170use ieee_proposed.fixed_pkg.all;
171use ieee_proposed.float_pkg.all;
172See floating point package documentation
173http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Float_ug.pdf [DEAD LINK]
174