1library ieee;
2use ieee.std_logic_1164.all;
3use ieee.numeric_std.all;
4use ieee.math_real.all;
5
6entity test is
7    generic(
8        ROW_BITS : integer := 8;
9        WIDTH    : integer := 16
10        );
11
12    port(
13        clk     : in  std_logic;
14        rd_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
15        rd_data : out std_logic_vector(WIDTH - 1 downto 0);
16        wr_en   : in  std_logic;
17        wr_sel  : in  std_logic_vector(WIDTH/8 - 1 downto 0);
18        wr_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
19        wr_data : in  std_logic_vector(WIDTH - 1 downto 0)
20        );
21
22end test;
23
24architecture rtl of test is
25    constant SIZE : integer := 2**ROW_BITS;
26
27    type ram_type is array (0 to SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0);
28    signal ram : ram_type;
29
30begin
31    process(clk)
32        variable lbit : integer range 0 to WIDTH - 1;
33        variable mbit : integer range 0 to WIDTH - 1;
34        variable widx : integer range 0 to SIZE - 1;
35    begin
36        if rising_edge(clk) then
37            if wr_en = '1' then
38                for i in 0 to WIDTH/8-1 loop
39                    lbit := i * 8;
40                    mbit := lbit + 7;
41                    widx := to_integer(unsigned(wr_addr));
42                    if wr_sel(i) = '1' then
43                        ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit);
44                    end if;
45                end loop;
46            end if;
47
48            rd_data <= ram(to_integer(unsigned(rd_addr)));
49        end if;
50    end process;
51end;
52