1
2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20-- ---------------------------------------------------------------------
21--
22-- $Id: ap_a_ap_a_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
23-- $Revision: 1.2 $
24--
25-- ---------------------------------------------------------------------
26
27entity ap_a_02 is
28
29end entity ap_a_02;
30
31
32library ieee;  use ieee.std_logic_1164.all;
33
34architecture test of ap_a_02 is
35
36  -- code from book
37
38  -- end code from book
39
40begin
41
42  b1 : block is
43               signal sulv : std_ulogic_vector(7 downto 0);
44             signal slv : std_logic_vector(7 downto 0);
45  begin
46    -- code from book
47
48    sulv <= To_stdulogicvector ( slv );
49
50    -- end code from book
51    slv <= "10101010";
52  end block b1;
53
54  b2 : block is
55               signal sulv : std_ulogic_vector(7 downto 0);
56             signal slv : std_logic_vector(7 downto 0);
57  begin
58    -- code from book
59
60    slv <= To_stdlogicvector ( sulv );
61
62    -- end code from book
63    sulv <= "00001111";
64  end block b2;
65
66  b3 : block is
67               signal a, ena, y : std_logic;
68  begin
69    -- code from book
70
71    y <= a when ena = '1' else
72         'Z';
73
74    -- end code from book
75    ena <= '0', '1' after 20 ns, '0' after 40 ns;
76    a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;
77  end block b3;
78
79  b4 : block is
80               signal a, ena, y : std_logic;
81  begin
82    -- code from book
83
84    y <= a when ena = '1' else
85         'H';
86
87    -- end code from book
88    ena <= '0', '1' after 20 ns, '0' after 40 ns;
89    a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;
90  end block b4;
91
92  b5 : block is
93               signal a, b, x, s, y : std_logic;
94  begin
95    -- code from book
96
97    y <= a when x = '1' else
98         b when s = '1' else
99         '-';
100
101    -- end code from book
102    x <= '0', '1' after 20 ns, '0' after 40 ns;
103    s <= '0', '1' after 60 ns, '0' after 80 ns;
104    a <= '0', '1' after 10 ns, '0' after 30 ns,
105         '1' after 50 ns, '0' after 70 ns,
106         '1' after 90 ns;
107    b <= '0', '1' after 15 ns, '0' after 35 ns,
108         '1' after 55 ns, '0' after 75 ns,
109         '1' after 95 ns;
110  end block b5;
111
112end architecture test;
113
114