1
2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20-- ---------------------------------------------------------------------
21--
22-- $Id: ap_a_ap_a_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
23-- $Revision: 1.2 $
24--
25-- ---------------------------------------------------------------------
26
27library ieee;  use ieee.std_logic_1164.all;
28
29               entity bidir_buffer is
30                 port ( bidir : inout std_logic_vector;
31                        ena : in std_ulogic;
32                        going_out : in std_ulogic_vector;
33                        coming_in : out std_ulogic_vector );
34               end entity bidir_buffer;
35
36--------------------------------------------------
37
38               architecture behavior of bidir_buffer is
39-- code from book
40
41                 constant hi_impedance : std_logic_vector(bidir'range) := (others => 'Z');
42                 -- . . .
43
44-- end code from book
45               begin
46-- code from book
47
48                 bidir <= To_stdlogicvector(going_out) when ena = '1' else
49                          hi_impedance;
50                 coming_in <= To_stdulogicvector(bidir);
51
52-- end code from book
53               end architecture behavior;
54
55
56
57               entity ap_a_07 is
58               end entity ap_a_07;
59
60
61               library ieee;  use ieee.std_logic_1164.all;
62               architecture test of ap_a_07 is
63
64                 signal bidir : std_logic_vector(3 downto 0);
65                 signal going_out, coming_in : std_ulogic_vector(3 downto 0);
66                 signal ena : std_ulogic;
67
68               begin
69
70                 dut : entity work.bidir_buffer
71                   port map ( bidir, ena, going_out, coming_in );
72
73                 ena <= '0', '1' after 10 ns, '0' after 30 ns;
74
75                 going_out <= "0000", "1111" after 20 ns;
76
77                 bidir <= "ZZZZ", "0000" after 40 ns, "1111" after 50 ns, "ZZZZ" after 60 ns;
78
79               end architecture test;
80