1
2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20-- ---------------------------------------------------------------------
21--
22-- $Id: ap_a_fg_a_06.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
23-- $Revision: 1.1.1.1 $
24--
25-- ---------------------------------------------------------------------
26
27entity fg_a_06 is
28
29end entity fg_a_06;
30
31
32library ieee;  use ieee.std_logic_1164.all;
33
34architecture test of fg_a_06 is
35
36  -- code from book
37
38  constant terminal_count : integer := 2**6 - 1;
39  subtype counter_range is integer range 0 to terminal_count;
40  signal count : counter_range;
41  -- . . .
42
43  -- end code from book
44
45  signal clk, reset : std_ulogic;
46
47begin
48
49  -- code from book
50
51  counter6 : process (reset, clk)
52  begin
53    if reset = '0' then
54      count <= 0;
55    elsif rising_edge(clk) then
56      if count < terminal_count then
57        count <= count + 1;
58      else
59        count <= 0;
60      end if;
61    end if;
62  end process counter6;
63
64  -- end code from book
65
66  stimulus : process is
67  begin
68    reset <= '1';  clk <= '0';  wait for 10 ns;
69    clk <= '1', '0' after 10 ns;  wait for 20 ns;
70    clk <= '1', '0' after 10 ns;  wait for 20 ns;
71    clk <= '1', '0' after 10 ns;  wait for 20 ns;
72    reset <= '0', '1' after 30 ns;
73    clk <= '1' after 10 ns, '0' after 20 ns;
74    wait for 40 ns;
75    for i in 1 to terminal_count + 10 loop
76      clk <= '1', '0' after 10 ns;
77      wait for 20 ns;
78    end loop;
79
80    wait;
81  end process stimulus;
82
83end architecture test;
84
85