1 2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20-- --------------------------------------------------------------------- 21-- 22-- $Id: ch_03_ch_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $ 23-- $Revision: 1.3 $ 24-- 25-- --------------------------------------------------------------------- 26 27entity ch_03_04 is 28end entity ch_03_04; 29 30architecture test of ch_03_04 is 31 32 type opcode_type is (opcode_1, opcode_2, halt_opcode); 33 signal opcode : opcode_type := opcode_1; 34 35 signal halt_indicator : boolean := false; 36 37begin 38 39 process_3_1_d : process (opcode) is 40 41 variable PC : integer := 0; 42 constant effective_address : integer := 1; 43 variable executing : boolean := true; 44 45 begin 46 47 -- code from book: 48 49 if opcode = halt_opcode then 50 PC := effective_address; 51 executing := false; 52 halt_indicator <= true; 53 end if; 54 55 -- end of code from book 56 57 end process process_3_1_d; 58 59 stimulus : process is 60 begin 61 opcode <= opcode_2 after 100 ns, halt_opcode after 200 ns; 62 wait; 63 end process stimulus; 64 65end architecture test; 66