1 2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20-- --------------------------------------------------------------------- 21-- 22-- $Id: ch_06_reg.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ 23-- $Revision: 1.2 $ 24-- 25-- --------------------------------------------------------------------- 26 27library ieee; use ieee.std_logic_1164.all; 28 29 entity reg is 30 port ( clk : in std_ulogic; 31 d : in std_ulogic_vector; 32 q : out std_ulogic_vector ); 33 end entity reg; 34